2 * Copyright (c) 2010 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 #include "arch/arm/faults.hh"
49 #include "arch/arm/pagetable.hh"
50 #include "arch/arm/system.hh"
51 #include "arch/arm/table_walker.hh"
52 #include "arch/arm/tlb.hh"
53 #include "arch/arm/utility.hh"
54 #include "base/inifile.hh"
55 #include "base/str.hh"
56 #include "base/trace.hh"
57 #include "cpu/thread_context.hh"
58 #include "debug/Checkpoint.hh"
59 #include "debug/TLB.hh"
60 #include "debug/TLBVerbose.hh"
61 #include "mem/page_table.hh"
62 #include "params/ArmTLB.hh"
63 #include "sim/full_system.hh"
64 #include "sim/process.hh"
67 using namespace ArmISA
;
69 TLB::TLB(const Params
*p
)
70 : BaseTLB(p
), size(p
->size
) , tableWalker(p
->walker
),
71 rangeMRU(1), bootUncacheability(false), miscRegValid(false)
73 table
= new TlbEntry
[size
];
74 memset(table
, 0, sizeof(TlbEntry
) * size
);
76 tableWalker
->setTlb(this);
86 TLB::translateFunctional(ThreadContext
*tc
, Addr va
, Addr
&pa
)
90 TlbEntry
*e
= lookup(va
, contextId
, true);
98 TLB::lookup(Addr va
, uint8_t cid
, bool functional
)
101 TlbEntry
*retval
= NULL
;
103 // Maitaining LRU array
106 while (retval
== NULL
&& x
< size
) {
107 if (table
[x
].match(va
, cid
)) {
109 // We only move the hit entry ahead when the position is higher than rangeMRU
111 TlbEntry tmp_entry
= table
[x
];
112 for(int i
= x
; i
> 0; i
--)
113 table
[i
] = table
[i
-1];
114 table
[0] = tmp_entry
;
124 DPRINTF(TLBVerbose
, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n",
125 va
, cid
, retval
? "hit" : "miss", retval
? retval
->pfn
: 0,
126 retval
? retval
->size
: 0, retval
? retval
->pAddr(va
) : 0,
127 retval
? retval
->ap
: 0);
132 // insert a new TLB entry
134 TLB::insert(Addr addr
, TlbEntry
&entry
)
136 DPRINTF(TLB
, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x"
137 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x"
138 " domain:%#x\n", entry
.pfn
, entry
.size
, entry
.vpn
, entry
.asid
,
139 entry
.N
, entry
.global
, entry
.valid
, entry
.nonCacheable
, entry
.sNp
,
140 entry
.xn
, entry
.ap
, entry
.domain
);
142 if (table
[size
-1].valid
)
143 DPRINTF(TLB
, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n",
144 table
[size
-1].vpn
<< table
[size
-1].N
, table
[size
-1].asid
,
145 table
[size
-1].pfn
<< table
[size
-1].N
, table
[size
-1].size
,
148 //inserting to MRU position and evicting the LRU one
150 for(int i
= size
-1; i
> 0; i
--)
151 table
[i
] = table
[i
-1];
162 DPRINTF(TLB
, "Current TLB contents:\n");
166 DPRINTF(TLB
, " * %#x, asn %d ppn %#x size: %#x ap:%d\n",
167 te
->vpn
<< te
->N
, te
->asid
, te
->pfn
<< te
->N
, te
->size
, te
->ap
);
176 DPRINTF(TLB
, "Flushing all TLB entries\n");
182 DPRINTF(TLB
, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
183 te
->vpn
<< te
->N
, te
->asid
, te
->pfn
<< te
->N
, te
->size
, te
->ap
);
189 memset(table
, 0, sizeof(TlbEntry
) * size
);
196 TLB::flushMvaAsid(Addr mva
, uint64_t asn
)
198 DPRINTF(TLB
, "Flushing mva %#x asid: %#x\n", mva
, asn
);
201 te
= lookup(mva
, asn
);
203 DPRINTF(TLB
, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
204 te
->vpn
<< te
->N
, te
->asid
, te
->pfn
<< te
->N
, te
->size
, te
->ap
);
207 te
= lookup(mva
,asn
);
213 TLB::flushAsid(uint64_t asn
)
215 DPRINTF(TLB
, "Flushing all entries with asid: %#x\n", asn
);
222 if (te
->asid
== asn
) {
224 DPRINTF(TLB
, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
225 te
->vpn
<< te
->N
, te
->asid
, te
->pfn
<< te
->N
, te
->size
, te
->ap
);
234 TLB::flushMva(Addr mva
)
236 DPRINTF(TLB
, "Flushing all entries with mva: %#x\n", mva
);
243 Addr v
= te
->vpn
<< te
->N
;
244 if (mva
>= v
&& mva
< v
+ te
->size
) {
246 DPRINTF(TLB
, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
247 te
->vpn
<< te
->N
, te
->asid
, te
->pfn
<< te
->N
, te
->size
, te
->ap
);
256 TLB::serialize(ostream
&os
)
258 DPRINTF(Checkpoint
, "Serializing Arm TLB\n");
260 SERIALIZE_SCALAR(_attr
);
262 int num_entries
= size
;
263 SERIALIZE_SCALAR(num_entries
);
264 for(int i
= 0; i
< size
; i
++){
265 nameOut(os
, csprintf("%s.TlbEntry%d", name(), i
));
266 table
[i
].serialize(os
);
271 TLB::unserialize(Checkpoint
*cp
, const string
§ion
)
273 DPRINTF(Checkpoint
, "Unserializing Arm TLB\n");
275 UNSERIALIZE_SCALAR(_attr
);
277 UNSERIALIZE_SCALAR(num_entries
);
278 for(int i
= 0; i
< min(size
, num_entries
); i
++){
279 table
[i
].unserialize(cp
, csprintf("%s.TlbEntry%d", section
, i
));
281 miscRegValid
= false;
288 .name(name() + ".inst_hits")
289 .desc("ITB inst hits")
293 .name(name() + ".inst_misses")
294 .desc("ITB inst misses")
298 .name(name() + ".inst_accesses")
299 .desc("ITB inst accesses")
303 .name(name() + ".read_hits")
304 .desc("DTB read hits")
308 .name(name() + ".read_misses")
309 .desc("DTB read misses")
313 .name(name() + ".read_accesses")
314 .desc("DTB read accesses")
318 .name(name() + ".write_hits")
319 .desc("DTB write hits")
323 .name(name() + ".write_misses")
324 .desc("DTB write misses")
328 .name(name() + ".write_accesses")
329 .desc("DTB write accesses")
333 .name(name() + ".hits")
338 .name(name() + ".misses")
343 .name(name() + ".accesses")
344 .desc("DTB accesses")
348 .name(name() + ".flush_tlb")
349 .desc("Number of times complete TLB was flushed")
353 .name(name() + ".flush_tlb_mva")
354 .desc("Number of times TLB was flushed by MVA")
358 .name(name() + ".flush_tlb_mva_asid")
359 .desc("Number of times TLB was flushed by MVA & ASID")
363 .name(name() + ".flush_tlb_asid")
364 .desc("Number of times TLB was flushed by ASID")
368 .name(name() + ".flush_entries")
369 .desc("Number of entries that have been flushed from TLB")
373 .name(name() + ".align_faults")
374 .desc("Number of TLB faults due to alignment restrictions")
378 .name(name() + ".prefetch_faults")
379 .desc("Number of TLB faults due to prefetch")
383 .name(name() + ".domain_faults")
384 .desc("Number of TLB faults due to domain restrictions")
388 .name(name() + ".perms_faults")
389 .desc("Number of TLB faults due to permissions restrictions")
392 instAccesses
= instHits
+ instMisses
;
393 readAccesses
= readHits
+ readMisses
;
394 writeAccesses
= writeHits
+ writeMisses
;
395 hits
= readHits
+ writeHits
+ instHits
;
396 misses
= readMisses
+ writeMisses
+ instMisses
;
397 accesses
= readAccesses
+ writeAccesses
+ instAccesses
;
401 TLB::translateSe(RequestPtr req
, ThreadContext
*tc
, Mode mode
,
402 Translation
*translation
, bool &delay
, bool timing
)
406 Addr vaddr
= req
->getVaddr();
407 uint32_t flags
= req
->getFlags();
409 bool is_fetch
= (mode
== Execute
);
410 bool is_write
= (mode
== Write
);
413 assert(flags
& MustBeOne
);
414 if (sctlr
.a
|| !(flags
& AllowUnaligned
)) {
415 if (vaddr
& flags
& AlignmentMask
) {
416 return new DataAbort(vaddr
, 0, is_write
, ArmFault::AlignmentFault
);
422 Process
*p
= tc
->getProcessPtr();
424 if (!p
->pTable
->translate(vaddr
, paddr
))
425 return Fault(new GenericPageTableFault(vaddr
));
426 req
->setPaddr(paddr
);
432 TLB::trickBoxCheck(RequestPtr req
, Mode mode
, uint8_t domain
, bool sNp
)
438 TLB::walkTrickBoxCheck(Addr pa
, Addr va
, Addr sz
, bool is_exec
,
439 bool is_write
, uint8_t domain
, bool sNp
)
445 TLB::translateFs(RequestPtr req
, ThreadContext
*tc
, Mode mode
,
446 Translation
*translation
, bool &delay
, bool timing
)
450 DPRINTF(TLBVerbose
, "TLB variables changed!\n");
453 Addr vaddr
= req
->getVaddr();
454 uint32_t flags
= req
->getFlags();
456 bool is_fetch
= (mode
== Execute
);
457 bool is_write
= (mode
== Write
);
458 bool is_priv
= isPriv
&& !(flags
& UserMode
);
460 req
->setAsid(contextId
.asid
);
462 DPRINTF(TLBVerbose
, "CPSR is priv:%d UserMode:%d\n",
463 isPriv
, flags
& UserMode
);
464 // If this is a clrex instruction, provide a PA of 0 with no fault
465 // This will force the monitor to set the tracked address to 0
466 // a bit of a hack but this effectively clrears this processors monitor
467 if (flags
& Request::CLEAR_LL
){
469 req
->setFlags(Request::UNCACHEABLE
);
470 req
->setFlags(Request::CLEAR_LL
);
473 if ((req
->isInstFetch() && (!sctlr
.i
)) ||
474 ((!req
->isInstFetch()) && (!sctlr
.c
))){
475 req
->setFlags(Request::UNCACHEABLE
);
478 assert(flags
& MustBeOne
);
479 if (sctlr
.a
|| !(flags
& AllowUnaligned
)) {
480 if (vaddr
& flags
& AlignmentMask
) {
482 return new DataAbort(vaddr
, 0, is_write
, ArmFault::AlignmentFault
);
490 req
->setPaddr(vaddr
);
491 if (sctlr
.tre
== 0) {
492 req
->setFlags(Request::UNCACHEABLE
);
494 if (nmrr
.ir0
== 0 || nmrr
.or0
== 0 || prrr
.tr0
!= 0x2)
495 req
->setFlags(Request::UNCACHEABLE
);
498 // Set memory attributes
500 tableWalker
->memAttrs(tc
, temp_te
, sctlr
, 0, 1);
501 temp_te
.shareable
= true;
502 DPRINTF(TLBVerbose
, "(No MMU) setting memory attributes: shareable:\
503 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te
.shareable
,
504 temp_te
.innerAttrs
, temp_te
.outerAttrs
);
505 setAttr(temp_te
.attributes
);
507 return trickBoxCheck(req
, mode
, 0, false);
510 DPRINTF(TLBVerbose
, "Translating vaddr=%#x context=%d\n", vaddr
, contextId
);
511 // Translation enabled
513 TlbEntry
*te
= lookup(vaddr
, contextId
);
515 if (req
->isPrefetch()){
516 //if the request is a prefetch don't attempt to fill the TLB
517 //or go any further with the memory access
519 return new PrefetchAbort(vaddr
, ArmFault::PrefetchTLBMiss
);
529 // start translation table walk, pass variables rather than
530 // re-retreaving in table walker for speed
531 DPRINTF(TLB
, "TLB Miss: Starting hardware table walker for %#x(%d)\n",
533 fault
= tableWalker
->walk(req
, tc
, contextId
, mode
, translation
,
535 if (timing
&& fault
== NoFault
) {
537 // for timing mode, return and wait for table walk
543 te
= lookup(vaddr
, contextId
);
556 // Set memory attributes
558 "Setting memory attributes: shareable: %d, innerAttrs: %d, \
560 te
->shareable
, te
->innerAttrs
, te
->outerAttrs
);
561 setAttr(te
->attributes
);
562 if (te
->nonCacheable
) {
563 req
->setFlags(Request::UNCACHEABLE
);
565 // Prevent prefetching from I/O devices.
566 if (req
->isPrefetch()) {
567 return new PrefetchAbort(vaddr
, ArmFault::PrefetchUncacheable
);
571 if (!bootUncacheability
&&
572 ((ArmSystem
*)tc
->getSystemPtr())->adderBootUncacheable(vaddr
))
573 req
->setFlags(Request::UNCACHEABLE
);
575 switch ( (dacr
>> (te
->domain
* 2)) & 0x3) {
578 DPRINTF(TLB
, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x"
579 " write:%d sNp:%d\n", dacr
, te
->domain
, is_write
, te
->sNp
);
581 return new PrefetchAbort(vaddr
,
582 (te
->sNp
? ArmFault::Domain0
: ArmFault::Domain1
));
584 return new DataAbort(vaddr
, te
->domain
, is_write
,
585 (te
->sNp
? ArmFault::Domain0
: ArmFault::Domain1
));
587 // Continue with permissions check
590 panic("UNPRED domain\n");
592 req
->setPaddr(te
->pAddr(vaddr
));
593 fault
= trickBoxCheck(req
, mode
, te
->domain
, te
->sNp
);
611 DPRINTF(TLB
, "Access permissions 0, checking rs:%#x\n", (int)sctlr
.rs
);
613 switch ((int)sctlr
.rs
) {
618 abt
= is_write
|| !is_priv
;
634 abt
= !is_priv
&& is_write
;
640 panic("UNPRED premissions\n");
642 abt
= !is_priv
|| is_write
;
649 panic("Unknown permissions\n");
651 if ((is_fetch
) && (abt
|| te
->xn
)) {
653 DPRINTF(TLB
, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d"
654 " write:%d sNp:%d\n", ap
, is_priv
, is_write
, te
->sNp
);
655 return new PrefetchAbort(vaddr
,
656 (te
->sNp
? ArmFault::Permission0
:
657 ArmFault::Permission1
));
660 DPRINTF(TLB
, "TLB Fault: Data abort on permission check. AP:%d priv:%d"
661 " write:%d sNp:%d\n", ap
, is_priv
, is_write
, te
->sNp
);
662 return new DataAbort(vaddr
, te
->domain
, is_write
,
663 (te
->sNp
? ArmFault::Permission0
:
664 ArmFault::Permission1
));
667 req
->setPaddr(te
->pAddr(vaddr
));
668 // Check for a trickbox generated address fault
669 fault
= trickBoxCheck(req
, mode
, te
->domain
, te
->sNp
);
677 TLB::translateAtomic(RequestPtr req
, ThreadContext
*tc
, Mode mode
)
682 fault
= translateFs(req
, tc
, mode
, NULL
, delay
, false);
684 fault
= translateSe(req
, tc
, mode
, NULL
, delay
, false);
690 TLB::translateTiming(RequestPtr req
, ThreadContext
*tc
,
691 Translation
*translation
, Mode mode
)
697 fault
= translateFs(req
, tc
, mode
, translation
, delay
, true);
699 fault
= translateSe(req
, tc
, mode
, translation
, delay
, true);
700 DPRINTF(TLBVerbose
, "Translation returning delay=%d fault=%d\n", delay
, fault
!=
703 translation
->finish(fault
, req
, tc
, mode
);
705 translation
->markDelayed();
712 return tableWalker
->getPort("port");
718 ArmTLBParams::create()
720 return new ArmISA::TLB(this);