2 * Copyright (c) 2010-2013 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
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12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
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18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 #include "arch/arm/tlb.hh"
51 #include "arch/arm/faults.hh"
52 #include "arch/arm/pagetable.hh"
53 #include "arch/arm/system.hh"
54 #include "arch/arm/table_walker.hh"
55 #include "arch/arm/stage2_lookup.hh"
56 #include "arch/arm/stage2_mmu.hh"
57 #include "arch/arm/utility.hh"
58 #include "base/inifile.hh"
59 #include "base/str.hh"
60 #include "base/trace.hh"
61 #include "cpu/base.hh"
62 #include "cpu/thread_context.hh"
63 #include "debug/Checkpoint.hh"
64 #include "debug/TLB.hh"
65 #include "debug/TLBVerbose.hh"
66 #include "mem/page_table.hh"
67 #include "params/ArmTLB.hh"
68 #include "sim/full_system.hh"
69 #include "sim/process.hh"
72 using namespace ArmISA
;
74 TLB::TLB(const ArmTLBParams
*p
)
75 : BaseTLB(p
), table(new TlbEntry
[p
->size
]), size(p
->size
),
76 isStage2(p
->is_stage2
), stage2Req(false), _attr(0),
77 directToStage2(false), tableWalker(p
->walker
), stage2Tlb(NULL
),
78 stage2Mmu(NULL
), rangeMRU(1),
79 aarch64(false), aarch64EL(EL0
), isPriv(false), isSecure(false),
80 isHyp(false), asid(0), vmid(0), dacr(0),
81 miscRegValid(false), miscRegContext(0), curTranType(NormalTran
)
83 tableWalker
->setTlb(this);
85 // Cache system-level properties
86 haveLPAE
= tableWalker
->haveLPAE();
87 haveVirtualization
= tableWalker
->haveVirtualization();
88 haveLargeAsid64
= tableWalker
->haveLargeAsid64();
99 if (stage2Mmu
&& !isStage2
)
100 stage2Tlb
= stage2Mmu
->stage2Tlb();
104 TLB::setMMU(Stage2MMU
*m
, MasterID master_id
)
107 tableWalker
->setMMU(m
, master_id
);
111 TLB::translateFunctional(ThreadContext
*tc
, Addr va
, Addr
&pa
)
115 if (directToStage2
) {
117 return stage2Tlb
->translateFunctional(tc
, va
, pa
);
120 TlbEntry
*e
= lookup(va
, asid
, vmid
, isHyp
, isSecure
, true, false,
121 aarch64
? aarch64EL
: EL1
);
129 TLB::finalizePhysical(RequestPtr req
, ThreadContext
*tc
, Mode mode
) const
135 TLB::lookup(Addr va
, uint16_t asn
, uint8_t vmid
, bool hyp
, bool secure
,
136 bool functional
, bool ignore_asn
, uint8_t target_el
)
139 TlbEntry
*retval
= NULL
;
141 // Maintaining LRU array
143 while (retval
== NULL
&& x
< size
) {
144 if ((!ignore_asn
&& table
[x
].match(va
, asn
, vmid
, hyp
, secure
, false,
146 (ignore_asn
&& table
[x
].match(va
, vmid
, hyp
, secure
, target_el
))) {
147 // We only move the hit entry ahead when the position is higher
149 if (x
> rangeMRU
&& !functional
) {
150 TlbEntry tmp_entry
= table
[x
];
151 for (int i
= x
; i
> 0; i
--)
152 table
[i
] = table
[i
- 1];
153 table
[0] = tmp_entry
;
163 DPRINTF(TLBVerbose
, "Lookup %#x, asn %#x -> %s vmn 0x%x hyp %d secure %d "
164 "ppn %#x size: %#x pa: %#x ap:%d ns:%d nstid:%d g:%d asid: %d "
166 va
, asn
, retval
? "hit" : "miss", vmid
, hyp
, secure
,
167 retval
? retval
->pfn
: 0, retval
? retval
->size
: 0,
168 retval
? retval
->pAddr(va
) : 0, retval
? retval
->ap
: 0,
169 retval
? retval
->ns
: 0, retval
? retval
->nstid
: 0,
170 retval
? retval
->global
: 0, retval
? retval
->asid
: 0,
171 retval
? retval
->el
: 0);
176 // insert a new TLB entry
178 TLB::insert(Addr addr
, TlbEntry
&entry
)
180 DPRINTF(TLB
, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x"
181 " asid:%d vmid:%d N:%d global:%d valid:%d nc:%d xn:%d"
182 " ap:%#x domain:%#x ns:%d nstid:%d isHyp:%d\n", entry
.pfn
,
183 entry
.size
, entry
.vpn
, entry
.asid
, entry
.vmid
, entry
.N
,
184 entry
.global
, entry
.valid
, entry
.nonCacheable
, entry
.xn
,
185 entry
.ap
, static_cast<uint8_t>(entry
.domain
), entry
.ns
, entry
.nstid
,
188 if (table
[size
- 1].valid
)
189 DPRINTF(TLB
, " - Replacing Valid entry %#x, asn %d vmn %d ppn %#x "
190 "size: %#x ap:%d ns:%d nstid:%d g:%d isHyp:%d el: %d\n",
191 table
[size
-1].vpn
<< table
[size
-1].N
, table
[size
-1].asid
,
192 table
[size
-1].vmid
, table
[size
-1].pfn
<< table
[size
-1].N
,
193 table
[size
-1].size
, table
[size
-1].ap
, table
[size
-1].ns
,
194 table
[size
-1].nstid
, table
[size
-1].global
, table
[size
-1].isHyp
,
197 //inserting to MRU position and evicting the LRU one
199 for (int i
= size
- 1; i
> 0; --i
)
200 table
[i
] = table
[i
-1];
204 ppRefills
->notify(1);
208 TLB::printTlb() const
212 DPRINTF(TLB
, "Current TLB contents:\n");
216 DPRINTF(TLB
, " * %s\n", te
->print());
222 TLB::flushAllSecurity(bool secure_lookup
, uint8_t target_el
, bool ignore_el
)
224 DPRINTF(TLB
, "Flushing all TLB entries (%s lookup)\n",
225 (secure_lookup
? "secure" : "non-secure"));
230 if (te
->valid
&& secure_lookup
== !te
->nstid
&&
231 (te
->vmid
== vmid
|| secure_lookup
) &&
232 checkELMatch(target_el
, te
->el
, ignore_el
)) {
234 DPRINTF(TLB
, " - %s\n", te
->print());
243 // If there's a second stage TLB (and we're not it) then flush it as well
244 // if we're currently in hyp mode
245 if (!isStage2
&& isHyp
) {
246 stage2Tlb
->flushAllSecurity(secure_lookup
, true);
251 TLB::flushAllNs(bool hyp
, uint8_t target_el
, bool ignore_el
)
253 DPRINTF(TLB
, "Flushing all NS TLB entries (%s lookup)\n",
254 (hyp
? "hyp" : "non-hyp"));
259 if (te
->valid
&& te
->nstid
&& te
->isHyp
== hyp
&&
260 checkELMatch(target_el
, te
->el
, ignore_el
)) {
262 DPRINTF(TLB
, " - %s\n", te
->print());
271 // If there's a second stage TLB (and we're not it) then flush it as well
272 if (!isStage2
&& !hyp
) {
273 stage2Tlb
->flushAllNs(false, true);
278 TLB::flushMvaAsid(Addr mva
, uint64_t asn
, bool secure_lookup
, uint8_t target_el
)
280 DPRINTF(TLB
, "Flushing TLB entries with mva: %#x, asid: %#x "
281 "(%s lookup)\n", mva
, asn
, (secure_lookup
?
282 "secure" : "non-secure"));
283 _flushMva(mva
, asn
, secure_lookup
, false, false, target_el
);
288 TLB::flushAsid(uint64_t asn
, bool secure_lookup
, uint8_t target_el
)
290 DPRINTF(TLB
, "Flushing TLB entries with asid: %#x (%s lookup)\n", asn
,
291 (secure_lookup
? "secure" : "non-secure"));
298 if (te
->valid
&& te
->asid
== asn
&& secure_lookup
== !te
->nstid
&&
299 (te
->vmid
== vmid
|| secure_lookup
) &&
300 checkELMatch(target_el
, te
->el
, false)) {
303 DPRINTF(TLB
, " - %s\n", te
->print());
312 TLB::flushMva(Addr mva
, bool secure_lookup
, bool hyp
, uint8_t target_el
)
314 DPRINTF(TLB
, "Flushing TLB entries with mva: %#x (%s lookup)\n", mva
,
315 (secure_lookup
? "secure" : "non-secure"));
316 _flushMva(mva
, 0xbeef, secure_lookup
, hyp
, true, target_el
);
321 TLB::_flushMva(Addr mva
, uint64_t asn
, bool secure_lookup
, bool hyp
,
322 bool ignore_asn
, uint8_t target_el
)
325 // D5.7.2: Sign-extend address to 64 bits
327 te
= lookup(mva
, asn
, vmid
, hyp
, secure_lookup
, false, ignore_asn
,
330 if (secure_lookup
== !te
->nstid
) {
331 DPRINTF(TLB
, " - %s\n", te
->print());
335 te
= lookup(mva
, asn
, vmid
, hyp
, secure_lookup
, false, ignore_asn
,
341 TLB::checkELMatch(uint8_t target_el
, uint8_t tentry_el
, bool ignore_el
)
345 if (target_el
== 2 || target_el
== 3) {
346 elMatch
= (tentry_el
== target_el
);
348 elMatch
= (tentry_el
== 0) || (tentry_el
== 1);
357 // We might have unserialized something or switched CPUs, so make
358 // sure to re-read the misc regs.
359 miscRegValid
= false;
363 TLB::takeOverFrom(BaseTLB
*_otlb
)
365 TLB
*otlb
= dynamic_cast<TLB
*>(_otlb
);
366 /* Make sure we actually have a valid type */
369 haveLPAE
= otlb
->haveLPAE
;
370 directToStage2
= otlb
->directToStage2
;
371 stage2Req
= otlb
->stage2Req
;
373 /* Sync the stage2 MMU if they exist in both
374 * the old CPU and the new
377 stage2Tlb
&& otlb
->stage2Tlb
) {
378 stage2Tlb
->takeOverFrom(otlb
->stage2Tlb
);
381 panic("Incompatible TLB type!");
386 TLB::serialize(CheckpointOut
&cp
) const
388 DPRINTF(Checkpoint
, "Serializing Arm TLB\n");
390 SERIALIZE_SCALAR(_attr
);
391 SERIALIZE_SCALAR(haveLPAE
);
392 SERIALIZE_SCALAR(directToStage2
);
393 SERIALIZE_SCALAR(stage2Req
);
395 int num_entries
= size
;
396 SERIALIZE_SCALAR(num_entries
);
397 for (int i
= 0; i
< size
; i
++)
398 table
[i
].serializeSection(cp
, csprintf("TlbEntry%d", i
));
402 TLB::unserialize(CheckpointIn
&cp
)
404 DPRINTF(Checkpoint
, "Unserializing Arm TLB\n");
406 UNSERIALIZE_SCALAR(_attr
);
407 UNSERIALIZE_SCALAR(haveLPAE
);
408 UNSERIALIZE_SCALAR(directToStage2
);
409 UNSERIALIZE_SCALAR(stage2Req
);
412 UNSERIALIZE_SCALAR(num_entries
);
413 for (int i
= 0; i
< min(size
, num_entries
); i
++)
414 table
[i
].unserializeSection(cp
, csprintf("TlbEntry%d", i
));
421 .name(name() + ".inst_hits")
422 .desc("ITB inst hits")
426 .name(name() + ".inst_misses")
427 .desc("ITB inst misses")
431 .name(name() + ".inst_accesses")
432 .desc("ITB inst accesses")
436 .name(name() + ".read_hits")
437 .desc("DTB read hits")
441 .name(name() + ".read_misses")
442 .desc("DTB read misses")
446 .name(name() + ".read_accesses")
447 .desc("DTB read accesses")
451 .name(name() + ".write_hits")
452 .desc("DTB write hits")
456 .name(name() + ".write_misses")
457 .desc("DTB write misses")
461 .name(name() + ".write_accesses")
462 .desc("DTB write accesses")
466 .name(name() + ".hits")
471 .name(name() + ".misses")
476 .name(name() + ".accesses")
477 .desc("DTB accesses")
481 .name(name() + ".flush_tlb")
482 .desc("Number of times complete TLB was flushed")
486 .name(name() + ".flush_tlb_mva")
487 .desc("Number of times TLB was flushed by MVA")
491 .name(name() + ".flush_tlb_mva_asid")
492 .desc("Number of times TLB was flushed by MVA & ASID")
496 .name(name() + ".flush_tlb_asid")
497 .desc("Number of times TLB was flushed by ASID")
501 .name(name() + ".flush_entries")
502 .desc("Number of entries that have been flushed from TLB")
506 .name(name() + ".align_faults")
507 .desc("Number of TLB faults due to alignment restrictions")
511 .name(name() + ".prefetch_faults")
512 .desc("Number of TLB faults due to prefetch")
516 .name(name() + ".domain_faults")
517 .desc("Number of TLB faults due to domain restrictions")
521 .name(name() + ".perms_faults")
522 .desc("Number of TLB faults due to permissions restrictions")
525 instAccesses
= instHits
+ instMisses
;
526 readAccesses
= readHits
+ readMisses
;
527 writeAccesses
= writeHits
+ writeMisses
;
528 hits
= readHits
+ writeHits
+ instHits
;
529 misses
= readMisses
+ writeMisses
+ instMisses
;
530 accesses
= readAccesses
+ writeAccesses
+ instAccesses
;
534 TLB::regProbePoints()
536 ppRefills
.reset(new ProbePoints::PMU(getProbeManager(), "Refills"));
540 TLB::translateSe(RequestPtr req
, ThreadContext
*tc
, Mode mode
,
541 Translation
*translation
, bool &delay
, bool timing
)
544 Addr vaddr_tainted
= req
->getVaddr();
547 vaddr
= purifyTaggedAddr(vaddr_tainted
, tc
, aarch64EL
, ttbcr
);
549 vaddr
= vaddr_tainted
;
550 uint32_t flags
= req
->getFlags();
552 bool is_fetch
= (mode
== Execute
);
553 bool is_write
= (mode
== Write
);
556 assert(flags
& MustBeOne
);
557 if (sctlr
.a
|| !(flags
& AllowUnaligned
)) {
558 if (vaddr
& mask(flags
& AlignmentMask
)) {
559 // LPAE is always disabled in SE mode
560 return std::make_shared
<DataAbort
>(
562 TlbEntry::DomainType::NoAccess
, is_write
,
563 ArmFault::AlignmentFault
, isStage2
,
570 Process
*p
= tc
->getProcessPtr();
572 if (!p
->pTable
->translate(vaddr
, paddr
))
573 return std::make_shared
<GenericPageTableFault
>(vaddr_tainted
);
574 req
->setPaddr(paddr
);
580 TLB::trickBoxCheck(RequestPtr req
, Mode mode
, TlbEntry::DomainType domain
)
586 TLB::walkTrickBoxCheck(Addr pa
, bool is_secure
, Addr va
, Addr sz
, bool is_exec
,
587 bool is_write
, TlbEntry::DomainType domain
, LookupLevel lookup_level
)
593 TLB::checkPermissions(TlbEntry
*te
, RequestPtr req
, Mode mode
)
595 Addr vaddr
= req
->getVaddr(); // 32-bit don't have to purify
596 uint32_t flags
= req
->getFlags();
597 bool is_fetch
= (mode
== Execute
);
598 bool is_write
= (mode
== Write
);
599 bool is_priv
= isPriv
&& !(flags
& UserMode
);
601 // Get the translation type from the actuall table entry
602 ArmFault::TranMethod tranMethod
= te
->longDescFormat
? ArmFault::LpaeTran
603 : ArmFault::VmsaTran
;
605 // If this is the second stage of translation and the request is for a
606 // stage 1 page table walk then we need to check the HCR.PTW bit. This
607 // allows us to generate a fault if the request targets an area marked
608 // as a device or strongly ordered.
609 if (isStage2
&& req
->isPTWalk() && hcr
.ptw
&&
610 (te
->mtype
!= TlbEntry::MemoryType::Normal
)) {
611 return std::make_shared
<DataAbort
>(
612 vaddr
, te
->domain
, is_write
,
613 ArmFault::PermissionLL
+ te
->lookupLevel
,
614 isStage2
, tranMethod
);
617 // Generate an alignment fault for unaligned data accesses to device or
618 // strongly ordered memory
620 if (te
->mtype
!= TlbEntry::MemoryType::Normal
) {
621 if (vaddr
& mask(flags
& AlignmentMask
)) {
623 return std::make_shared
<DataAbort
>(
624 vaddr
, TlbEntry::DomainType::NoAccess
, is_write
,
625 ArmFault::AlignmentFault
, isStage2
,
631 if (te
->nonCacheable
) {
632 // Prevent prefetching from I/O devices.
633 if (req
->isPrefetch()) {
634 // Here we can safely use the fault status for the short
635 // desc. format in all cases
636 return std::make_shared
<PrefetchAbort
>(
637 vaddr
, ArmFault::PrefetchUncacheable
,
638 isStage2
, tranMethod
);
642 if (!te
->longDescFormat
) {
643 switch ((dacr
>> (static_cast<uint8_t>(te
->domain
) * 2)) & 0x3) {
646 DPRINTF(TLB
, "TLB Fault: Data abort on domain. DACR: %#x"
647 " domain: %#x write:%d\n", dacr
,
648 static_cast<uint8_t>(te
->domain
), is_write
);
650 return std::make_shared
<PrefetchAbort
>(
652 ArmFault::DomainLL
+ te
->lookupLevel
,
653 isStage2
, tranMethod
);
655 return std::make_shared
<DataAbort
>(
656 vaddr
, te
->domain
, is_write
,
657 ArmFault::DomainLL
+ te
->lookupLevel
,
658 isStage2
, tranMethod
);
660 // Continue with permissions check
663 panic("UNPRED domain\n");
669 // The 'ap' variable is AP[2:0] or {AP[2,1],1b'0}, i.e. always three bits
670 uint8_t ap
= te
->longDescFormat
? te
->ap
<< 1 : te
->ap
;
671 uint8_t hap
= te
->hap
;
673 if (sctlr
.afe
== 1 || te
->longDescFormat
)
677 bool isWritable
= true;
678 // If this is a stage 2 access (eg for reading stage 1 page table entries)
679 // then don't perform the AP permissions check, we stil do the HAP check
686 DPRINTF(TLB
, "Access permissions 0, checking rs:%#x\n",
689 switch ((int)sctlr
.rs
) {
694 abt
= is_write
|| !is_priv
;
710 abt
= !is_priv
&& is_write
;
711 isWritable
= is_priv
;
717 panic("UNPRED premissions\n");
719 abt
= !is_priv
|| is_write
;
728 panic("Unknown permissions %#x\n", ap
);
732 bool hapAbt
= is_write
? !(hap
& 2) : !(hap
& 1);
733 bool xn
= te
->xn
|| (isWritable
&& sctlr
.wxn
) ||
734 (ap
== 3 && sctlr
.uwxn
&& is_priv
);
735 if (is_fetch
&& (abt
|| xn
||
736 (te
->longDescFormat
&& te
->pxn
&& !is_priv
) ||
737 (isSecure
&& te
->ns
&& scr
.sif
))) {
739 DPRINTF(TLB
, "TLB Fault: Prefetch abort on permission check. AP:%d "
740 "priv:%d write:%d ns:%d sif:%d sctlr.afe: %d \n",
741 ap
, is_priv
, is_write
, te
->ns
, scr
.sif
,sctlr
.afe
);
742 return std::make_shared
<PrefetchAbort
>(
744 ArmFault::PermissionLL
+ te
->lookupLevel
,
745 isStage2
, tranMethod
);
746 } else if (abt
| hapAbt
) {
748 DPRINTF(TLB
, "TLB Fault: Data abort on permission check. AP:%d priv:%d"
749 " write:%d\n", ap
, is_priv
, is_write
);
750 return std::make_shared
<DataAbort
>(
751 vaddr
, te
->domain
, is_write
,
752 ArmFault::PermissionLL
+ te
->lookupLevel
,
753 isStage2
| !abt
, tranMethod
);
760 TLB::checkPermissions64(TlbEntry
*te
, RequestPtr req
, Mode mode
,
765 Addr vaddr_tainted
= req
->getVaddr();
766 Addr vaddr
= purifyTaggedAddr(vaddr_tainted
, tc
, aarch64EL
, ttbcr
);
768 uint32_t flags
= req
->getFlags();
769 bool is_fetch
= (mode
== Execute
);
770 bool is_write
= (mode
== Write
);
771 bool is_priv M5_VAR_USED
= isPriv
&& !(flags
& UserMode
);
773 updateMiscReg(tc
, curTranType
);
775 // If this is the second stage of translation and the request is for a
776 // stage 1 page table walk then we need to check the HCR.PTW bit. This
777 // allows us to generate a fault if the request targets an area marked
778 // as a device or strongly ordered.
779 if (isStage2
&& req
->isPTWalk() && hcr
.ptw
&&
780 (te
->mtype
!= TlbEntry::MemoryType::Normal
)) {
781 return std::make_shared
<DataAbort
>(
782 vaddr_tainted
, te
->domain
, is_write
,
783 ArmFault::PermissionLL
+ te
->lookupLevel
,
784 isStage2
, ArmFault::LpaeTran
);
787 // Generate an alignment fault for unaligned accesses to device or
788 // strongly ordered memory
790 if (te
->mtype
!= TlbEntry::MemoryType::Normal
) {
791 if (vaddr
& mask(flags
& AlignmentMask
)) {
793 return std::make_shared
<DataAbort
>(
795 TlbEntry::DomainType::NoAccess
, is_write
,
796 ArmFault::AlignmentFault
, isStage2
,
802 if (te
->nonCacheable
) {
803 // Prevent prefetching from I/O devices.
804 if (req
->isPrefetch()) {
805 // Here we can safely use the fault status for the short
806 // desc. format in all cases
807 return std::make_shared
<PrefetchAbort
>(
809 ArmFault::PrefetchUncacheable
,
810 isStage2
, ArmFault::LpaeTran
);
814 uint8_t ap
= 0x3 & (te
->ap
); // 2-bit access protection field
818 uint8_t pxn
= te
->pxn
;
819 bool r
= !is_write
&& !is_fetch
;
822 DPRINTF(TLBVerbose
, "Checking permissions: ap:%d, xn:%d, pxn:%d, r:%d, "
823 "w:%d, x:%d\n", ap
, xn
, pxn
, r
, w
, x
);
826 panic("Virtualization in AArch64 state is not supported yet");
831 uint8_t perm
= (ap
<< 2) | (xn
<< 1) | pxn
;
841 grant
= r
|| w
|| (x
&& !sctlr
.wxn
);
862 uint8_t perm
= (ap
<< 2) | (xn
<< 1) | pxn
;
866 grant
= r
|| w
|| (x
&& !sctlr
.wxn
);
874 // regions that are writeable at EL0 should not be
898 uint8_t perm
= (ap
& 0x2) | xn
;
901 grant
= r
|| w
|| (x
&& !sctlr
.wxn
) ;
923 DPRINTF(TLB
, "TLB Fault: Prefetch abort on permission check. "
924 "AP:%d priv:%d write:%d ns:%d sif:%d "
926 ap
, is_priv
, is_write
, te
->ns
, scr
.sif
, sctlr
.afe
);
927 // Use PC value instead of vaddr because vaddr might be aligned to
928 // cache line and should not be the address reported in FAR
929 return std::make_shared
<PrefetchAbort
>(
931 ArmFault::PermissionLL
+ te
->lookupLevel
,
932 isStage2
, ArmFault::LpaeTran
);
935 DPRINTF(TLB
, "TLB Fault: Data abort on permission check. AP:%d "
936 "priv:%d write:%d\n", ap
, is_priv
, is_write
);
937 return std::make_shared
<DataAbort
>(
938 vaddr_tainted
, te
->domain
, is_write
,
939 ArmFault::PermissionLL
+ te
->lookupLevel
,
940 isStage2
, ArmFault::LpaeTran
);
948 TLB::translateFs(RequestPtr req
, ThreadContext
*tc
, Mode mode
,
949 Translation
*translation
, bool &delay
, bool timing
,
950 TLB::ArmTranslationType tranType
, bool functional
)
952 // No such thing as a functional timing access
953 assert(!(timing
&& functional
));
955 updateMiscReg(tc
, tranType
);
957 Addr vaddr_tainted
= req
->getVaddr();
960 vaddr
= purifyTaggedAddr(vaddr_tainted
, tc
, aarch64EL
, ttbcr
);
962 vaddr
= vaddr_tainted
;
963 uint32_t flags
= req
->getFlags();
965 bool is_fetch
= (mode
== Execute
);
966 bool is_write
= (mode
== Write
);
967 bool long_desc_format
= aarch64
|| (haveLPAE
&& ttbcr
.eae
);
968 ArmFault::TranMethod tranMethod
= long_desc_format
? ArmFault::LpaeTran
969 : ArmFault::VmsaTran
;
973 DPRINTF(TLBVerbose
, "CPSR is priv:%d UserMode:%d secure:%d S1S2NsTran:%d\n",
974 isPriv
, flags
& UserMode
, isSecure
, tranType
& S1S2NsTran
);
976 DPRINTF(TLB
, "translateFs addr %#x, mode %d, st2 %d, scr %#x sctlr %#x "
977 "flags %#x tranType 0x%x\n", vaddr_tainted
, mode
, isStage2
,
978 scr
, sctlr
, flags
, tranType
);
980 if ((req
->isInstFetch() && (!sctlr
.i
)) ||
981 ((!req
->isInstFetch()) && (!sctlr
.c
))){
982 req
->setFlags(Request::UNCACHEABLE
| Request::STRICT_ORDER
);
985 assert(flags
& MustBeOne
);
986 if (sctlr
.a
|| !(flags
& AllowUnaligned
)) {
987 if (vaddr
& mask(flags
& AlignmentMask
)) {
989 return std::make_shared
<DataAbort
>(
991 TlbEntry::DomainType::NoAccess
, is_write
,
992 ArmFault::AlignmentFault
, isStage2
,
998 // If guest MMU is off or hcr.vm=0 go straight to stage2
999 if ((isStage2
&& !hcr
.vm
) || (!isStage2
&& !sctlr
.m
)) {
1001 req
->setPaddr(vaddr
);
1002 // When the MMU is off the security attribute corresponds to the
1003 // security state of the processor
1005 req
->setFlags(Request::SECURE
);
1007 // @todo: double check this (ARM ARM issue C B3.2.1)
1008 if (long_desc_format
|| sctlr
.tre
== 0) {
1009 req
->setFlags(Request::UNCACHEABLE
| Request::STRICT_ORDER
);
1011 if (nmrr
.ir0
== 0 || nmrr
.or0
== 0 || prrr
.tr0
!= 0x2)
1012 req
->setFlags(Request::UNCACHEABLE
| Request::STRICT_ORDER
);
1015 // Set memory attributes
1017 temp_te
.ns
= !isSecure
;
1018 if (isStage2
|| hcr
.dc
== 0 || isSecure
||
1019 (isHyp
&& !(tranType
& S1CTran
))) {
1021 temp_te
.mtype
= is_fetch
? TlbEntry::MemoryType::Normal
1022 : TlbEntry::MemoryType::StronglyOrdered
;
1023 temp_te
.innerAttrs
= 0x0;
1024 temp_te
.outerAttrs
= 0x0;
1025 temp_te
.shareable
= true;
1026 temp_te
.outerShareable
= true;
1028 temp_te
.mtype
= TlbEntry::MemoryType::Normal
;
1029 temp_te
.innerAttrs
= 0x3;
1030 temp_te
.outerAttrs
= 0x3;
1031 temp_te
.shareable
= false;
1032 temp_te
.outerShareable
= false;
1034 temp_te
.setAttributes(long_desc_format
);
1035 DPRINTF(TLBVerbose
, "(No MMU) setting memory attributes: shareable: "
1036 "%d, innerAttrs: %d, outerAttrs: %d, isStage2: %d\n",
1037 temp_te
.shareable
, temp_te
.innerAttrs
, temp_te
.outerAttrs
,
1039 setAttr(temp_te
.attributes
);
1041 return trickBoxCheck(req
, mode
, TlbEntry::DomainType::NoAccess
);
1044 DPRINTF(TLBVerbose
, "Translating %s=%#x context=%d\n",
1045 isStage2
? "IPA" : "VA", vaddr_tainted
, asid
);
1046 // Translation enabled
1048 TlbEntry
*te
= NULL
;
1050 Fault fault
= getResultTe(&te
, req
, tc
, mode
, translation
, timing
,
1051 functional
, &mergeTe
);
1052 // only proceed if we have a valid table entry
1053 if ((te
== NULL
) && (fault
== NoFault
)) delay
= true;
1055 // If we have the table entry transfer some of the attributes to the
1056 // request that triggered the translation
1058 // Set memory attributes
1060 "Setting memory attributes: shareable: %d, innerAttrs: %d, "
1061 "outerAttrs: %d, mtype: %d, isStage2: %d\n",
1062 te
->shareable
, te
->innerAttrs
, te
->outerAttrs
,
1063 static_cast<uint8_t>(te
->mtype
), isStage2
);
1064 setAttr(te
->attributes
);
1066 if (te
->nonCacheable
)
1067 req
->setFlags(Request::UNCACHEABLE
);
1069 // Require requests to be ordered if the request goes to
1070 // strongly ordered or device memory (i.e., anything other
1071 // than normal memory requires strict order).
1072 if (te
->mtype
!= TlbEntry::MemoryType::Normal
)
1073 req
->setFlags(Request::STRICT_ORDER
);
1075 Addr pa
= te
->pAddr(vaddr
);
1078 if (isSecure
&& !te
->ns
) {
1079 req
->setFlags(Request::SECURE
);
1081 if ((!is_fetch
) && (vaddr
& mask(flags
& AlignmentMask
)) &&
1082 (te
->mtype
!= TlbEntry::MemoryType::Normal
)) {
1083 // Unaligned accesses to Device memory should always cause an
1084 // abort regardless of sctlr.a
1086 return std::make_shared
<DataAbort
>(
1088 TlbEntry::DomainType::NoAccess
, is_write
,
1089 ArmFault::AlignmentFault
, isStage2
,
1093 // Check for a trickbox generated address fault
1094 if (fault
== NoFault
) {
1095 fault
= trickBoxCheck(req
, mode
, te
->domain
);
1099 // Generate Illegal Inst Set State fault if IL bit is set in CPSR
1100 if (fault
== NoFault
) {
1101 if (aarch64
&& is_fetch
&& cpsr
.il
== 1) {
1102 return std::make_shared
<IllegalInstSetStateFault
>();
1110 TLB::translateAtomic(RequestPtr req
, ThreadContext
*tc
, Mode mode
,
1111 TLB::ArmTranslationType tranType
)
1113 updateMiscReg(tc
, tranType
);
1115 if (directToStage2
) {
1117 return stage2Tlb
->translateAtomic(req
, tc
, mode
, tranType
);
1123 fault
= translateFs(req
, tc
, mode
, NULL
, delay
, false, tranType
);
1125 fault
= translateSe(req
, tc
, mode
, NULL
, delay
, false);
1131 TLB::translateFunctional(RequestPtr req
, ThreadContext
*tc
, Mode mode
,
1132 TLB::ArmTranslationType tranType
)
1134 updateMiscReg(tc
, tranType
);
1136 if (directToStage2
) {
1138 return stage2Tlb
->translateFunctional(req
, tc
, mode
, tranType
);
1144 fault
= translateFs(req
, tc
, mode
, NULL
, delay
, false, tranType
, true);
1146 fault
= translateSe(req
, tc
, mode
, NULL
, delay
, false);
1152 TLB::translateTiming(RequestPtr req
, ThreadContext
*tc
,
1153 Translation
*translation
, Mode mode
, TLB::ArmTranslationType tranType
)
1155 updateMiscReg(tc
, tranType
);
1157 if (directToStage2
) {
1159 return stage2Tlb
->translateTiming(req
, tc
, translation
, mode
, tranType
);
1162 assert(translation
);
1164 return translateComplete(req
, tc
, translation
, mode
, tranType
, isStage2
);
1168 TLB::translateComplete(RequestPtr req
, ThreadContext
*tc
,
1169 Translation
*translation
, Mode mode
, TLB::ArmTranslationType tranType
,
1175 fault
= translateFs(req
, tc
, mode
, translation
, delay
, true, tranType
);
1177 fault
= translateSe(req
, tc
, mode
, translation
, delay
, true);
1178 DPRINTF(TLBVerbose
, "Translation returning delay=%d fault=%d\n", delay
, fault
!=
1180 // If we have a translation, and we're not in the middle of doing a stage
1181 // 2 translation tell the translation that we've either finished or its
1182 // going to take a while. By not doing this when we're in the middle of a
1183 // stage 2 translation we prevent marking the translation as delayed twice,
1184 // one when the translation starts and again when the stage 1 translation
1186 if (translation
&& (callFromS2
|| !stage2Req
|| req
->hasPaddr() || fault
!= NoFault
)) {
1188 translation
->finish(fault
, req
, tc
, mode
);
1190 translation
->markDelayed();
1196 TLB::getMasterPort()
1198 return &stage2Mmu
->getPort();
1202 TLB::updateMiscReg(ThreadContext
*tc
, ArmTranslationType tranType
)
1204 // check if the regs have changed, or the translation mode is different.
1205 // NOTE: the tran type doesn't affect stage 2 TLB's as they only handle
1206 // one type of translation anyway
1207 if (miscRegValid
&& miscRegContext
== tc
->contextId() &&
1208 ((tranType
== curTranType
) || isStage2
)) {
1212 DPRINTF(TLBVerbose
, "TLB variables changed!\n");
1213 cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
1214 // Dependencies: SCR/SCR_EL3, CPSR
1215 isSecure
= inSecureState(tc
);
1216 isSecure
&= (tranType
& HypMode
) == 0;
1217 isSecure
&= (tranType
& S1S2NsTran
) == 0;
1218 aarch64
= !cpsr
.width
;
1219 if (aarch64
) { // AArch64
1220 aarch64EL
= (ExceptionLevel
) (uint8_t) cpsr
.el
;
1221 switch (aarch64EL
) {
1225 sctlr
= tc
->readMiscReg(MISCREG_SCTLR_EL1
);
1226 ttbcr
= tc
->readMiscReg(MISCREG_TCR_EL1
);
1227 uint64_t ttbr_asid
= ttbcr
.a1
?
1228 tc
->readMiscReg(MISCREG_TTBR1_EL1
) :
1229 tc
->readMiscReg(MISCREG_TTBR0_EL1
);
1230 asid
= bits(ttbr_asid
,
1231 (haveLargeAsid64
&& ttbcr
.as
) ? 63 : 55, 48);
1235 sctlr
= tc
->readMiscReg(MISCREG_SCTLR_EL2
);
1236 ttbcr
= tc
->readMiscReg(MISCREG_TCR_EL2
);
1240 sctlr
= tc
->readMiscReg(MISCREG_SCTLR_EL3
);
1241 ttbcr
= tc
->readMiscReg(MISCREG_TCR_EL3
);
1245 scr
= tc
->readMiscReg(MISCREG_SCR_EL3
);
1246 isPriv
= aarch64EL
!= EL0
;
1247 // @todo: modify this behaviour to support Virtualization in
1251 directToStage2
= false;
1254 sctlr
= tc
->readMiscReg(flattenMiscRegNsBanked(MISCREG_SCTLR
, tc
,
1256 ttbcr
= tc
->readMiscReg(flattenMiscRegNsBanked(MISCREG_TTBCR
, tc
,
1258 scr
= tc
->readMiscReg(MISCREG_SCR
);
1259 isPriv
= cpsr
.mode
!= MODE_USER
;
1260 if (haveLPAE
&& ttbcr
.eae
) {
1261 // Long-descriptor translation table format in use
1262 uint64_t ttbr_asid
= tc
->readMiscReg(
1263 flattenMiscRegNsBanked(ttbcr
.a1
? MISCREG_TTBR1
1266 asid
= bits(ttbr_asid
, 55, 48);
1268 // Short-descriptor translation table format in use
1269 CONTEXTIDR context_id
= tc
->readMiscReg(flattenMiscRegNsBanked(
1270 MISCREG_CONTEXTIDR
, tc
,!isSecure
));
1271 asid
= context_id
.asid
;
1273 prrr
= tc
->readMiscReg(flattenMiscRegNsBanked(MISCREG_PRRR
, tc
,
1275 nmrr
= tc
->readMiscReg(flattenMiscRegNsBanked(MISCREG_NMRR
, tc
,
1277 dacr
= tc
->readMiscReg(flattenMiscRegNsBanked(MISCREG_DACR
, tc
,
1279 hcr
= tc
->readMiscReg(MISCREG_HCR
);
1281 if (haveVirtualization
) {
1282 vmid
= bits(tc
->readMiscReg(MISCREG_VTTBR
), 55, 48);
1283 isHyp
= cpsr
.mode
== MODE_HYP
;
1284 isHyp
|= tranType
& HypMode
;
1285 isHyp
&= (tranType
& S1S2NsTran
) == 0;
1286 isHyp
&= (tranType
& S1CTran
) == 0;
1288 sctlr
= tc
->readMiscReg(MISCREG_HSCTLR
);
1290 // Work out if we should skip the first stage of translation and go
1291 // directly to stage 2. This value is cached so we don't have to
1292 // compute it for every translation.
1293 stage2Req
= hcr
.vm
&& !isStage2
&& !isHyp
&& !isSecure
&&
1294 !(tranType
& S1CTran
);
1295 directToStage2
= stage2Req
&& !sctlr
.m
;
1300 directToStage2
= false;
1303 miscRegValid
= true;
1304 miscRegContext
= tc
->contextId();
1305 curTranType
= tranType
;
1309 TLB::getTE(TlbEntry
**te
, RequestPtr req
, ThreadContext
*tc
, Mode mode
,
1310 Translation
*translation
, bool timing
, bool functional
,
1311 bool is_secure
, TLB::ArmTranslationType tranType
)
1313 bool is_fetch
= (mode
== Execute
);
1314 bool is_write
= (mode
== Write
);
1316 Addr vaddr_tainted
= req
->getVaddr();
1318 ExceptionLevel target_el
= aarch64
? aarch64EL
: EL1
;
1320 vaddr
= purifyTaggedAddr(vaddr_tainted
, tc
, target_el
, ttbcr
);
1322 vaddr
= vaddr_tainted
;
1324 *te
= lookup(vaddr
, asid
, vmid
, isHyp
, is_secure
, false, false, target_el
);
1326 if (req
->isPrefetch()) {
1327 // if the request is a prefetch don't attempt to fill the TLB or go
1328 // any further with the memory access (here we can safely use the
1329 // fault status for the short desc. format in all cases)
1331 return std::make_shared
<PrefetchAbort
>(
1332 vaddr_tainted
, ArmFault::PrefetchTLBMiss
, isStage2
);
1342 // start translation table walk, pass variables rather than
1343 // re-retreaving in table walker for speed
1344 DPRINTF(TLB
, "TLB Miss: Starting hardware table walker for %#x(%d:%d)\n",
1345 vaddr_tainted
, asid
, vmid
);
1347 fault
= tableWalker
->walk(req
, tc
, asid
, vmid
, isHyp
, mode
,
1348 translation
, timing
, functional
, is_secure
,
1350 // for timing mode, return and wait for table walk,
1351 if (timing
|| fault
!= NoFault
) {
1355 *te
= lookup(vaddr
, asid
, vmid
, isHyp
, is_secure
, false, false, target_el
);
1371 TLB::getResultTe(TlbEntry
**te
, RequestPtr req
, ThreadContext
*tc
, Mode mode
,
1372 Translation
*translation
, bool timing
, bool functional
,
1376 TlbEntry
*s1Te
= NULL
;
1378 Addr vaddr_tainted
= req
->getVaddr();
1380 // Get the stage 1 table entry
1381 fault
= getTE(&s1Te
, req
, tc
, mode
, translation
, timing
, functional
,
1382 isSecure
, curTranType
);
1383 // only proceed if we have a valid table entry
1384 if ((s1Te
!= NULL
) && (fault
== NoFault
)) {
1385 // Check stage 1 permissions before checking stage 2
1387 fault
= checkPermissions64(s1Te
, req
, mode
, tc
);
1389 fault
= checkPermissions(s1Te
, req
, mode
);
1390 if (stage2Req
& (fault
== NoFault
)) {
1391 Stage2LookUp
*s2Lookup
= new Stage2LookUp(this, stage2Tlb
, *s1Te
,
1392 req
, translation
, mode
, timing
, functional
, curTranType
);
1393 fault
= s2Lookup
->getTe(tc
, mergeTe
);
1394 if (s2Lookup
->isComplete()) {
1396 // We've finished with the lookup so delete it
1399 // The lookup hasn't completed, so we can't delete it now. We
1400 // get round this by asking the object to self delete when the
1401 // translation is complete.
1402 s2Lookup
->setSelfDelete();
1405 // This case deals with an S1 hit (or bypass), followed by
1406 // an S2 hit-but-perms issue
1408 DPRINTF(TLBVerbose
, "s2TLB: reqVa %#x, reqPa %#x, fault %p\n",
1409 vaddr_tainted
, req
->hasPaddr() ? req
->getPaddr() : ~0, fault
);
1410 if (fault
!= NoFault
) {
1411 ArmFault
*armFault
= reinterpret_cast<ArmFault
*>(fault
.get());
1412 armFault
->annotate(ArmFault::S1PTW
, false);
1413 armFault
->annotate(ArmFault::OVA
, vaddr_tainted
);
1423 ArmTLBParams::create()
1425 return new ArmISA::TLB(this);