2 * Copyright (c) 2010 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
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18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
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26 * this software without specific prior written permission.
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 #include "arch/arm/faults.hh"
49 #include "arch/arm/pagetable.hh"
50 #include "arch/arm/tlb.hh"
51 #include "arch/arm/utility.hh"
52 #include "base/inifile.hh"
53 #include "base/str.hh"
54 #include "base/trace.hh"
55 #include "cpu/thread_context.hh"
56 #include "debug/Checkpoint.hh"
57 #include "debug/TLB.hh"
58 #include "debug/TLBVerbose.hh"
59 #include "mem/page_table.hh"
60 #include "params/ArmTLB.hh"
61 #include "sim/process.hh"
64 #include "arch/arm/table_walker.hh"
68 using namespace ArmISA
;
70 TLB::TLB(const Params
*p
)
71 : BaseTLB(p
), size(p
->size
)
73 , tableWalker(p
->walker
)
75 , rangeMRU(1), miscRegValid(false)
77 table
= new TlbEntry
[size
];
78 memset(table
, 0, sizeof(TlbEntry
) * size
);
81 tableWalker
->setTlb(this);
92 TLB::translateFunctional(ThreadContext
*tc
, Addr va
, Addr
&pa
)
96 TlbEntry
*e
= lookup(va
, contextId
, true);
104 TLB::lookup(Addr va
, uint8_t cid
, bool functional
)
107 TlbEntry
*retval
= NULL
;
109 // Maitaining LRU array
112 while (retval
== NULL
&& x
< size
) {
113 if (table
[x
].match(va
, cid
)) {
115 // We only move the hit entry ahead when the position is higher than rangeMRU
117 TlbEntry tmp_entry
= table
[x
];
118 for(int i
= x
; i
> 0; i
--)
119 table
[i
] = table
[i
-1];
120 table
[0] = tmp_entry
;
130 DPRINTF(TLBVerbose
, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n",
131 va
, cid
, retval
? "hit" : "miss", retval
? retval
->pfn
: 0,
132 retval
? retval
->size
: 0, retval
? retval
->pAddr(va
) : 0,
133 retval
? retval
->ap
: 0);
138 // insert a new TLB entry
140 TLB::insert(Addr addr
, TlbEntry
&entry
)
142 DPRINTF(TLB
, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x"
143 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x"
144 " domain:%#x\n", entry
.pfn
, entry
.size
, entry
.vpn
, entry
.asid
,
145 entry
.N
, entry
.global
, entry
.valid
, entry
.nonCacheable
, entry
.sNp
,
146 entry
.xn
, entry
.ap
, entry
.domain
);
148 if (table
[size
-1].valid
)
149 DPRINTF(TLB
, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n",
150 table
[size
-1].vpn
<< table
[size
-1].N
, table
[size
-1].asid
,
151 table
[size
-1].pfn
<< table
[size
-1].N
, table
[size
-1].size
,
154 //inserting to MRU position and evicting the LRU one
156 for(int i
= size
-1; i
> 0; i
--)
157 table
[i
] = table
[i
-1];
168 DPRINTF(TLB
, "Current TLB contents:\n");
172 DPRINTF(TLB
, " * %#x, asn %d ppn %#x size: %#x ap:%d\n",
173 te
->vpn
<< te
->N
, te
->asid
, te
->pfn
<< te
->N
, te
->size
, te
->ap
);
182 DPRINTF(TLB
, "Flushing all TLB entries\n");
188 DPRINTF(TLB
, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
189 te
->vpn
<< te
->N
, te
->asid
, te
->pfn
<< te
->N
, te
->size
, te
->ap
);
195 memset(table
, 0, sizeof(TlbEntry
) * size
);
202 TLB::flushMvaAsid(Addr mva
, uint64_t asn
)
204 DPRINTF(TLB
, "Flushing mva %#x asid: %#x\n", mva
, asn
);
207 te
= lookup(mva
, asn
);
209 DPRINTF(TLB
, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
210 te
->vpn
<< te
->N
, te
->asid
, te
->pfn
<< te
->N
, te
->size
, te
->ap
);
213 te
= lookup(mva
,asn
);
219 TLB::flushAsid(uint64_t asn
)
221 DPRINTF(TLB
, "Flushing all entries with asid: %#x\n", asn
);
228 if (te
->asid
== asn
) {
230 DPRINTF(TLB
, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
231 te
->vpn
<< te
->N
, te
->asid
, te
->pfn
<< te
->N
, te
->size
, te
->ap
);
240 TLB::flushMva(Addr mva
)
242 DPRINTF(TLB
, "Flushing all entries with mva: %#x\n", mva
);
249 Addr v
= te
->vpn
<< te
->N
;
250 if (mva
>= v
&& mva
< v
+ te
->size
) {
252 DPRINTF(TLB
, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
253 te
->vpn
<< te
->N
, te
->asid
, te
->pfn
<< te
->N
, te
->size
, te
->ap
);
262 TLB::serialize(ostream
&os
)
264 DPRINTF(Checkpoint
, "Serializing Arm TLB\n");
266 SERIALIZE_SCALAR(_attr
);
268 int num_entries
= size
;
269 SERIALIZE_SCALAR(num_entries
);
270 for(int i
= 0; i
< size
; i
++){
271 nameOut(os
, csprintf("%s.TlbEntry%d", name(), i
));
272 table
[i
].serialize(os
);
277 TLB::unserialize(Checkpoint
*cp
, const string
§ion
)
279 DPRINTF(Checkpoint
, "Unserializing Arm TLB\n");
281 UNSERIALIZE_SCALAR(_attr
);
283 UNSERIALIZE_SCALAR(num_entries
);
284 for(int i
= 0; i
< min(size
, num_entries
); i
++){
285 table
[i
].unserialize(cp
, csprintf("%s.TlbEntry%d", section
, i
));
287 miscRegValid
= false;
294 .name(name() + ".inst_hits")
295 .desc("ITB inst hits")
299 .name(name() + ".inst_misses")
300 .desc("ITB inst misses")
304 .name(name() + ".inst_accesses")
305 .desc("ITB inst accesses")
309 .name(name() + ".read_hits")
310 .desc("DTB read hits")
314 .name(name() + ".read_misses")
315 .desc("DTB read misses")
319 .name(name() + ".read_accesses")
320 .desc("DTB read accesses")
324 .name(name() + ".write_hits")
325 .desc("DTB write hits")
329 .name(name() + ".write_misses")
330 .desc("DTB write misses")
334 .name(name() + ".write_accesses")
335 .desc("DTB write accesses")
339 .name(name() + ".hits")
344 .name(name() + ".misses")
349 .name(name() + ".accesses")
350 .desc("DTB accesses")
354 .name(name() + ".flush_tlb")
355 .desc("Number of times complete TLB was flushed")
359 .name(name() + ".flush_tlb_mva")
360 .desc("Number of times TLB was flushed by MVA")
364 .name(name() + ".flush_tlb_mva_asid")
365 .desc("Number of times TLB was flushed by MVA & ASID")
369 .name(name() + ".flush_tlb_asid")
370 .desc("Number of times TLB was flushed by ASID")
374 .name(name() + ".flush_entries")
375 .desc("Number of entries that have been flushed from TLB")
379 .name(name() + ".align_faults")
380 .desc("Number of TLB faults due to alignment restrictions")
384 .name(name() + ".prefetch_faults")
385 .desc("Number of TLB faults due to prefetch")
389 .name(name() + ".domain_faults")
390 .desc("Number of TLB faults due to domain restrictions")
394 .name(name() + ".perms_faults")
395 .desc("Number of TLB faults due to permissions restrictions")
398 instAccesses
= instHits
+ instMisses
;
399 readAccesses
= readHits
+ readMisses
;
400 writeAccesses
= writeHits
+ writeMisses
;
401 hits
= readHits
+ writeHits
+ instHits
;
402 misses
= readMisses
+ writeMisses
+ instMisses
;
403 accesses
= readAccesses
+ writeAccesses
+ instAccesses
;
408 TLB::translateSe(RequestPtr req
, ThreadContext
*tc
, Mode mode
,
409 Translation
*translation
, bool &delay
, bool timing
)
413 Addr vaddr
= req
->getVaddr();
414 uint32_t flags
= req
->getFlags();
416 bool is_fetch
= (mode
== Execute
);
417 bool is_write
= (mode
== Write
);
420 assert(flags
& MustBeOne
);
421 if (sctlr
.a
|| !(flags
& AllowUnaligned
)) {
422 if (vaddr
& flags
& AlignmentMask
) {
423 return new DataAbort(vaddr
, 0, is_write
, ArmFault::AlignmentFault
);
429 Process
*p
= tc
->getProcessPtr();
431 if (!p
->pTable
->translate(vaddr
, paddr
))
432 return Fault(new GenericPageTableFault(vaddr
));
433 req
->setPaddr(paddr
);
441 TLB::trickBoxCheck(RequestPtr req
, Mode mode
, uint8_t domain
, bool sNp
)
447 TLB::walkTrickBoxCheck(Addr pa
, Addr va
, Addr sz
, bool is_exec
,
448 bool is_write
, uint8_t domain
, bool sNp
)
454 TLB::translateFs(RequestPtr req
, ThreadContext
*tc
, Mode mode
,
455 Translation
*translation
, bool &delay
, bool timing
)
459 DPRINTF(TLBVerbose
, "TLB variables changed!\n");
462 Addr vaddr
= req
->getVaddr();
463 uint32_t flags
= req
->getFlags();
465 bool is_fetch
= (mode
== Execute
);
466 bool is_write
= (mode
== Write
);
467 bool is_priv
= isPriv
&& !(flags
& UserMode
);
469 DPRINTF(TLBVerbose
, "CPSR is priv:%d UserMode:%d\n",
470 isPriv
, flags
& UserMode
);
471 // If this is a clrex instruction, provide a PA of 0 with no fault
472 // This will force the monitor to set the tracked address to 0
473 // a bit of a hack but this effectively clrears this processors monitor
474 if (flags
& Request::CLEAR_LL
){
476 req
->setFlags(Request::UNCACHEABLE
);
477 req
->setFlags(Request::CLEAR_LL
);
480 if ((req
->isInstFetch() && (!sctlr
.i
)) ||
481 ((!req
->isInstFetch()) && (!sctlr
.c
))){
482 req
->setFlags(Request::UNCACHEABLE
);
485 assert(flags
& MustBeOne
);
486 if (sctlr
.a
|| !(flags
& AllowUnaligned
)) {
487 if (vaddr
& flags
& AlignmentMask
) {
489 return new DataAbort(vaddr
, 0, is_write
, ArmFault::AlignmentFault
);
497 req
->setPaddr(vaddr
);
498 if (sctlr
.tre
== 0) {
499 req
->setFlags(Request::UNCACHEABLE
);
501 if (nmrr
.ir0
== 0 || nmrr
.or0
== 0 || prrr
.tr0
!= 0x2)
502 req
->setFlags(Request::UNCACHEABLE
);
505 // Set memory attributes
507 tableWalker
->memAttrs(tc
, temp_te
, sctlr
, 0, 1);
508 temp_te
.shareable
= true;
509 DPRINTF(TLBVerbose
, "(No MMU) setting memory attributes: shareable:\
510 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te
.shareable
,
511 temp_te
.innerAttrs
, temp_te
.outerAttrs
);
512 setAttr(temp_te
.attributes
);
514 return trickBoxCheck(req
, mode
, 0, false);
517 DPRINTF(TLBVerbose
, "Translating vaddr=%#x context=%d\n", vaddr
, contextId
);
518 // Translation enabled
520 TlbEntry
*te
= lookup(vaddr
, contextId
);
522 if (req
->isPrefetch()){
523 //if the request is a prefetch don't attempt to fill the TLB
524 //or go any further with the memory access
526 return new PrefetchAbort(vaddr
, ArmFault::PrefetchTLBMiss
);
536 // start translation table walk, pass variables rather than
537 // re-retreaving in table walker for speed
538 DPRINTF(TLB
, "TLB Miss: Starting hardware table walker for %#x(%d)\n",
540 fault
= tableWalker
->walk(req
, tc
, contextId
, mode
, translation
,
542 if (timing
&& fault
== NoFault
) {
544 // for timing mode, return and wait for table walk
550 te
= lookup(vaddr
, contextId
);
563 // Set memory attributes
565 "Setting memory attributes: shareable: %d, innerAttrs: %d, \
567 te
->shareable
, te
->innerAttrs
, te
->outerAttrs
);
568 setAttr(te
->attributes
);
569 if (te
->nonCacheable
) {
570 req
->setFlags(Request::UNCACHEABLE
);
572 // Prevent prefetching from I/O devices.
573 if (req
->isPrefetch()) {
574 return new PrefetchAbort(vaddr
, ArmFault::PrefetchUncacheable
);
578 switch ( (dacr
>> (te
->domain
* 2)) & 0x3) {
581 DPRINTF(TLB
, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x"
582 " write:%d sNp:%d\n", dacr
, te
->domain
, is_write
, te
->sNp
);
584 return new PrefetchAbort(vaddr
,
585 (te
->sNp
? ArmFault::Domain0
: ArmFault::Domain1
));
587 return new DataAbort(vaddr
, te
->domain
, is_write
,
588 (te
->sNp
? ArmFault::Domain0
: ArmFault::Domain1
));
590 // Continue with permissions check
593 panic("UNPRED domain\n");
595 req
->setPaddr(te
->pAddr(vaddr
));
596 fault
= trickBoxCheck(req
, mode
, te
->domain
, te
->sNp
);
614 DPRINTF(TLB
, "Access permissions 0, checking rs:%#x\n", (int)sctlr
.rs
);
616 switch ((int)sctlr
.rs
) {
621 abt
= is_write
|| !is_priv
;
637 abt
= !is_priv
&& is_write
;
643 panic("UNPRED premissions\n");
645 abt
= !is_priv
|| is_write
;
652 panic("Unknown permissions\n");
654 if ((is_fetch
) && (abt
|| te
->xn
)) {
656 DPRINTF(TLB
, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d"
657 " write:%d sNp:%d\n", ap
, is_priv
, is_write
, te
->sNp
);
658 return new PrefetchAbort(vaddr
,
659 (te
->sNp
? ArmFault::Permission0
:
660 ArmFault::Permission1
));
663 DPRINTF(TLB
, "TLB Fault: Data abort on permission check. AP:%d priv:%d"
664 " write:%d sNp:%d\n", ap
, is_priv
, is_write
, te
->sNp
);
665 return new DataAbort(vaddr
, te
->domain
, is_write
,
666 (te
->sNp
? ArmFault::Permission0
:
667 ArmFault::Permission1
));
670 req
->setPaddr(te
->pAddr(vaddr
));
671 // Check for a trickbox generated address fault
672 fault
= trickBoxCheck(req
, mode
, te
->domain
, te
->sNp
);
682 TLB::translateAtomic(RequestPtr req
, ThreadContext
*tc
, Mode mode
)
687 fault
= translateFs(req
, tc
, mode
, NULL
, delay
, false);
689 fault
= translateSe(req
, tc
, mode
, NULL
, delay
, false);
696 TLB::translateTiming(RequestPtr req
, ThreadContext
*tc
,
697 Translation
*translation
, Mode mode
)
703 fault
= translateFs(req
, tc
, mode
, translation
, delay
, true);
705 fault
= translateSe(req
, tc
, mode
, translation
, delay
, true);
707 DPRINTF(TLB
, "Translation returning delay=%d fault=%d\n", delay
, fault
!=
710 translation
->finish(fault
, req
, tc
, mode
);
712 translation
->markDelayed();
720 return tableWalker
->getPort("port");
729 ArmTLBParams::create()
731 return new ArmISA::TLB(this);