src/arch/arm/tlb.cc

   1 /*
   2  * Copyright (c) 2010 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2001-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ali Saidi
  41  *          Nathan Binkert
  42  *          Steve Reinhardt
  43  */
  44
  45 #include <string>
  46 #include <vector>
  47
  48 #include "arch/arm/faults.hh"
  49 #include "arch/arm/pagetable.hh"
  50 #include "arch/arm/tlb.hh"
  51 #include "arch/arm/utility.hh"
  52 #include "base/inifile.hh"
  53 #include "base/str.hh"
  54 #include "base/trace.hh"
  55 #include "cpu/thread_context.hh"
  56 #include "debug/Checkpoint.hh"
  57 #include "debug/TLB.hh"
  58 #include "debug/TLBVerbose.hh"
  59 #include "mem/page_table.hh"
  60 #include "params/ArmTLB.hh"
  61 #include "sim/process.hh"
  62
  63 #if FULL_SYSTEM
  64 #include "arch/arm/table_walker.hh"
  65 #endif
  66
  67 using namespace std;
  68 using namespace ArmISA;
  69
  70 TLB::TLB(const Params *p)
  71     : BaseTLB(p), size(p->size)
  72 #if FULL_SYSTEM
  73       , tableWalker(p->walker)
  74 #endif
  75     , rangeMRU(1), miscRegValid(false)
  76 {
  77     table = new TlbEntry[size];
  78     memset(table, 0, sizeof(TlbEntry) * size);
  79
  80 #if FULL_SYSTEM
  81     tableWalker->setTlb(this);
  82 #endif
  83 }
  84
  85 TLB::~TLB()
  86 {
  87     if (table)
  88         delete [] table;
  89 }
  90
  91 bool
  92 TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa)
  93 {
  94     if (!miscRegValid)
  95         updateMiscReg(tc);
  96     TlbEntry *e = lookup(va, contextId, true);
  97     if (!e)
  98         return false;
  99     pa = e->pAddr(va);
 100     return true;
 101 }
 102
 103 TlbEntry*
 104 TLB::lookup(Addr va, uint8_t cid, bool functional)
 105 {
 106
 107     TlbEntry *retval = NULL;
 108
 109     // Maitaining LRU array
 110
 111     int x = 0;
 112     while (retval == NULL && x < size) {
 113         if (table[x].match(va, cid)) {
 114
 115             // We only move the hit entry ahead when the position is higher than rangeMRU
 116             if (x > rangeMRU) {
 117                 TlbEntry tmp_entry = table[x];
 118                 for(int i = x; i > 0; i--)
 119                     table[i] = table[i-1];
 120                 table[0] = tmp_entry;
 121                 retval = &table[0];
 122             } else {
 123                 retval = &table[x];
 124             }
 125             break;
 126         }
 127         x++;
 128     }
 129
 130     DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n",
 131             va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0,
 132             retval ? retval->size : 0, retval ? retval->pAddr(va) : 0,
 133             retval ? retval->ap : 0);
 134     ;
 135     return retval;
 136 }
 137
 138 // insert a new TLB entry
 139 void
 140 TLB::insert(Addr addr, TlbEntry &entry)
 141 {
 142     DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x"
 143             " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x"
 144             " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid,
 145             entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp,
 146             entry.xn, entry.ap, entry.domain);
 147
 148     if (table[size-1].valid)
 149         DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n",
 150                 table[size-1].vpn << table[size-1].N, table[size-1].asid,
 151                 table[size-1].pfn << table[size-1].N, table[size-1].size,
 152                 table[size-1].ap);
 153
 154     //inserting to MRU position and evicting the LRU one
 155
 156     for(int i = size-1; i > 0; i--)
 157       table[i] = table[i-1];
 158     table[0] = entry;
 159
 160     inserts++;
 161 }
 162
 163 void
 164 TLB::printTlb()
 165 {
 166     int x = 0;
 167     TlbEntry *te;
 168     DPRINTF(TLB, "Current TLB contents:\n");
 169     while (x < size) {
 170        te = &table[x];
 171        if (te->valid)
 172            DPRINTF(TLB, " *  %#x, asn %d ppn %#x size: %#x ap:%d\n",
 173                 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
 174        x++;
 175     }
 176 }
 177
 178
 179 void
 180 TLB::flushAll()
 181 {
 182     DPRINTF(TLB, "Flushing all TLB entries\n");
 183     int x = 0;
 184     TlbEntry *te;
 185     while (x < size) {
 186        te = &table[x];
 187        if (te->valid) {
 188            DPRINTF(TLB, " -  %#x, asn %d ppn %#x size: %#x ap:%d\n",
 189                 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
 190            flushedEntries++;
 191        }
 192        x++;
 193     }
 194
 195     memset(table, 0, sizeof(TlbEntry) * size);
 196
 197     flushTlb++;
 198 }
 199
 200
 201 void
 202 TLB::flushMvaAsid(Addr mva, uint64_t asn)
 203 {
 204     DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn);
 205     TlbEntry *te;
 206
 207     te = lookup(mva, asn);
 208     while (te != NULL) {
 209      DPRINTF(TLB, " -  %#x, asn %d ppn %#x size: %#x ap:%d\n",
 210             te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
 211         te->valid = false;
 212         flushedEntries++;
 213         te = lookup(mva,asn);
 214     }
 215     flushTlbMvaAsid++;
 216 }
 217
 218 void
 219 TLB::flushAsid(uint64_t asn)
 220 {
 221     DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn);
 222
 223     int x = 0;
 224     TlbEntry *te;
 225
 226     while (x < size) {
 227         te = &table[x];
 228         if (te->asid == asn) {
 229             te->valid = false;
 230             DPRINTF(TLB, " -  %#x, asn %d ppn %#x size: %#x ap:%d\n",
 231                 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
 232             flushedEntries++;
 233         }
 234         x++;
 235     }
 236     flushTlbAsid++;
 237 }
 238
 239 void
 240 TLB::flushMva(Addr mva)
 241 {
 242     DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva);
 243
 244     int x = 0;
 245     TlbEntry *te;
 246
 247     while (x < size) {
 248         te = &table[x];
 249         Addr v = te->vpn << te->N;
 250         if (mva >= v && mva < v + te->size) {
 251             te->valid = false;
 252             DPRINTF(TLB, " -  %#x, asn %d ppn %#x size: %#x ap:%d\n",
 253                 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
 254             flushedEntries++;
 255         }
 256         x++;
 257     }
 258     flushTlbMva++;
 259 }
 260
 261 void
 262 TLB::serialize(ostream &os)
 263 {
 264     DPRINTF(Checkpoint, "Serializing Arm TLB\n");
 265
 266     SERIALIZE_SCALAR(_attr);
 267
 268     int num_entries = size;
 269     SERIALIZE_SCALAR(num_entries);
 270     for(int i = 0; i < size; i++){
 271         nameOut(os, csprintf("%s.TlbEntry%d", name(), i));
 272         table[i].serialize(os);
 273     }
 274 }
 275
 276 void
 277 TLB::unserialize(Checkpoint *cp, const string &section)
 278 {
 279     DPRINTF(Checkpoint, "Unserializing Arm TLB\n");
 280
 281     UNSERIALIZE_SCALAR(_attr);
 282     int num_entries;
 283     UNSERIALIZE_SCALAR(num_entries);
 284     for(int i = 0; i < min(size, num_entries); i++){
 285         table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i));
 286     }
 287     miscRegValid = false;
 288 }
 289
 290 void
 291 TLB::regStats()
 292 {
 293     instHits
 294         .name(name() + ".inst_hits")
 295         .desc("ITB inst hits")
 296         ;
 297
 298     instMisses
 299         .name(name() + ".inst_misses")
 300         .desc("ITB inst misses")
 301         ;
 302
 303     instAccesses
 304         .name(name() + ".inst_accesses")
 305         .desc("ITB inst accesses")
 306         ;
 307
 308     readHits
 309         .name(name() + ".read_hits")
 310         .desc("DTB read hits")
 311         ;
 312
 313     readMisses
 314         .name(name() + ".read_misses")
 315         .desc("DTB read misses")
 316         ;
 317
 318     readAccesses
 319         .name(name() + ".read_accesses")
 320         .desc("DTB read accesses")
 321         ;
 322
 323     writeHits
 324         .name(name() + ".write_hits")
 325         .desc("DTB write hits")
 326         ;
 327
 328     writeMisses
 329         .name(name() + ".write_misses")
 330         .desc("DTB write misses")
 331         ;
 332
 333     writeAccesses
 334         .name(name() + ".write_accesses")
 335         .desc("DTB write accesses")
 336         ;
 337
 338     hits
 339         .name(name() + ".hits")
 340         .desc("DTB hits")
 341         ;
 342
 343     misses
 344         .name(name() + ".misses")
 345         .desc("DTB misses")
 346         ;
 347
 348     accesses
 349         .name(name() + ".accesses")
 350         .desc("DTB accesses")
 351         ;
 352
 353     flushTlb
 354         .name(name() + ".flush_tlb")
 355         .desc("Number of times complete TLB was flushed")
 356         ;
 357
 358     flushTlbMva
 359         .name(name() + ".flush_tlb_mva")
 360         .desc("Number of times TLB was flushed by MVA")
 361         ;
 362
 363     flushTlbMvaAsid
 364         .name(name() + ".flush_tlb_mva_asid")
 365         .desc("Number of times TLB was flushed by MVA & ASID")
 366         ;
 367
 368     flushTlbAsid
 369         .name(name() + ".flush_tlb_asid")
 370         .desc("Number of times TLB was flushed by ASID")
 371         ;
 372
 373     flushedEntries
 374         .name(name() + ".flush_entries")
 375         .desc("Number of entries that have been flushed from TLB")
 376         ;
 377
 378     alignFaults
 379         .name(name() + ".align_faults")
 380         .desc("Number of TLB faults due to alignment restrictions")
 381         ;
 382
 383     prefetchFaults
 384         .name(name() + ".prefetch_faults")
 385         .desc("Number of TLB faults due to prefetch")
 386         ;
 387
 388     domainFaults
 389         .name(name() + ".domain_faults")
 390         .desc("Number of TLB faults due to domain restrictions")
 391         ;
 392
 393     permsFaults
 394         .name(name() + ".perms_faults")
 395         .desc("Number of TLB faults due to permissions restrictions")
 396         ;
 397
 398     instAccesses = instHits + instMisses;
 399     readAccesses = readHits + readMisses;
 400     writeAccesses = writeHits + writeMisses;
 401     hits = readHits + writeHits + instHits;
 402     misses = readMisses + writeMisses + instMisses;
 403     accesses = readAccesses + writeAccesses + instAccesses;
 404 }
 405
 406 #if !FULL_SYSTEM
 407 Fault
 408 TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
 409         Translation *translation, bool &delay, bool timing)
 410 {
 411     if (!miscRegValid)
 412         updateMiscReg(tc);
 413     Addr vaddr = req->getVaddr();
 414     uint32_t flags = req->getFlags();
 415
 416     bool is_fetch = (mode == Execute);
 417     bool is_write = (mode == Write);
 418
 419     if (!is_fetch) {
 420         assert(flags & MustBeOne);
 421         if (sctlr.a || !(flags & AllowUnaligned)) {
 422             if (vaddr & flags & AlignmentMask) {
 423                 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
 424             }
 425         }
 426     }
 427
 428     Addr paddr;
 429     Process *p = tc->getProcessPtr();
 430
 431     if (!p->pTable->translate(vaddr, paddr))
 432         return Fault(new GenericPageTableFault(vaddr));
 433     req->setPaddr(paddr);
 434
 435     return NoFault;
 436 }
 437
 438 #else // FULL_SYSTEM
 439
 440 Fault
 441 TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp)
 442 {
 443     return NoFault;
 444 }
 445
 446 Fault
 447 TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
 448         bool is_write, uint8_t domain, bool sNp)
 449 {
 450     return NoFault;
 451 }
 452
 453 Fault
 454 TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
 455         Translation *translation, bool &delay, bool timing)
 456 {
 457     if (!miscRegValid) {
 458         updateMiscReg(tc);
 459         DPRINTF(TLBVerbose, "TLB variables changed!\n");
 460     }
 461
 462     Addr vaddr = req->getVaddr();
 463     uint32_t flags = req->getFlags();
 464
 465     bool is_fetch = (mode == Execute);
 466     bool is_write = (mode == Write);
 467     bool is_priv = isPriv && !(flags & UserMode);
 468
 469     DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n",
 470             isPriv, flags & UserMode);
 471     // If this is a clrex instruction, provide a PA of 0 with no fault
 472     // This will force the monitor to set the tracked address to 0
 473     // a bit of a hack but this effectively clrears this processors monitor
 474     if (flags & Request::CLEAR_LL){
 475        req->setPaddr(0);
 476        req->setFlags(Request::UNCACHEABLE);
 477        req->setFlags(Request::CLEAR_LL);
 478        return NoFault;
 479     }
 480     if ((req->isInstFetch() && (!sctlr.i)) ||
 481         ((!req->isInstFetch()) && (!sctlr.c))){
 482        req->setFlags(Request::UNCACHEABLE);
 483     }
 484     if (!is_fetch) {
 485         assert(flags & MustBeOne);
 486         if (sctlr.a || !(flags & AllowUnaligned)) {
 487             if (vaddr & flags & AlignmentMask) {
 488                 alignFaults++;
 489                 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
 490             }
 491         }
 492     }
 493
 494     Fault fault;
 495
 496     if (!sctlr.m) {
 497         req->setPaddr(vaddr);
 498         if (sctlr.tre == 0) {
 499             req->setFlags(Request::UNCACHEABLE);
 500         } else {
 501             if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2)
 502                req->setFlags(Request::UNCACHEABLE);
 503         }
 504
 505         // Set memory attributes
 506         TlbEntry temp_te;
 507         tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1);
 508         temp_te.shareable = true;
 509         DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\
 510                 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable,
 511                 temp_te.innerAttrs, temp_te.outerAttrs);
 512         setAttr(temp_te.attributes);
 513
 514         return trickBoxCheck(req, mode, 0, false);
 515     }
 516
 517     DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, contextId);
 518     // Translation enabled
 519
 520     TlbEntry *te = lookup(vaddr, contextId);
 521     if (te == NULL) {
 522         if (req->isPrefetch()){
 523            //if the request is a prefetch don't attempt to fill the TLB
 524            //or go any further with the memory access
 525            prefetchFaults++;
 526            return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss);
 527         }
 528
 529         if (is_fetch)
 530             instMisses++;
 531         else if (is_write)
 532             writeMisses++;
 533         else
 534             readMisses++;
 535
 536         // start translation table walk, pass variables rather than
 537         // re-retreaving in table walker for speed
 538         DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n",
 539                 vaddr, contextId);
 540         fault = tableWalker->walk(req, tc, contextId, mode, translation,
 541                 timing);
 542         if (timing && fault == NoFault) {
 543             delay = true;
 544             // for timing mode, return and wait for table walk
 545             return fault;
 546         }
 547         if (fault)
 548             return fault;
 549
 550         te = lookup(vaddr, contextId);
 551         if (!te)
 552             printTlb();
 553         assert(te);
 554     } else {
 555         if (is_fetch)
 556             instHits++;
 557         else if (is_write)
 558             writeHits++;
 559         else
 560             readHits++;
 561     }
 562
 563     // Set memory attributes
 564     DPRINTF(TLBVerbose,
 565             "Setting memory attributes: shareable: %d, innerAttrs: %d, \
 566             outerAttrs: %d\n",
 567             te->shareable, te->innerAttrs, te->outerAttrs);
 568     setAttr(te->attributes);
 569     if (te->nonCacheable) {
 570         req->setFlags(Request::UNCACHEABLE);
 571
 572         // Prevent prefetching from I/O devices.
 573         if (req->isPrefetch()) {
 574             return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable);
 575         }
 576     }
 577
 578     switch ( (dacr >> (te->domain * 2)) & 0x3) {
 579       case 0:
 580         domainFaults++;
 581         DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x"
 582                " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp);
 583         if (is_fetch)
 584             return new PrefetchAbort(vaddr,
 585                 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
 586         else
 587             return new DataAbort(vaddr, te->domain, is_write,
 588                 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
 589       case 1:
 590         // Continue with permissions check
 591         break;
 592       case 2:
 593         panic("UNPRED domain\n");
 594       case 3:
 595         req->setPaddr(te->pAddr(vaddr));
 596         fault = trickBoxCheck(req, mode, te->domain, te->sNp);
 597         if (fault)
 598             return fault;
 599         return NoFault;
 600     }
 601
 602     uint8_t ap = te->ap;
 603
 604     if (sctlr.afe == 1)
 605         ap |= 1;
 606
 607     bool abt;
 608
 609    /* if (!sctlr.xp)
 610         ap &= 0x3;
 611 */
 612     switch (ap) {
 613       case 0:
 614         DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs);
 615         if (!sctlr.xp) {
 616             switch ((int)sctlr.rs) {
 617               case 2:
 618                 abt = is_write;
 619                 break;
 620               case 1:
 621                 abt = is_write || !is_priv;
 622                 break;
 623               case 0:
 624               case 3:
 625               default:
 626                 abt = true;
 627                 break;
 628             }
 629         } else {
 630             abt = true;
 631         }
 632         break;
 633       case 1:
 634         abt = !is_priv;
 635         break;
 636       case 2:
 637         abt = !is_priv && is_write;
 638         break;
 639       case 3:
 640         abt = false;
 641         break;
 642       case 4:
 643         panic("UNPRED premissions\n");
 644       case 5:
 645         abt = !is_priv || is_write;
 646         break;
 647       case 6:
 648       case 7:
 649         abt = is_write;
 650         break;
 651       default:
 652         panic("Unknown permissions\n");
 653     }
 654     if ((is_fetch) && (abt || te->xn)) {
 655         permsFaults++;
 656         DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d"
 657                " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
 658         return new PrefetchAbort(vaddr,
 659                 (te->sNp ? ArmFault::Permission0 :
 660                  ArmFault::Permission1));
 661     } else if (abt) {
 662         permsFaults++;
 663         DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d"
 664                " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
 665         return new DataAbort(vaddr, te->domain, is_write,
 666                 (te->sNp ? ArmFault::Permission0 :
 667                  ArmFault::Permission1));
 668     }
 669
 670     req->setPaddr(te->pAddr(vaddr));
 671     // Check for a trickbox generated address fault
 672     fault = trickBoxCheck(req, mode, te->domain, te->sNp);
 673     if (fault)
 674         return fault;
 675
 676     return NoFault;
 677 }
 678
 679 #endif
 680
 681 Fault
 682 TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
 683 {
 684     bool delay = false;
 685     Fault fault;
 686 #if FULL_SYSTEM
 687     fault = translateFs(req, tc, mode, NULL, delay, false);
 688 #else
 689     fault = translateSe(req, tc, mode, NULL, delay, false);
 690 #endif
 691     assert(!delay);
 692     return fault;
 693 }
 694
 695 Fault
 696 TLB::translateTiming(RequestPtr req, ThreadContext *tc,
 697         Translation *translation, Mode mode)
 698 {
 699     assert(translation);
 700     bool delay = false;
 701     Fault fault;
 702 #if FULL_SYSTEM
 703     fault = translateFs(req, tc, mode, translation, delay, true);
 704 #else
 705     fault = translateSe(req, tc, mode, translation, delay, true);
 706 #endif
 707     DPRINTF(TLB, "Translation returning delay=%d fault=%d\n", delay, fault !=
 708             NoFault);
 709     if (!delay)
 710         translation->finish(fault, req, tc, mode);
 711     else
 712         translation->markDelayed();
 713     return fault;
 714 }
 715
 716 Port*
 717 TLB::getPort()
 718 {
 719 #if FULL_SYSTEM
 720     return tableWalker->getPort("port");
 721 #else
 722     return NULL;
 723 #endif
 724 }
 725
 726
 727
 728 ArmISA::TLB *
 729 ArmTLBParams::create()
 730 {
 731     return new ArmISA::TLB(this);
 732 }