2 * Copyright (c) 2010 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
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12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
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48 #include "arch/arm/faults.hh"
49 #include "arch/arm/pagetable.hh"
50 #include "arch/arm/tlb.hh"
51 #include "arch/arm/utility.hh"
52 #include "base/inifile.hh"
53 #include "base/str.hh"
54 #include "base/trace.hh"
55 #include "cpu/thread_context.hh"
56 #include "mem/page_table.hh"
57 #include "params/ArmTLB.hh"
58 #include "sim/process.hh"
61 #include "arch/arm/table_walker.hh"
65 using namespace ArmISA
;
67 TLB::TLB(const Params
*p
)
68 : BaseTLB(p
), size(p
->size
)
70 , tableWalker(p
->walker
)
72 , rangeMRU(1), miscRegValid(false)
74 table
= new TlbEntry
[size
];
75 memset(table
, 0, sizeof(TlbEntry
[size
]));
78 tableWalker
->setTlb(this);
89 TLB::translateFunctional(ThreadContext
*tc
, Addr va
, Addr
&pa
)
93 TlbEntry
*e
= lookup(va
, contextId
, true);
101 TLB::lookup(Addr va
, uint8_t cid
, bool functional
)
104 TlbEntry
*retval
= NULL
;
106 // Maitaining LRU array
109 while (retval
== NULL
&& x
< size
) {
110 if (table
[x
].match(va
, cid
)) {
112 // We only move the hit entry ahead when the position is higher than rangeMRU
114 TlbEntry tmp_entry
= table
[x
];
115 for(int i
= x
; i
> 0; i
--)
116 table
[i
] = table
[i
-1];
117 table
[0] = tmp_entry
;
127 DPRINTF(TLBVerbose
, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n",
128 va
, cid
, retval
? "hit" : "miss", retval
? retval
->pfn
: 0,
129 retval
? retval
->size
: 0, retval
? retval
->pAddr(va
) : 0,
130 retval
? retval
->ap
: 0);
135 // insert a new TLB entry
137 TLB::insert(Addr addr
, TlbEntry
&entry
)
139 DPRINTF(TLB
, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x"
140 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x"
141 " domain:%#x\n", entry
.pfn
, entry
.size
, entry
.vpn
, entry
.asid
,
142 entry
.N
, entry
.global
, entry
.valid
, entry
.nonCacheable
, entry
.sNp
,
143 entry
.xn
, entry
.ap
, entry
.domain
);
145 if (table
[size
-1].valid
)
146 DPRINTF(TLB
, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n",
147 table
[size
-1].vpn
<< table
[size
-1].N
, table
[size
-1].asid
,
148 table
[size
-1].pfn
<< table
[size
-1].N
, table
[size
-1].size
,
151 //inserting to MRU position and evicting the LRU one
153 for(int i
= size
-1; i
> 0; i
--)
154 table
[i
] = table
[i
-1];
165 DPRINTF(TLB
, "Current TLB contents:\n");
169 DPRINTF(TLB
, " * %#x, asn %d ppn %#x size: %#x ap:%d\n",
170 te
->vpn
<< te
->N
, te
->asid
, te
->pfn
<< te
->N
, te
->size
, te
->ap
);
179 DPRINTF(TLB
, "Flushing all TLB entries\n");
185 DPRINTF(TLB
, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
186 te
->vpn
<< te
->N
, te
->asid
, te
->pfn
<< te
->N
, te
->size
, te
->ap
);
192 memset(table
, 0, sizeof(TlbEntry
[size
]));
199 TLB::flushMvaAsid(Addr mva
, uint64_t asn
)
201 DPRINTF(TLB
, "Flushing mva %#x asid: %#x\n", mva
, asn
);
204 te
= lookup(mva
, asn
);
206 DPRINTF(TLB
, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
207 te
->vpn
<< te
->N
, te
->asid
, te
->pfn
<< te
->N
, te
->size
, te
->ap
);
210 te
= lookup(mva
,asn
);
216 TLB::flushAsid(uint64_t asn
)
218 DPRINTF(TLB
, "Flushing all entries with asid: %#x\n", asn
);
225 if (te
->asid
== asn
) {
227 DPRINTF(TLB
, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
228 te
->vpn
<< te
->N
, te
->asid
, te
->pfn
<< te
->N
, te
->size
, te
->ap
);
237 TLB::flushMva(Addr mva
)
239 DPRINTF(TLB
, "Flushing all entries with mva: %#x\n", mva
);
246 Addr v
= te
->vpn
<< te
->N
;
247 if (mva
>= v
&& mva
< v
+ te
->size
) {
249 DPRINTF(TLB
, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
250 te
->vpn
<< te
->N
, te
->asid
, te
->pfn
<< te
->N
, te
->size
, te
->ap
);
259 TLB::serialize(ostream
&os
)
261 DPRINTF(Checkpoint
, "Serializing Arm TLB\n");
263 SERIALIZE_SCALAR(_attr
);
264 for(int i
= 0; i
< size
; i
++){
265 nameOut(os
, csprintf("%s.TlbEntry%d", name(), i
));
266 table
[i
].serialize(os
);
271 TLB::unserialize(Checkpoint
*cp
, const string
§ion
)
273 DPRINTF(Checkpoint
, "Unserializing Arm TLB\n");
275 UNSERIALIZE_SCALAR(_attr
);
276 for(int i
= 0; i
< size
; i
++){
277 table
[i
].unserialize(cp
, csprintf("%s.TlbEntry%d", section
, i
));
279 miscRegValid
= false;
286 .name(name() + ".inst_hits")
287 .desc("ITB inst hits")
291 .name(name() + ".inst_misses")
292 .desc("ITB inst misses")
296 .name(name() + ".inst_accesses")
297 .desc("ITB inst accesses")
301 .name(name() + ".read_hits")
302 .desc("DTB read hits")
306 .name(name() + ".read_misses")
307 .desc("DTB read misses")
311 .name(name() + ".read_accesses")
312 .desc("DTB read accesses")
316 .name(name() + ".write_hits")
317 .desc("DTB write hits")
321 .name(name() + ".write_misses")
322 .desc("DTB write misses")
326 .name(name() + ".write_accesses")
327 .desc("DTB write accesses")
331 .name(name() + ".hits")
336 .name(name() + ".misses")
341 .name(name() + ".accesses")
342 .desc("DTB accesses")
346 .name(name() + ".flush_tlb")
347 .desc("Number of times complete TLB was flushed")
351 .name(name() + ".flush_tlb_mva")
352 .desc("Number of times TLB was flushed by MVA")
356 .name(name() + ".flush_tlb_mva_asid")
357 .desc("Number of times TLB was flushed by MVA & ASID")
361 .name(name() + ".flush_tlb_asid")
362 .desc("Number of times TLB was flushed by ASID")
366 .name(name() + ".flush_entries")
367 .desc("Number of entries that have been flushed from TLB")
371 .name(name() + ".align_faults")
372 .desc("Number of TLB faults due to alignment restrictions")
376 .name(name() + ".prefetch_faults")
377 .desc("Number of TLB faults due to prefetch")
381 .name(name() + ".domain_faults")
382 .desc("Number of TLB faults due to domain restrictions")
386 .name(name() + ".perms_faults")
387 .desc("Number of TLB faults due to permissions restrictions")
390 instAccesses
= instHits
+ instMisses
;
391 readAccesses
= readHits
+ readMisses
;
392 writeAccesses
= writeHits
+ writeMisses
;
393 hits
= readHits
+ writeHits
+ instHits
;
394 misses
= readMisses
+ writeMisses
+ instMisses
;
395 accesses
= readAccesses
+ writeAccesses
+ instAccesses
;
400 TLB::translateSe(RequestPtr req
, ThreadContext
*tc
, Mode mode
,
401 Translation
*translation
, bool &delay
, bool timing
)
405 Addr vaddr
= req
->getVaddr();
406 uint32_t flags
= req
->getFlags();
408 bool is_fetch
= (mode
== Execute
);
409 bool is_write
= (mode
== Write
);
412 assert(flags
& MustBeOne
);
413 if (sctlr
.a
|| !(flags
& AllowUnaligned
)) {
414 if (vaddr
& flags
& AlignmentMask
) {
415 return new DataAbort(vaddr
, 0, is_write
, ArmFault::AlignmentFault
);
421 Process
*p
= tc
->getProcessPtr();
423 if (!p
->pTable
->translate(vaddr
, paddr
))
424 return Fault(new GenericPageTableFault(vaddr
));
425 req
->setPaddr(paddr
);
433 TLB::trickBoxCheck(RequestPtr req
, Mode mode
, uint8_t domain
, bool sNp
)
439 TLB::walkTrickBoxCheck(Addr pa
, Addr va
, Addr sz
, bool is_exec
,
440 bool is_write
, uint8_t domain
, bool sNp
)
446 TLB::translateFs(RequestPtr req
, ThreadContext
*tc
, Mode mode
,
447 Translation
*translation
, bool &delay
, bool timing
)
452 Addr vaddr
= req
->getVaddr();
453 uint32_t flags
= req
->getFlags();
455 bool is_fetch
= (mode
== Execute
);
456 bool is_write
= (mode
== Write
);
457 bool is_priv
= isPriv
&& !(flags
& UserMode
);
459 DPRINTF(TLBVerbose
, "CPSR is user:%d UserMode:%d\n",
460 isPriv
, flags
& UserMode
);
461 // If this is a clrex instruction, provide a PA of 0 with no fault
462 // This will force the monitor to set the tracked address to 0
463 // a bit of a hack but this effectively clrears this processors monitor
464 if (flags
& Request::CLEAR_LL
){
466 req
->setFlags(Request::UNCACHEABLE
);
467 req
->setFlags(Request::CLEAR_LL
);
470 if ((req
->isInstFetch() && (!sctlr
.i
)) ||
471 ((!req
->isInstFetch()) && (!sctlr
.c
))){
472 req
->setFlags(Request::UNCACHEABLE
);
475 assert(flags
& MustBeOne
);
476 if (sctlr
.a
|| !(flags
& AllowUnaligned
)) {
477 if (vaddr
& flags
& AlignmentMask
) {
479 return new DataAbort(vaddr
, 0, is_write
, ArmFault::AlignmentFault
);
487 req
->setPaddr(vaddr
);
488 if (sctlr
.tre
== 0) {
489 req
->setFlags(Request::UNCACHEABLE
);
491 if (nmrr
.ir0
== 0 || nmrr
.or0
== 0 || prrr
.tr0
!= 0x2)
492 req
->setFlags(Request::UNCACHEABLE
);
495 // Set memory attributes
497 tableWalker
->memAttrs(tc
, temp_te
, sctlr
, 0, 1);
498 temp_te
.shareable
= true;
499 DPRINTF(TLBVerbose
, "(No MMU) setting memory attributes: shareable:\
500 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te
.shareable
,
501 temp_te
.innerAttrs
, temp_te
.outerAttrs
);
502 setAttr(temp_te
.attributes
);
504 return trickBoxCheck(req
, mode
, 0, false);
507 DPRINTF(TLBVerbose
, "Translating vaddr=%#x context=%d\n", vaddr
, contextId
);
508 // Translation enabled
510 TlbEntry
*te
= lookup(vaddr
, contextId
);
512 if (req
->isPrefetch()){
513 //if the request is a prefetch don't attempt to fill the TLB
514 //or go any further with the memory access
516 return new PrefetchAbort(vaddr
, ArmFault::PrefetchTLBMiss
);
526 // start translation table walk, pass variables rather than
527 // re-retreaving in table walker for speed
528 DPRINTF(TLB
, "TLB Miss: Starting hardware table walker for %#x(%d)\n",
530 fault
= tableWalker
->walk(req
, tc
, contextId
, mode
, translation
,
534 // for timing mode, return and wait for table walk
540 te
= lookup(vaddr
, contextId
);
553 // Set memory attributes
555 "Setting memory attributes: shareable: %d, innerAttrs: %d, \
557 te
->shareable
, te
->innerAttrs
, te
->outerAttrs
);
558 setAttr(te
->attributes
);
559 if (te
->nonCacheable
) {
560 req
->setFlags(Request::UNCACHEABLE
);
562 // Prevent prefetching from I/O devices.
563 if (req
->isPrefetch()) {
564 return new PrefetchAbort(vaddr
, ArmFault::PrefetchUncacheable
);
568 switch ( (dacr
>> (te
->domain
* 2)) & 0x3) {
571 DPRINTF(TLB
, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x"
572 " write:%d sNp:%d\n", dacr
, te
->domain
, is_write
, te
->sNp
);
574 return new PrefetchAbort(vaddr
,
575 (te
->sNp
? ArmFault::Domain0
: ArmFault::Domain1
));
577 return new DataAbort(vaddr
, te
->domain
, is_write
,
578 (te
->sNp
? ArmFault::Domain0
: ArmFault::Domain1
));
580 // Continue with permissions check
583 panic("UNPRED domain\n");
585 req
->setPaddr(te
->pAddr(vaddr
));
586 fault
= trickBoxCheck(req
, mode
, te
->domain
, te
->sNp
);
604 DPRINTF(TLB
, "Access permissions 0, checking rs:%#x\n", (int)sctlr
.rs
);
606 switch ((int)sctlr
.rs
) {
611 abt
= is_write
|| !is_priv
;
627 abt
= !is_priv
&& is_write
;
633 panic("UNPRED premissions\n");
635 abt
= !is_priv
|| is_write
;
642 panic("Unknown permissions\n");
644 if ((is_fetch
) && (abt
|| te
->xn
)) {
646 DPRINTF(TLB
, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d"
647 " write:%d sNp:%d\n", ap
, is_priv
, is_write
, te
->sNp
);
648 return new PrefetchAbort(vaddr
,
649 (te
->sNp
? ArmFault::Permission0
:
650 ArmFault::Permission1
));
653 DPRINTF(TLB
, "TLB Fault: Data abort on permission check. AP:%d priv:%d"
654 " write:%d sNp:%d\n", ap
, is_priv
, is_write
, te
->sNp
);
655 return new DataAbort(vaddr
, te
->domain
, is_write
,
656 (te
->sNp
? ArmFault::Permission0
:
657 ArmFault::Permission1
));
660 req
->setPaddr(te
->pAddr(vaddr
));
661 // Check for a trickbox generated address fault
662 fault
= trickBoxCheck(req
, mode
, te
->domain
, te
->sNp
);
672 TLB::translateAtomic(RequestPtr req
, ThreadContext
*tc
, Mode mode
)
677 fault
= translateFs(req
, tc
, mode
, NULL
, delay
, false);
679 fault
= translateSe(req
, tc
, mode
, NULL
, delay
, false);
686 TLB::translateTiming(RequestPtr req
, ThreadContext
*tc
,
687 Translation
*translation
, Mode mode
)
693 fault
= translateFs(req
, tc
, mode
, translation
, delay
, true);
695 fault
= translateSe(req
, tc
, mode
, translation
, delay
, true);
698 translation
->finish(fault
, req
, tc
, mode
);
706 return tableWalker
->getPort("port");
715 ArmTLBParams::create()
717 return new ArmISA::TLB(this);