2 * Copyright (c) 2010-2013, 2016-2019 ARM Limited
5 * The license below extends only to copyright in the software and shall
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45 #include "arch/arm/tlb.hh"
51 #include "arch/arm/faults.hh"
52 #include "arch/arm/pagetable.hh"
53 #include "arch/arm/stage2_lookup.hh"
54 #include "arch/arm/stage2_mmu.hh"
55 #include "arch/arm/system.hh"
56 #include "arch/arm/table_walker.hh"
57 #include "arch/arm/utility.hh"
58 #include "arch/generic/mmapped_ipr.hh"
59 #include "base/inifile.hh"
60 #include "base/str.hh"
61 #include "base/trace.hh"
62 #include "cpu/base.hh"
63 #include "cpu/thread_context.hh"
64 #include "debug/Checkpoint.hh"
65 #include "debug/TLB.hh"
66 #include "debug/TLBVerbose.hh"
67 #include "mem/page_table.hh"
68 #include "mem/request.hh"
69 #include "params/ArmTLB.hh"
70 #include "sim/full_system.hh"
71 #include "sim/process.hh"
74 using namespace ArmISA
;
76 TLB::TLB(const ArmTLBParams
*p
)
77 : BaseTLB(p
), table(new TlbEntry
[p
->size
]), size(p
->size
),
78 isStage2(p
->is_stage2
), stage2Req(false), stage2DescReq(false), _attr(0),
79 directToStage2(false), tableWalker(p
->walker
), stage2Tlb(NULL
),
80 stage2Mmu(NULL
), test(nullptr), rangeMRU(1),
81 aarch64(false), aarch64EL(EL0
), isPriv(false), isSecure(false),
82 isHyp(false), asid(0), vmid(0), hcr(0), dacr(0),
83 miscRegValid(false), miscRegContext(0), curTranType(NormalTran
)
85 const ArmSystem
*sys
= dynamic_cast<const ArmSystem
*>(p
->sys
);
87 tableWalker
->setTlb(this);
89 // Cache system-level properties
90 haveLPAE
= tableWalker
->haveLPAE();
91 haveVirtualization
= tableWalker
->haveVirtualization();
92 haveLargeAsid64
= tableWalker
->haveLargeAsid64();
95 m5opRange
= sys
->m5opRange();
106 if (stage2Mmu
&& !isStage2
)
107 stage2Tlb
= stage2Mmu
->stage2Tlb();
111 TLB::setMMU(Stage2MMU
*m
, MasterID master_id
)
114 tableWalker
->setMMU(m
, master_id
);
118 TLB::translateFunctional(ThreadContext
*tc
, Addr va
, Addr
&pa
)
122 if (directToStage2
) {
124 return stage2Tlb
->translateFunctional(tc
, va
, pa
);
127 TlbEntry
*e
= lookup(va
, asid
, vmid
, isHyp
, isSecure
, true, false,
128 aarch64
? aarch64EL
: EL1
);
136 TLB::finalizePhysical(const RequestPtr
&req
,
137 ThreadContext
*tc
, Mode mode
) const
139 const Addr paddr
= req
->getPaddr();
141 if (m5opRange
.contains(paddr
)) {
142 req
->setFlags(Request::MMAPPED_IPR
| Request::GENERIC_IPR
);
143 req
->setPaddr(GenericISA::iprAddressPseudoInst(
152 TLB::lookup(Addr va
, uint16_t asn
, uint8_t vmid
, bool hyp
, bool secure
,
153 bool functional
, bool ignore_asn
, ExceptionLevel target_el
)
156 TlbEntry
*retval
= NULL
;
158 // Maintaining LRU array
160 while (retval
== NULL
&& x
< size
) {
161 if ((!ignore_asn
&& table
[x
].match(va
, asn
, vmid
, hyp
, secure
, false,
163 (ignore_asn
&& table
[x
].match(va
, vmid
, hyp
, secure
, target_el
))) {
164 // We only move the hit entry ahead when the position is higher
166 if (x
> rangeMRU
&& !functional
) {
167 TlbEntry tmp_entry
= table
[x
];
168 for (int i
= x
; i
> 0; i
--)
169 table
[i
] = table
[i
- 1];
170 table
[0] = tmp_entry
;
180 DPRINTF(TLBVerbose
, "Lookup %#x, asn %#x -> %s vmn 0x%x hyp %d secure %d "
181 "ppn %#x size: %#x pa: %#x ap:%d ns:%d nstid:%d g:%d asid: %d "
183 va
, asn
, retval
? "hit" : "miss", vmid
, hyp
, secure
,
184 retval
? retval
->pfn
: 0, retval
? retval
->size
: 0,
185 retval
? retval
->pAddr(va
) : 0, retval
? retval
->ap
: 0,
186 retval
? retval
->ns
: 0, retval
? retval
->nstid
: 0,
187 retval
? retval
->global
: 0, retval
? retval
->asid
: 0,
188 retval
? retval
->el
: 0);
193 // insert a new TLB entry
195 TLB::insert(Addr addr
, TlbEntry
&entry
)
197 DPRINTF(TLB
, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x"
198 " asid:%d vmid:%d N:%d global:%d valid:%d nc:%d xn:%d"
199 " ap:%#x domain:%#x ns:%d nstid:%d isHyp:%d\n", entry
.pfn
,
200 entry
.size
, entry
.vpn
, entry
.asid
, entry
.vmid
, entry
.N
,
201 entry
.global
, entry
.valid
, entry
.nonCacheable
, entry
.xn
,
202 entry
.ap
, static_cast<uint8_t>(entry
.domain
), entry
.ns
, entry
.nstid
,
205 if (table
[size
- 1].valid
)
206 DPRINTF(TLB
, " - Replacing Valid entry %#x, asn %d vmn %d ppn %#x "
207 "size: %#x ap:%d ns:%d nstid:%d g:%d isHyp:%d el: %d\n",
208 table
[size
-1].vpn
<< table
[size
-1].N
, table
[size
-1].asid
,
209 table
[size
-1].vmid
, table
[size
-1].pfn
<< table
[size
-1].N
,
210 table
[size
-1].size
, table
[size
-1].ap
, table
[size
-1].ns
,
211 table
[size
-1].nstid
, table
[size
-1].global
, table
[size
-1].isHyp
,
214 //inserting to MRU position and evicting the LRU one
216 for (int i
= size
- 1; i
> 0; --i
)
217 table
[i
] = table
[i
-1];
221 ppRefills
->notify(1);
225 TLB::printTlb() const
229 DPRINTF(TLB
, "Current TLB contents:\n");
233 DPRINTF(TLB
, " * %s\n", te
->print());
239 TLB::flushAllSecurity(bool secure_lookup
, ExceptionLevel target_el
,
242 DPRINTF(TLB
, "Flushing all TLB entries (%s lookup)\n",
243 (secure_lookup
? "secure" : "non-secure"));
248 const bool el_match
= ignore_el
?
249 true : te
->checkELMatch(target_el
);
251 if (te
->valid
&& secure_lookup
== !te
->nstid
&&
252 (te
->vmid
== vmid
|| secure_lookup
) && el_match
) {
254 DPRINTF(TLB
, " - %s\n", te
->print());
263 // If there's a second stage TLB (and we're not it) then flush it as well
264 // if we're currently in hyp mode
265 if (!isStage2
&& isHyp
) {
266 stage2Tlb
->flushAllSecurity(secure_lookup
, EL1
, true);
271 TLB::flushAllNs(ExceptionLevel target_el
, bool ignore_el
)
273 bool hyp
= target_el
== EL2
;
275 DPRINTF(TLB
, "Flushing all NS TLB entries (%s lookup)\n",
276 (hyp
? "hyp" : "non-hyp"));
281 const bool el_match
= ignore_el
?
282 true : te
->checkELMatch(target_el
);
284 if (te
->valid
&& te
->nstid
&& te
->isHyp
== hyp
&& el_match
) {
286 DPRINTF(TLB
, " - %s\n", te
->print());
295 // If there's a second stage TLB (and we're not it) then flush it as well
296 if (!isStage2
&& !hyp
) {
297 stage2Tlb
->flushAllNs(EL1
, true);
302 TLB::flushMvaAsid(Addr mva
, uint64_t asn
, bool secure_lookup
,
303 ExceptionLevel target_el
)
305 DPRINTF(TLB
, "Flushing TLB entries with mva: %#x, asid: %#x "
306 "(%s lookup)\n", mva
, asn
, (secure_lookup
?
307 "secure" : "non-secure"));
308 _flushMva(mva
, asn
, secure_lookup
, false, target_el
);
313 TLB::flushAsid(uint64_t asn
, bool secure_lookup
, ExceptionLevel target_el
)
315 DPRINTF(TLB
, "Flushing TLB entries with asid: %#x (%s lookup)\n", asn
,
316 (secure_lookup
? "secure" : "non-secure"));
323 if (te
->valid
&& te
->asid
== asn
&& secure_lookup
== !te
->nstid
&&
324 (te
->vmid
== vmid
|| secure_lookup
) &&
325 te
->checkELMatch(target_el
)) {
328 DPRINTF(TLB
, " - %s\n", te
->print());
337 TLB::flushMva(Addr mva
, bool secure_lookup
, ExceptionLevel target_el
)
339 DPRINTF(TLB
, "Flushing TLB entries with mva: %#x (%s lookup)\n", mva
,
340 (secure_lookup
? "secure" : "non-secure"));
341 _flushMva(mva
, 0xbeef, secure_lookup
, true, target_el
);
346 TLB::_flushMva(Addr mva
, uint64_t asn
, bool secure_lookup
,
347 bool ignore_asn
, ExceptionLevel target_el
)
350 // D5.7.2: Sign-extend address to 64 bits
353 bool hyp
= target_el
== EL2
;
355 te
= lookup(mva
, asn
, vmid
, hyp
, secure_lookup
, false, ignore_asn
,
358 if (secure_lookup
== !te
->nstid
) {
359 DPRINTF(TLB
, " - %s\n", te
->print());
363 te
= lookup(mva
, asn
, vmid
, hyp
, secure_lookup
, false, ignore_asn
,
369 TLB::flushIpaVmid(Addr ipa
, bool secure_lookup
, ExceptionLevel target_el
)
372 stage2Tlb
->_flushMva(ipa
, 0xbeef, secure_lookup
, true, target_el
);
378 // We might have unserialized something or switched CPUs, so make
379 // sure to re-read the misc regs.
380 miscRegValid
= false;
384 TLB::takeOverFrom(BaseTLB
*_otlb
)
386 TLB
*otlb
= dynamic_cast<TLB
*>(_otlb
);
387 /* Make sure we actually have a valid type */
390 haveLPAE
= otlb
->haveLPAE
;
391 directToStage2
= otlb
->directToStage2
;
392 stage2Req
= otlb
->stage2Req
;
393 stage2DescReq
= otlb
->stage2DescReq
;
395 /* Sync the stage2 MMU if they exist in both
396 * the old CPU and the new
399 stage2Tlb
&& otlb
->stage2Tlb
) {
400 stage2Tlb
->takeOverFrom(otlb
->stage2Tlb
);
403 panic("Incompatible TLB type!");
408 TLB::serialize(CheckpointOut
&cp
) const
410 DPRINTF(Checkpoint
, "Serializing Arm TLB\n");
412 SERIALIZE_SCALAR(_attr
);
413 SERIALIZE_SCALAR(haveLPAE
);
414 SERIALIZE_SCALAR(directToStage2
);
415 SERIALIZE_SCALAR(stage2Req
);
416 SERIALIZE_SCALAR(stage2DescReq
);
418 int num_entries
= size
;
419 SERIALIZE_SCALAR(num_entries
);
420 for (int i
= 0; i
< size
; i
++)
421 table
[i
].serializeSection(cp
, csprintf("TlbEntry%d", i
));
425 TLB::unserialize(CheckpointIn
&cp
)
427 DPRINTF(Checkpoint
, "Unserializing Arm TLB\n");
429 UNSERIALIZE_SCALAR(_attr
);
430 UNSERIALIZE_SCALAR(haveLPAE
);
431 UNSERIALIZE_SCALAR(directToStage2
);
432 UNSERIALIZE_SCALAR(stage2Req
);
433 UNSERIALIZE_SCALAR(stage2DescReq
);
436 UNSERIALIZE_SCALAR(num_entries
);
437 for (int i
= 0; i
< min(size
, num_entries
); i
++)
438 table
[i
].unserializeSection(cp
, csprintf("TlbEntry%d", i
));
446 .name(name() + ".inst_hits")
447 .desc("ITB inst hits")
451 .name(name() + ".inst_misses")
452 .desc("ITB inst misses")
456 .name(name() + ".inst_accesses")
457 .desc("ITB inst accesses")
461 .name(name() + ".read_hits")
462 .desc("DTB read hits")
466 .name(name() + ".read_misses")
467 .desc("DTB read misses")
471 .name(name() + ".read_accesses")
472 .desc("DTB read accesses")
476 .name(name() + ".write_hits")
477 .desc("DTB write hits")
481 .name(name() + ".write_misses")
482 .desc("DTB write misses")
486 .name(name() + ".write_accesses")
487 .desc("DTB write accesses")
491 .name(name() + ".hits")
496 .name(name() + ".misses")
501 .name(name() + ".accesses")
502 .desc("DTB accesses")
506 .name(name() + ".flush_tlb")
507 .desc("Number of times complete TLB was flushed")
511 .name(name() + ".flush_tlb_mva")
512 .desc("Number of times TLB was flushed by MVA")
516 .name(name() + ".flush_tlb_mva_asid")
517 .desc("Number of times TLB was flushed by MVA & ASID")
521 .name(name() + ".flush_tlb_asid")
522 .desc("Number of times TLB was flushed by ASID")
526 .name(name() + ".flush_entries")
527 .desc("Number of entries that have been flushed from TLB")
531 .name(name() + ".align_faults")
532 .desc("Number of TLB faults due to alignment restrictions")
536 .name(name() + ".prefetch_faults")
537 .desc("Number of TLB faults due to prefetch")
541 .name(name() + ".domain_faults")
542 .desc("Number of TLB faults due to domain restrictions")
546 .name(name() + ".perms_faults")
547 .desc("Number of TLB faults due to permissions restrictions")
550 instAccesses
= instHits
+ instMisses
;
551 readAccesses
= readHits
+ readMisses
;
552 writeAccesses
= writeHits
+ writeMisses
;
553 hits
= readHits
+ writeHits
+ instHits
;
554 misses
= readMisses
+ writeMisses
+ instMisses
;
555 accesses
= readAccesses
+ writeAccesses
+ instAccesses
;
559 TLB::regProbePoints()
561 ppRefills
.reset(new ProbePoints::PMU(getProbeManager(), "Refills"));
565 TLB::translateSe(const RequestPtr
&req
, ThreadContext
*tc
, Mode mode
,
566 Translation
*translation
, bool &delay
, bool timing
)
569 Addr vaddr_tainted
= req
->getVaddr();
572 vaddr
= purifyTaggedAddr(vaddr_tainted
, tc
, aarch64EL
, ttbcr
);
574 vaddr
= vaddr_tainted
;
575 Request::Flags flags
= req
->getFlags();
577 bool is_fetch
= (mode
== Execute
);
578 bool is_write
= (mode
== Write
);
581 assert(flags
& MustBeOne
|| req
->isPrefetch());
582 if (sctlr
.a
|| !(flags
& AllowUnaligned
)) {
583 if (vaddr
& mask(flags
& AlignmentMask
)) {
584 // LPAE is always disabled in SE mode
585 return std::make_shared
<DataAbort
>(
587 TlbEntry::DomainType::NoAccess
, is_write
,
588 ArmFault::AlignmentFault
, isStage2
,
595 Process
*p
= tc
->getProcessPtr();
597 if (!p
->pTable
->translate(vaddr
, paddr
))
598 return std::make_shared
<GenericPageTableFault
>(vaddr_tainted
);
599 req
->setPaddr(paddr
);
601 return finalizePhysical(req
, tc
, mode
);
605 TLB::checkPermissions(TlbEntry
*te
, const RequestPtr
&req
, Mode mode
)
607 // a data cache maintenance instruction that operates by MVA does
608 // not generate a Data Abort exeception due to a Permission fault
609 if (req
->isCacheMaintenance()) {
613 Addr vaddr
= req
->getVaddr(); // 32-bit don't have to purify
614 Request::Flags flags
= req
->getFlags();
615 bool is_fetch
= (mode
== Execute
);
616 bool is_write
= (mode
== Write
);
617 bool is_priv
= isPriv
&& !(flags
& UserMode
);
619 // Get the translation type from the actuall table entry
620 ArmFault::TranMethod tranMethod
= te
->longDescFormat
? ArmFault::LpaeTran
621 : ArmFault::VmsaTran
;
623 // If this is the second stage of translation and the request is for a
624 // stage 1 page table walk then we need to check the HCR.PTW bit. This
625 // allows us to generate a fault if the request targets an area marked
626 // as a device or strongly ordered.
627 if (isStage2
&& req
->isPTWalk() && hcr
.ptw
&&
628 (te
->mtype
!= TlbEntry::MemoryType::Normal
)) {
629 return std::make_shared
<DataAbort
>(
630 vaddr
, te
->domain
, is_write
,
631 ArmFault::PermissionLL
+ te
->lookupLevel
,
632 isStage2
, tranMethod
);
635 // Generate an alignment fault for unaligned data accesses to device or
636 // strongly ordered memory
638 if (te
->mtype
!= TlbEntry::MemoryType::Normal
) {
639 if (vaddr
& mask(flags
& AlignmentMask
)) {
641 return std::make_shared
<DataAbort
>(
642 vaddr
, TlbEntry::DomainType::NoAccess
, is_write
,
643 ArmFault::AlignmentFault
, isStage2
,
649 if (te
->nonCacheable
) {
650 // Prevent prefetching from I/O devices.
651 if (req
->isPrefetch()) {
652 // Here we can safely use the fault status for the short
653 // desc. format in all cases
654 return std::make_shared
<PrefetchAbort
>(
655 vaddr
, ArmFault::PrefetchUncacheable
,
656 isStage2
, tranMethod
);
660 if (!te
->longDescFormat
) {
661 switch ((dacr
>> (static_cast<uint8_t>(te
->domain
) * 2)) & 0x3) {
664 DPRINTF(TLB
, "TLB Fault: Data abort on domain. DACR: %#x"
665 " domain: %#x write:%d\n", dacr
,
666 static_cast<uint8_t>(te
->domain
), is_write
);
668 // Use PC value instead of vaddr because vaddr might
669 // be aligned to cache line and should not be the
670 // address reported in FAR
671 return std::make_shared
<PrefetchAbort
>(
673 ArmFault::DomainLL
+ te
->lookupLevel
,
674 isStage2
, tranMethod
);
676 return std::make_shared
<DataAbort
>(
677 vaddr
, te
->domain
, is_write
,
678 ArmFault::DomainLL
+ te
->lookupLevel
,
679 isStage2
, tranMethod
);
681 // Continue with permissions check
684 panic("UNPRED domain\n");
690 // The 'ap' variable is AP[2:0] or {AP[2,1],1b'0}, i.e. always three bits
691 uint8_t ap
= te
->longDescFormat
? te
->ap
<< 1 : te
->ap
;
692 uint8_t hap
= te
->hap
;
694 if (sctlr
.afe
== 1 || te
->longDescFormat
)
698 bool isWritable
= true;
699 // If this is a stage 2 access (eg for reading stage 1 page table entries)
700 // then don't perform the AP permissions check, we stil do the HAP check
707 DPRINTF(TLB
, "Access permissions 0, checking rs:%#x\n",
710 switch ((int)sctlr
.rs
) {
715 abt
= is_write
|| !is_priv
;
731 abt
= !is_priv
&& is_write
;
732 isWritable
= is_priv
;
738 panic("UNPRED premissions\n");
740 abt
= !is_priv
|| is_write
;
749 panic("Unknown permissions %#x\n", ap
);
753 bool hapAbt
= is_write
? !(hap
& 2) : !(hap
& 1);
754 bool xn
= te
->xn
|| (isWritable
&& sctlr
.wxn
) ||
755 (ap
== 3 && sctlr
.uwxn
&& is_priv
);
756 if (is_fetch
&& (abt
|| xn
||
757 (te
->longDescFormat
&& te
->pxn
&& is_priv
) ||
758 (isSecure
&& te
->ns
&& scr
.sif
))) {
760 DPRINTF(TLB
, "TLB Fault: Prefetch abort on permission check. AP:%d "
761 "priv:%d write:%d ns:%d sif:%d sctlr.afe: %d \n",
762 ap
, is_priv
, is_write
, te
->ns
, scr
.sif
,sctlr
.afe
);
763 // Use PC value instead of vaddr because vaddr might be aligned to
764 // cache line and should not be the address reported in FAR
765 return std::make_shared
<PrefetchAbort
>(
767 ArmFault::PermissionLL
+ te
->lookupLevel
,
768 isStage2
, tranMethod
);
769 } else if (abt
| hapAbt
) {
771 DPRINTF(TLB
, "TLB Fault: Data abort on permission check. AP:%d priv:%d"
772 " write:%d\n", ap
, is_priv
, is_write
);
773 return std::make_shared
<DataAbort
>(
774 vaddr
, te
->domain
, is_write
,
775 ArmFault::PermissionLL
+ te
->lookupLevel
,
776 isStage2
| !abt
, tranMethod
);
783 TLB::checkPermissions64(TlbEntry
*te
, const RequestPtr
&req
, Mode mode
,
788 // A data cache maintenance instruction that operates by VA does
789 // not generate a Permission fault unless:
790 // * It is a data cache invalidate (dc ivac) which requires write
791 // permissions to the VA, or
792 // * It is executed from EL0
793 if (req
->isCacheClean() && aarch64EL
!= EL0
&& !isStage2
) {
797 Addr vaddr_tainted
= req
->getVaddr();
798 Addr vaddr
= purifyTaggedAddr(vaddr_tainted
, tc
, aarch64EL
, ttbcr
);
800 Request::Flags flags
= req
->getFlags();
801 bool is_fetch
= (mode
== Execute
);
802 // Cache clean operations require read permissions to the specified VA
803 bool is_write
= !req
->isCacheClean() && mode
== Write
;
804 bool is_priv M5_VAR_USED
= isPriv
&& !(flags
& UserMode
);
806 updateMiscReg(tc
, curTranType
);
808 // If this is the second stage of translation and the request is for a
809 // stage 1 page table walk then we need to check the HCR.PTW bit. This
810 // allows us to generate a fault if the request targets an area marked
811 // as a device or strongly ordered.
812 if (isStage2
&& req
->isPTWalk() && hcr
.ptw
&&
813 (te
->mtype
!= TlbEntry::MemoryType::Normal
)) {
814 return std::make_shared
<DataAbort
>(
815 vaddr_tainted
, te
->domain
, is_write
,
816 ArmFault::PermissionLL
+ te
->lookupLevel
,
817 isStage2
, ArmFault::LpaeTran
);
820 // Generate an alignment fault for unaligned accesses to device or
821 // strongly ordered memory
823 if (te
->mtype
!= TlbEntry::MemoryType::Normal
) {
824 if (vaddr
& mask(flags
& AlignmentMask
)) {
826 return std::make_shared
<DataAbort
>(
828 TlbEntry::DomainType::NoAccess
, is_write
,
829 ArmFault::AlignmentFault
, isStage2
,
835 if (te
->nonCacheable
) {
836 // Prevent prefetching from I/O devices.
837 if (req
->isPrefetch()) {
838 // Here we can safely use the fault status for the short
839 // desc. format in all cases
840 return std::make_shared
<PrefetchAbort
>(
842 ArmFault::PrefetchUncacheable
,
843 isStage2
, ArmFault::LpaeTran
);
847 uint8_t ap
= 0x3 & (te
->ap
); // 2-bit access protection field
851 uint8_t pxn
= te
->pxn
;
852 bool r
= !is_write
&& !is_fetch
;
855 DPRINTF(TLBVerbose
, "Checking permissions: ap:%d, xn:%d, pxn:%d, r:%d, "
856 "w:%d, x:%d\n", ap
, xn
, pxn
, r
, w
, x
);
859 assert(ArmSystem::haveVirtualization(tc
) && aarch64EL
!= EL2
);
860 // In stage 2 we use the hypervisor access permission bits.
861 // The following permissions are described in ARM DDI 0487A.f
863 uint8_t hap
= 0x3 & te
->hap
;
865 // sctlr.wxn overrides the xn bit
866 grant
= !sctlr
.wxn
&& !xn
;
867 } else if (is_write
) {
876 uint8_t perm
= (ap
<< 2) | (xn
<< 1) | pxn
;
886 grant
= r
|| w
|| (x
&& !sctlr
.wxn
);
907 if (checkPAN(tc
, ap
, req
, mode
)) {
912 uint8_t perm
= (ap
<< 2) | (xn
<< 1) | pxn
;
916 grant
= r
|| w
|| (x
&& !sctlr
.wxn
);
924 // regions that are writeable at EL0 should not be
946 if (hcr
.e2h
&& checkPAN(tc
, ap
, req
, mode
)) {
953 uint8_t perm
= (ap
& 0x2) | xn
;
956 grant
= r
|| w
|| (x
&& !sctlr
.wxn
) ;
978 DPRINTF(TLB
, "TLB Fault: Prefetch abort on permission check. "
979 "AP:%d priv:%d write:%d ns:%d sif:%d "
981 ap
, is_priv
, is_write
, te
->ns
, scr
.sif
, sctlr
.afe
);
982 // Use PC value instead of vaddr because vaddr might be aligned to
983 // cache line and should not be the address reported in FAR
984 return std::make_shared
<PrefetchAbort
>(
986 ArmFault::PermissionLL
+ te
->lookupLevel
,
987 isStage2
, ArmFault::LpaeTran
);
990 DPRINTF(TLB
, "TLB Fault: Data abort on permission check. AP:%d "
991 "priv:%d write:%d\n", ap
, is_priv
, is_write
);
992 return std::make_shared
<DataAbort
>(
993 vaddr_tainted
, te
->domain
, is_write
,
994 ArmFault::PermissionLL
+ te
->lookupLevel
,
995 isStage2
, ArmFault::LpaeTran
);
1003 TLB::checkPAN(ThreadContext
*tc
, uint8_t ap
, const RequestPtr
&req
, Mode mode
)
1005 // The PAN bit has no effect on:
1006 // 1) Instruction accesses.
1007 // 2) Data Cache instructions other than DC ZVA
1008 // 3) Address translation instructions, other than ATS1E1RP and
1009 // ATS1E1WP when ARMv8.2-ATS1E1 is implemented. (Unimplemented in
1011 // 4) Unprivileged instructions (Unimplemented in gem5)
1012 AA64MMFR1 mmfr1
= tc
->readMiscReg(MISCREG_ID_AA64MMFR1_EL1
);
1013 if (mmfr1
.pan
&& cpsr
.pan
&& (ap
& 0x1) && mode
!= Execute
&&
1014 (!req
->isCacheMaintenance() ||
1015 (req
->getFlags() & Request::CACHE_BLOCK_ZERO
))) {
1023 TLB::translateFs(const RequestPtr
&req
, ThreadContext
*tc
, Mode mode
,
1024 Translation
*translation
, bool &delay
, bool timing
,
1025 TLB::ArmTranslationType tranType
, bool functional
)
1027 // No such thing as a functional timing access
1028 assert(!(timing
&& functional
));
1030 updateMiscReg(tc
, tranType
);
1032 Addr vaddr_tainted
= req
->getVaddr();
1035 vaddr
= purifyTaggedAddr(vaddr_tainted
, tc
, aarch64EL
, ttbcr
);
1037 vaddr
= vaddr_tainted
;
1038 Request::Flags flags
= req
->getFlags();
1040 bool is_fetch
= (mode
== Execute
);
1041 bool is_write
= (mode
== Write
);
1042 bool long_desc_format
= aarch64
|| longDescFormatInUse(tc
);
1043 ArmFault::TranMethod tranMethod
= long_desc_format
? ArmFault::LpaeTran
1044 : ArmFault::VmsaTran
;
1048 DPRINTF(TLBVerbose
, "CPSR is priv:%d UserMode:%d secure:%d S1S2NsTran:%d\n",
1049 isPriv
, flags
& UserMode
, isSecure
, tranType
& S1S2NsTran
);
1051 DPRINTF(TLB
, "translateFs addr %#x, mode %d, st2 %d, scr %#x sctlr %#x "
1052 "flags %#lx tranType 0x%x\n", vaddr_tainted
, mode
, isStage2
,
1053 scr
, sctlr
, flags
, tranType
);
1055 if ((req
->isInstFetch() && (!sctlr
.i
)) ||
1056 ((!req
->isInstFetch()) && (!sctlr
.c
))){
1057 if (!req
->isCacheMaintenance()) {
1058 req
->setFlags(Request::UNCACHEABLE
);
1060 req
->setFlags(Request::STRICT_ORDER
);
1063 assert(flags
& MustBeOne
|| req
->isPrefetch());
1064 if (sctlr
.a
|| !(flags
& AllowUnaligned
)) {
1065 if (vaddr
& mask(flags
& AlignmentMask
)) {
1067 return std::make_shared
<DataAbort
>(
1069 TlbEntry::DomainType::NoAccess
, is_write
,
1070 ArmFault::AlignmentFault
, isStage2
,
1076 // If guest MMU is off or hcr.vm=0 go straight to stage2
1077 if ((isStage2
&& !hcr
.vm
) || (!isStage2
&& !sctlr
.m
)) {
1079 req
->setPaddr(vaddr
);
1080 // When the MMU is off the security attribute corresponds to the
1081 // security state of the processor
1083 req
->setFlags(Request::SECURE
);
1085 // @todo: double check this (ARM ARM issue C B3.2.1)
1086 if (long_desc_format
|| sctlr
.tre
== 0 || nmrr
.ir0
== 0 ||
1087 nmrr
.or0
== 0 || prrr
.tr0
!= 0x2) {
1088 if (!req
->isCacheMaintenance()) {
1089 req
->setFlags(Request::UNCACHEABLE
);
1091 req
->setFlags(Request::STRICT_ORDER
);
1094 // Set memory attributes
1096 temp_te
.ns
= !isSecure
;
1097 if (isStage2
|| hcr
.dc
== 0 || isSecure
||
1098 (isHyp
&& !(tranType
& S1CTran
))) {
1100 temp_te
.mtype
= is_fetch
? TlbEntry::MemoryType::Normal
1101 : TlbEntry::MemoryType::StronglyOrdered
;
1102 temp_te
.innerAttrs
= 0x0;
1103 temp_te
.outerAttrs
= 0x0;
1104 temp_te
.shareable
= true;
1105 temp_te
.outerShareable
= true;
1107 temp_te
.mtype
= TlbEntry::MemoryType::Normal
;
1108 temp_te
.innerAttrs
= 0x3;
1109 temp_te
.outerAttrs
= 0x3;
1110 temp_te
.shareable
= false;
1111 temp_te
.outerShareable
= false;
1113 temp_te
.setAttributes(long_desc_format
);
1114 DPRINTF(TLBVerbose
, "(No MMU) setting memory attributes: shareable: "
1115 "%d, innerAttrs: %d, outerAttrs: %d, isStage2: %d\n",
1116 temp_te
.shareable
, temp_te
.innerAttrs
, temp_te
.outerAttrs
,
1118 setAttr(temp_te
.attributes
);
1120 return testTranslation(req
, mode
, TlbEntry::DomainType::NoAccess
);
1123 DPRINTF(TLBVerbose
, "Translating %s=%#x context=%d\n",
1124 isStage2
? "IPA" : "VA", vaddr_tainted
, asid
);
1125 // Translation enabled
1127 TlbEntry
*te
= NULL
;
1129 Fault fault
= getResultTe(&te
, req
, tc
, mode
, translation
, timing
,
1130 functional
, &mergeTe
);
1131 // only proceed if we have a valid table entry
1132 if ((te
== NULL
) && (fault
== NoFault
)) delay
= true;
1134 // If we have the table entry transfer some of the attributes to the
1135 // request that triggered the translation
1137 // Set memory attributes
1139 "Setting memory attributes: shareable: %d, innerAttrs: %d, "
1140 "outerAttrs: %d, mtype: %d, isStage2: %d\n",
1141 te
->shareable
, te
->innerAttrs
, te
->outerAttrs
,
1142 static_cast<uint8_t>(te
->mtype
), isStage2
);
1143 setAttr(te
->attributes
);
1145 if (te
->nonCacheable
&& !req
->isCacheMaintenance())
1146 req
->setFlags(Request::UNCACHEABLE
);
1148 // Require requests to be ordered if the request goes to
1149 // strongly ordered or device memory (i.e., anything other
1150 // than normal memory requires strict order).
1151 if (te
->mtype
!= TlbEntry::MemoryType::Normal
)
1152 req
->setFlags(Request::STRICT_ORDER
);
1154 Addr pa
= te
->pAddr(vaddr
);
1157 if (isSecure
&& !te
->ns
) {
1158 req
->setFlags(Request::SECURE
);
1160 if ((!is_fetch
) && (vaddr
& mask(flags
& AlignmentMask
)) &&
1161 (te
->mtype
!= TlbEntry::MemoryType::Normal
)) {
1162 // Unaligned accesses to Device memory should always cause an
1163 // abort regardless of sctlr.a
1165 return std::make_shared
<DataAbort
>(
1167 TlbEntry::DomainType::NoAccess
, is_write
,
1168 ArmFault::AlignmentFault
, isStage2
,
1172 // Check for a trickbox generated address fault
1173 if (fault
== NoFault
)
1174 fault
= testTranslation(req
, mode
, te
->domain
);
1177 if (fault
== NoFault
) {
1178 // Don't try to finalize a physical address unless the
1179 // translation has completed (i.e., there is a table entry).
1180 return te
? finalizePhysical(req
, tc
, mode
) : NoFault
;
1187 TLB::translateAtomic(const RequestPtr
&req
, ThreadContext
*tc
, Mode mode
,
1188 TLB::ArmTranslationType tranType
)
1190 updateMiscReg(tc
, tranType
);
1192 if (directToStage2
) {
1194 return stage2Tlb
->translateAtomic(req
, tc
, mode
, tranType
);
1200 fault
= translateFs(req
, tc
, mode
, NULL
, delay
, false, tranType
);
1202 fault
= translateSe(req
, tc
, mode
, NULL
, delay
, false);
1208 TLB::translateFunctional(const RequestPtr
&req
, ThreadContext
*tc
, Mode mode
,
1209 TLB::ArmTranslationType tranType
)
1211 updateMiscReg(tc
, tranType
);
1213 if (directToStage2
) {
1215 return stage2Tlb
->translateFunctional(req
, tc
, mode
, tranType
);
1221 fault
= translateFs(req
, tc
, mode
, NULL
, delay
, false, tranType
, true);
1223 fault
= translateSe(req
, tc
, mode
, NULL
, delay
, false);
1229 TLB::translateTiming(const RequestPtr
&req
, ThreadContext
*tc
,
1230 Translation
*translation
, Mode mode
, TLB::ArmTranslationType tranType
)
1232 updateMiscReg(tc
, tranType
);
1234 if (directToStage2
) {
1236 stage2Tlb
->translateTiming(req
, tc
, translation
, mode
, tranType
);
1240 assert(translation
);
1242 translateComplete(req
, tc
, translation
, mode
, tranType
, isStage2
);
1246 TLB::translateComplete(const RequestPtr
&req
, ThreadContext
*tc
,
1247 Translation
*translation
, Mode mode
, TLB::ArmTranslationType tranType
,
1253 fault
= translateFs(req
, tc
, mode
, translation
, delay
, true, tranType
);
1255 fault
= translateSe(req
, tc
, mode
, translation
, delay
, true);
1256 DPRINTF(TLBVerbose
, "Translation returning delay=%d fault=%d\n", delay
, fault
!=
1258 // If we have a translation, and we're not in the middle of doing a stage
1259 // 2 translation tell the translation that we've either finished or its
1260 // going to take a while. By not doing this when we're in the middle of a
1261 // stage 2 translation we prevent marking the translation as delayed twice,
1262 // one when the translation starts and again when the stage 1 translation
1264 if (translation
&& (callFromS2
|| !stage2Req
|| req
->hasPaddr() || fault
!= NoFault
)) {
1266 translation
->finish(fault
, req
, tc
, mode
);
1268 translation
->markDelayed();
1274 TLB::getTableWalkerPort()
1276 return &stage2Mmu
->getDMAPort();
1280 TLB::updateMiscReg(ThreadContext
*tc
, ArmTranslationType tranType
)
1282 // check if the regs have changed, or the translation mode is different.
1283 // NOTE: the tran type doesn't affect stage 2 TLB's as they only handle
1284 // one type of translation anyway
1285 if (miscRegValid
&& miscRegContext
== tc
->contextId() &&
1286 ((tranType
== curTranType
) || isStage2
)) {
1290 DPRINTF(TLBVerbose
, "TLB variables changed!\n");
1291 cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
1293 // Dependencies: SCR/SCR_EL3, CPSR
1294 isSecure
= inSecureState(tc
) &&
1295 !(tranType
& HypMode
) && !(tranType
& S1S2NsTran
);
1297 aarch64EL
= tranTypeEL(cpsr
, tranType
);
1298 aarch64
= isStage2
?
1300 ELIs64(tc
, aarch64EL
== EL0
? EL1
: aarch64EL
);
1302 if (aarch64
) { // AArch64
1303 // determine EL we need to translate in
1304 switch (aarch64EL
) {
1308 sctlr
= tc
->readMiscReg(MISCREG_SCTLR_EL1
);
1309 ttbcr
= tc
->readMiscReg(MISCREG_TCR_EL1
);
1310 uint64_t ttbr_asid
= ttbcr
.a1
?
1311 tc
->readMiscReg(MISCREG_TTBR1_EL1
) :
1312 tc
->readMiscReg(MISCREG_TTBR0_EL1
);
1313 asid
= bits(ttbr_asid
,
1314 (haveLargeAsid64
&& ttbcr
.as
) ? 63 : 55, 48);
1318 sctlr
= tc
->readMiscReg(MISCREG_SCTLR_EL2
);
1319 ttbcr
= tc
->readMiscReg(MISCREG_TCR_EL2
);
1323 sctlr
= tc
->readMiscReg(MISCREG_SCTLR_EL3
);
1324 ttbcr
= tc
->readMiscReg(MISCREG_TCR_EL3
);
1328 hcr
= tc
->readMiscReg(MISCREG_HCR_EL2
);
1329 scr
= tc
->readMiscReg(MISCREG_SCR_EL3
);
1330 isPriv
= aarch64EL
!= EL0
;
1331 if (haveVirtualization
) {
1332 vmid
= bits(tc
->readMiscReg(MISCREG_VTTBR_EL2
), 55, 48);
1333 isHyp
= aarch64EL
== EL2
;
1334 isHyp
|= tranType
& HypMode
;
1335 isHyp
&= (tranType
& S1S2NsTran
) == 0;
1336 isHyp
&= (tranType
& S1CTran
) == 0;
1337 // Work out if we should skip the first stage of translation and go
1338 // directly to stage 2. This value is cached so we don't have to
1339 // compute it for every translation.
1340 stage2Req
= isStage2
||
1341 (hcr
.vm
&& !isHyp
&& !isSecure
&&
1342 !(tranType
& S1CTran
) && (aarch64EL
< EL2
) &&
1343 !(tranType
& S1E1Tran
)); // <--- FIX THIS HACK
1344 stage2DescReq
= isStage2
|| (hcr
.vm
&& !isHyp
&& !isSecure
&&
1346 directToStage2
= !isStage2
&& stage2Req
&& !sctlr
.m
;
1350 directToStage2
= false;
1352 stage2DescReq
= false;
1355 sctlr
= tc
->readMiscReg(snsBankedIndex(MISCREG_SCTLR
, tc
,
1357 ttbcr
= tc
->readMiscReg(snsBankedIndex(MISCREG_TTBCR
, tc
,
1359 scr
= tc
->readMiscReg(MISCREG_SCR
);
1360 isPriv
= cpsr
.mode
!= MODE_USER
;
1361 if (longDescFormatInUse(tc
)) {
1362 uint64_t ttbr_asid
= tc
->readMiscReg(
1363 snsBankedIndex(ttbcr
.a1
? MISCREG_TTBR1
:
1366 asid
= bits(ttbr_asid
, 55, 48);
1367 } else { // Short-descriptor translation table format in use
1368 CONTEXTIDR context_id
= tc
->readMiscReg(snsBankedIndex(
1369 MISCREG_CONTEXTIDR
, tc
,!isSecure
));
1370 asid
= context_id
.asid
;
1372 prrr
= tc
->readMiscReg(snsBankedIndex(MISCREG_PRRR
, tc
,
1374 nmrr
= tc
->readMiscReg(snsBankedIndex(MISCREG_NMRR
, tc
,
1376 dacr
= tc
->readMiscReg(snsBankedIndex(MISCREG_DACR
, tc
,
1378 hcr
= tc
->readMiscReg(MISCREG_HCR
);
1380 if (haveVirtualization
) {
1381 vmid
= bits(tc
->readMiscReg(MISCREG_VTTBR
), 55, 48);
1382 isHyp
= cpsr
.mode
== MODE_HYP
;
1383 isHyp
|= tranType
& HypMode
;
1384 isHyp
&= (tranType
& S1S2NsTran
) == 0;
1385 isHyp
&= (tranType
& S1CTran
) == 0;
1387 sctlr
= tc
->readMiscReg(MISCREG_HSCTLR
);
1389 // Work out if we should skip the first stage of translation and go
1390 // directly to stage 2. This value is cached so we don't have to
1391 // compute it for every translation.
1392 stage2Req
= hcr
.vm
&& !isStage2
&& !isHyp
&& !isSecure
&&
1393 !(tranType
& S1CTran
);
1394 stage2DescReq
= hcr
.vm
&& !isStage2
&& !isHyp
&& !isSecure
;
1395 directToStage2
= stage2Req
&& !sctlr
.m
;
1400 directToStage2
= false;
1401 stage2DescReq
= false;
1404 miscRegValid
= true;
1405 miscRegContext
= tc
->contextId();
1406 curTranType
= tranType
;
1410 TLB::tranTypeEL(CPSR cpsr
, ArmTranslationType type
)
1431 return currEL(cpsr
);
1434 panic("Unknown translation mode!\n");
1439 TLB::getTE(TlbEntry
**te
, const RequestPtr
&req
, ThreadContext
*tc
, Mode mode
,
1440 Translation
*translation
, bool timing
, bool functional
,
1441 bool is_secure
, TLB::ArmTranslationType tranType
)
1443 // In a 2-stage system, the IPA->PA translation can be started via this
1444 // call so make sure the miscRegs are correct.
1446 updateMiscReg(tc
, tranType
);
1448 bool is_fetch
= (mode
== Execute
);
1449 bool is_write
= (mode
== Write
);
1451 Addr vaddr_tainted
= req
->getVaddr();
1453 ExceptionLevel target_el
= aarch64
? aarch64EL
: EL1
;
1455 vaddr
= purifyTaggedAddr(vaddr_tainted
, tc
, target_el
, ttbcr
);
1457 vaddr
= vaddr_tainted
;
1459 *te
= lookup(vaddr
, asid
, vmid
, isHyp
, is_secure
, false, false, target_el
);
1461 if (req
->isPrefetch()) {
1462 // if the request is a prefetch don't attempt to fill the TLB or go
1463 // any further with the memory access (here we can safely use the
1464 // fault status for the short desc. format in all cases)
1466 return std::make_shared
<PrefetchAbort
>(
1467 vaddr_tainted
, ArmFault::PrefetchTLBMiss
, isStage2
);
1477 // start translation table walk, pass variables rather than
1478 // re-retreaving in table walker for speed
1479 DPRINTF(TLB
, "TLB Miss: Starting hardware table walker for %#x(%d:%d)\n",
1480 vaddr_tainted
, asid
, vmid
);
1482 fault
= tableWalker
->walk(req
, tc
, asid
, vmid
, isHyp
, mode
,
1483 translation
, timing
, functional
, is_secure
,
1484 tranType
, stage2DescReq
);
1485 // for timing mode, return and wait for table walk,
1486 if (timing
|| fault
!= NoFault
) {
1490 *te
= lookup(vaddr
, asid
, vmid
, isHyp
, is_secure
, false, false, target_el
);
1506 TLB::getResultTe(TlbEntry
**te
, const RequestPtr
&req
,
1507 ThreadContext
*tc
, Mode mode
,
1508 Translation
*translation
, bool timing
, bool functional
,
1514 // We are already in the stage 2 TLB. Grab the table entry for stage
1515 // 2 only. We are here because stage 1 translation is disabled.
1516 TlbEntry
*s2Te
= NULL
;
1517 // Get the stage 2 table entry
1518 fault
= getTE(&s2Te
, req
, tc
, mode
, translation
, timing
, functional
,
1519 isSecure
, curTranType
);
1520 // Check permissions of stage 2
1521 if ((s2Te
!= NULL
) && (fault
== NoFault
)) {
1523 fault
= checkPermissions64(s2Te
, req
, mode
, tc
);
1525 fault
= checkPermissions(s2Te
, req
, mode
);
1531 TlbEntry
*s1Te
= NULL
;
1533 Addr vaddr_tainted
= req
->getVaddr();
1535 // Get the stage 1 table entry
1536 fault
= getTE(&s1Te
, req
, tc
, mode
, translation
, timing
, functional
,
1537 isSecure
, curTranType
);
1538 // only proceed if we have a valid table entry
1539 if ((s1Te
!= NULL
) && (fault
== NoFault
)) {
1540 // Check stage 1 permissions before checking stage 2
1542 fault
= checkPermissions64(s1Te
, req
, mode
, tc
);
1544 fault
= checkPermissions(s1Te
, req
, mode
);
1545 if (stage2Req
& (fault
== NoFault
)) {
1546 Stage2LookUp
*s2Lookup
= new Stage2LookUp(this, stage2Tlb
, *s1Te
,
1547 req
, translation
, mode
, timing
, functional
, curTranType
);
1548 fault
= s2Lookup
->getTe(tc
, mergeTe
);
1549 if (s2Lookup
->isComplete()) {
1551 // We've finished with the lookup so delete it
1554 // The lookup hasn't completed, so we can't delete it now. We
1555 // get round this by asking the object to self delete when the
1556 // translation is complete.
1557 s2Lookup
->setSelfDelete();
1560 // This case deals with an S1 hit (or bypass), followed by
1561 // an S2 hit-but-perms issue
1563 DPRINTF(TLBVerbose
, "s2TLB: reqVa %#x, reqPa %#x, fault %p\n",
1564 vaddr_tainted
, req
->hasPaddr() ? req
->getPaddr() : ~0, fault
);
1565 if (fault
!= NoFault
) {
1566 ArmFault
*armFault
= reinterpret_cast<ArmFault
*>(fault
.get());
1567 armFault
->annotate(ArmFault::S1PTW
, false);
1568 armFault
->annotate(ArmFault::OVA
, vaddr_tainted
);
1578 TLB::setTestInterface(SimObject
*_ti
)
1583 TlbTestInterface
*ti(dynamic_cast<TlbTestInterface
*>(_ti
));
1584 fatal_if(!ti
, "%s is not a valid ARM TLB tester\n", _ti
->name());
1590 TLB::testTranslation(const RequestPtr
&req
, Mode mode
,
1591 TlbEntry::DomainType domain
)
1593 if (!test
|| !req
->hasSize() || req
->getSize() == 0 ||
1594 req
->isCacheMaintenance()) {
1597 return test
->translationCheck(req
, isPriv
, mode
, domain
);
1602 TLB::testWalk(Addr pa
, Addr size
, Addr va
, bool is_secure
, Mode mode
,
1603 TlbEntry::DomainType domain
, LookupLevel lookup_level
)
1608 return test
->walkCheck(pa
, size
, va
, is_secure
, isPriv
, mode
,
1609 domain
, lookup_level
);
1615 ArmTLBParams::create()
1617 return new ArmISA::TLB(this);