src/arch/arm/tlb.cc

   1 /*
   2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
   3  * Copyright (c) 2007 MIPS Technologies, Inc.
   4  * Copyright (c) 2007-2008 The Florida State University
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are
   9  * met: redistributions of source code must retain the above copyright
  10  * notice, this list of conditions and the following disclaimer;
  11  * redistributions in binary form must reproduce the above copyright
  12  * notice, this list of conditions and the following disclaimer in the
  13  * documentation and/or other materials provided with the distribution;
  14  * neither the name of the copyright holders nor the names of its
  15  * contributors may be used to endorse or promote products derived from
  16  * this software without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  24  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  25  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  26  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  28  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  * Authors: Nathan Binkert
  31  *          Steve Reinhardt
  32  *          Jaidev Patwardhan
  33  *          Stephen Hines
  34  */
  35
  36 #include <string>
  37 #include <vector>
  38
  39 #include "arch/arm/faults.hh"
  40 #include "arch/arm/pagetable.hh"
  41 #include "arch/arm/tlb.hh"
  42 #include "arch/arm/utility.hh"
  43 #include "base/inifile.hh"
  44 #include "base/str.hh"
  45 #include "base/trace.hh"
  46 #include "cpu/thread_context.hh"
  47 #include "mem/page_table.hh"
  48 #include "params/ArmTLB.hh"
  49 #include "sim/process.hh"
  50
  51
  52 using namespace std;
  53 using namespace ArmISA;
  54
  55 ///////////////////////////////////////////////////////////////////////
  56 //
  57 //  ARM TLB
  58 //
  59
  60 #define MODE2MASK(X)                    (1 << (X))
  61
  62 TLB::TLB(const Params *p)
  63     : BaseTLB(p), size(p->size), nlu(0)
  64 {
  65     table = new ArmISA::PTE[size];
  66     memset(table, 0, sizeof(ArmISA::PTE[size]));
  67     smallPages=0;
  68 }
  69
  70 TLB::~TLB()
  71 {
  72     if (table)
  73         delete [] table;
  74 }
  75
  76 // look up an entry in the TLB
  77 ArmISA::PTE *
  78 TLB::lookup(Addr vpn, uint8_t asn) const
  79 {
  80     // assume not found...
  81     ArmISA::PTE *retval = NULL;
  82     PageTable::const_iterator i = lookupTable.find(vpn);
  83     if (i != lookupTable.end()) {
  84         while (i->first == vpn) {
  85             int index = i->second;
  86             ArmISA::PTE *pte = &table[index];
  87
  88             /* 1KB TLB Lookup code - from ARM ARM Volume III - Rev. 2.50 */
  89             Addr Mask = pte->Mask;
  90             Addr InvMask = ~Mask;
  91             Addr VPN  = pte->VPN;
  92             //      warn("Valid: %d - %d\n",pte->V0,pte->V1);
  93             if(((vpn & InvMask) == (VPN & InvMask)) && (pte->G  || (asn == pte->asid)))
  94               { // We have a VPN + ASID Match
  95                 retval = pte;
  96                 break;
  97               }
  98             ++i;
  99         }
 100     }
 101
 102     DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
 103             retval ? "hit" : "miss", retval ? retval->PFN1 : 0);
 104     return retval;
 105 }
 106
 107 ArmISA::PTE* TLB::getEntry(unsigned Index) const
 108 {
 109     // Make sure that Index is valid
 110     assert(Index<size);
 111     return &table[Index];
 112 }
 113
 114 int TLB::probeEntry(Addr vpn,uint8_t asn) const
 115 {
 116     // assume not found...
 117     ArmISA::PTE *retval = NULL;
 118     int Ind=-1;
 119     PageTable::const_iterator i = lookupTable.find(vpn);
 120     if (i != lookupTable.end()) {
 121         while (i->first == vpn) {
 122             int index = i->second;
 123             ArmISA::PTE *pte = &table[index];
 124
 125             /* 1KB TLB Lookup code - from ARM ARM Volume III - Rev. 2.50 */
 126             Addr Mask = pte->Mask;
 127             Addr InvMask = ~Mask;
 128             Addr VPN  = pte->VPN;
 129             if(((vpn & InvMask) == (VPN & InvMask)) && (pte->G  || (asn == pte->asid)))
 130               { // We have a VPN + ASID Match
 131                 retval = pte;
 132                 Ind = index;
 133                 break;
 134               }
 135
 136             ++i;
 137         }
 138     }
 139     DPRINTF(Arm,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind);
 140     return Ind;
 141 }
 142 Fault inline
 143 TLB::checkCacheability(RequestPtr &req)
 144 {
 145   Addr VAddrUncacheable = 0xA0000000;
 146   // In ARM, cacheability is controlled by certain bits of the virtual address
 147   // or by the TLB entry
 148   if((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
 149     // mark request as uncacheable
 150     req->setFlags(Request::UNCACHEABLE);
 151   }
 152   return NoFault;
 153 }
 154 void TLB::insertAt(ArmISA::PTE &pte, unsigned Index, int _smallPages)
 155 {
 156   smallPages=_smallPages;
 157   if(Index > size){
 158     warn("Attempted to write at index (%d) beyond TLB size (%d)",Index,size);
 159   } else {
 160     // Update TLB
 161     DPRINTF(TLB,"TLB[%d]: %x %x %x %x\n",Index,pte.Mask<<11,((pte.VPN << 11) | pte.asid),((pte.PFN0 <<6) | (pte.C0 << 3) | (pte.D0 << 2) | (pte.V0 <<1) | pte.G),
 162             ((pte.PFN1 <<6) | (pte.C1 << 3) | (pte.D1 << 2) | (pte.V1 <<1) | pte.G));
 163     if(table[Index].V0 == true || table[Index].V1 == true){ // Previous entry is valid
 164       PageTable::iterator i = lookupTable.find(table[Index].VPN);
 165       lookupTable.erase(i);
 166     }
 167     table[Index]=pte;
 168     // Update fast lookup table
 169     lookupTable.insert(make_pair(table[Index].VPN, Index));
 170     //    int TestIndex=probeEntry(pte.VPN,pte.asid);
 171     //    warn("Inserted at: %d, Found at: %d (%x)\n",Index,TestIndex,pte.Mask);
 172   }
 173
 174 }
 175
 176 // insert a new TLB entry
 177 void
 178 TLB::insert(Addr addr, ArmISA::PTE &pte)
 179 {
 180   fatal("TLB Insert not yet implemented\n");
 181 }
 182
 183 void
 184 TLB::flushAll()
 185 {
 186     DPRINTF(TLB, "flushAll\n");
 187     memset(table, 0, sizeof(ArmISA::PTE[size]));
 188     lookupTable.clear();
 189     nlu = 0;
 190 }
 191
 192 void
 193 TLB::serialize(ostream &os)
 194 {
 195     SERIALIZE_SCALAR(size);
 196     SERIALIZE_SCALAR(nlu);
 197
 198     for (int i = 0; i < size; i++) {
 199         nameOut(os, csprintf("%s.PTE%d", name(), i));
 200         table[i].serialize(os);
 201     }
 202 }
 203
 204 void
 205 TLB::unserialize(Checkpoint *cp, const string &section)
 206 {
 207     UNSERIALIZE_SCALAR(size);
 208     UNSERIALIZE_SCALAR(nlu);
 209
 210     for (int i = 0; i < size; i++) {
 211         table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
 212         if (table[i].V0 || table[i].V1) {
 213             lookupTable.insert(make_pair(table[i].VPN, i));
 214         }
 215     }
 216 }
 217
 218 void
 219 TLB::regStats()
 220 {
 221     read_hits
 222         .name(name() + ".read_hits")
 223         .desc("DTB read hits")
 224         ;
 225
 226     read_misses
 227         .name(name() + ".read_misses")
 228         .desc("DTB read misses")
 229         ;
 230
 231
 232     read_accesses
 233         .name(name() + ".read_accesses")
 234         .desc("DTB read accesses")
 235         ;
 236
 237     write_hits
 238         .name(name() + ".write_hits")
 239         .desc("DTB write hits")
 240         ;
 241
 242     write_misses
 243         .name(name() + ".write_misses")
 244         .desc("DTB write misses")
 245         ;
 246
 247
 248     write_accesses
 249         .name(name() + ".write_accesses")
 250         .desc("DTB write accesses")
 251         ;
 252
 253     hits
 254         .name(name() + ".hits")
 255         .desc("DTB hits")
 256         ;
 257
 258     misses
 259         .name(name() + ".misses")
 260         .desc("DTB misses")
 261         ;
 262
 263     invalids
 264         .name(name() + ".invalids")
 265         .desc("DTB access violations")
 266         ;
 267
 268     accesses
 269         .name(name() + ".accesses")
 270         .desc("DTB accesses")
 271         ;
 272
 273     hits = read_hits + write_hits;
 274     misses = read_misses + write_misses;
 275     accesses = read_accesses + write_accesses;
 276 }
 277
 278 Fault
 279 TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
 280 {
 281 #if !FULL_SYSTEM
 282     Process * p = tc->getProcessPtr();
 283
 284     Fault fault = p->pTable->translate(req);
 285     if(fault != NoFault)
 286         return fault;
 287
 288     return NoFault;
 289 #else
 290     SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
 291     if (!sctlr.m) {
 292         req->setPaddr(req->getVaddr());
 293         return NoFault;
 294     }
 295     panic("MMU translation not implemented\n");
 296     return NoFault;
 297
 298
 299 #endif
 300 }
 301
 302 void
 303 TLB::translateTiming(RequestPtr req, ThreadContext *tc,
 304         Translation *translation, Mode mode)
 305 {
 306     assert(translation);
 307     translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
 308 }
 309
 310 ArmISA::PTE &
 311 TLB::index(bool advance)
 312 {
 313     ArmISA::PTE *pte = &table[nlu];
 314
 315     if (advance)
 316         nextnlu();
 317
 318     return *pte;
 319 }
 320
 321 ArmISA::TLB *
 322 ArmTLBParams::create()
 323 {
 324     return new ArmISA::TLB(this);
 325 }