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43 #ifndef __ARCH_ARM_TLB_HH__
44 #define __ARCH_ARM_TLB_HH__
47 #include "arch/arm/isa_traits.hh"
48 #include "arch/arm/pagetable.hh"
49 #include "arch/arm/utility.hh"
50 #include "arch/arm/vtophys.hh"
51 #include "arch/generic/tlb.hh"
52 #include "base/statistics.hh"
53 #include "mem/request.hh"
54 #include "params/ArmTLB.hh"
55 #include "sim/probe/pmu.hh"
65 class TLB : public BaseTLB
74 AlignDoubleWord = 0x3,
79 // Priv code operating as if it wasn't
81 // Because zero otherwise looks like a valid setting and may be used
82 // accidentally, this bit must be non-zero to show it was used on
87 enum ArmTranslationType {
91 // Secure code operating as if it wasn't (required by some Address
92 // Translate operations)
96 TlbEntry* table; // the Page Table
98 bool isStage2; // Indicates this TLB is part of the second stage MMU
99 bool stage2Req; // Indicates whether a stage 2 lookup is also required
100 uint64_t _attr; // Memory attributes for last accessed TLB entry
101 bool directToStage2; // Indicates whether all translation requests should
102 // be routed directly to the stage 2 TLB
104 TableWalker *tableWalker;
106 Stage2MMU *stage2Mmu;
109 mutable Stats::Scalar instHits;
110 mutable Stats::Scalar instMisses;
111 mutable Stats::Scalar readHits;
112 mutable Stats::Scalar readMisses;
113 mutable Stats::Scalar writeHits;
114 mutable Stats::Scalar writeMisses;
115 mutable Stats::Scalar inserts;
116 mutable Stats::Scalar flushTlb;
117 mutable Stats::Scalar flushTlbMva;
118 mutable Stats::Scalar flushTlbMvaAsid;
119 mutable Stats::Scalar flushTlbAsid;
120 mutable Stats::Scalar flushedEntries;
121 mutable Stats::Scalar alignFaults;
122 mutable Stats::Scalar prefetchFaults;
123 mutable Stats::Scalar domainFaults;
124 mutable Stats::Scalar permsFaults;
126 Stats::Formula readAccesses;
127 Stats::Formula writeAccesses;
128 Stats::Formula instAccesses;
130 Stats::Formula misses;
131 Stats::Formula accesses;
133 /** PMU probe for TLB refills */
134 ProbePoints::PMUUPtr ppRefills;
136 int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
139 TLB(const ArmTLBParams *p);
140 TLB(const Params *p, int _size, TableWalker *_walker);
142 /** Lookup an entry in the TLB
143 * @param vpn virtual address
144 * @param asn context id/address space id to use
145 * @param vmid The virtual machine ID used for stage 2 translation
146 * @param secure if the lookup is secure
147 * @param hyp if the lookup is done from hyp mode
148 * @param functional if the lookup should modify state
149 * @param ignore_asn if on lookup asn should be ignored
150 * @return pointer to TLB entry if it exists
152 TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp,
153 bool secure, bool functional,
154 bool ignore_asn, uint8_t target_el);
158 void takeOverFrom(BaseTLB *otlb) override;
160 /// setup all the back pointers
161 void init() override;
163 TableWalker *getTableWalker() { return tableWalker; }
165 void setMMU(Stage2MMU *m, MasterID master_id);
167 int getsize() const { return size; }
169 void insert(Addr vaddr, TlbEntry &pte);
171 Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode,
172 Translation *translation, bool timing, bool functional,
173 bool is_secure, ArmTranslationType tranType);
175 Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc,
176 Mode mode, Translation *translation, bool timing,
177 bool functional, TlbEntry *mergeTe);
179 Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode);
180 Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode,
184 /** Reset the entire TLB
185 * @param secure_lookup if the operation affects the secure world
187 void flushAllSecurity(bool secure_lookup, uint8_t target_el,
188 bool ignore_el = false);
190 /** Remove all entries in the non secure world, depending on whether they
191 * were allocated in hyp mode or not
192 * @param hyp if the opperation affects hyp mode
194 void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false);
197 /** Reset the entire TLB. Used for CPU switching to prevent stale
198 * translations after multiple switches
200 void flushAll() override
202 flushAllSecurity(false, 0, true);
203 flushAllSecurity(true, 0, true);
206 /** Remove any entries that match both a va and asn
207 * @param mva virtual address to flush
208 * @param asn contextid/asn to flush on match
209 * @param secure_lookup if the operation affects the secure world
211 void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup,
214 /** Remove any entries that match the asn
215 * @param asn contextid/asn to flush on match
216 * @param secure_lookup if the operation affects the secure world
218 void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el);
220 /** Remove all entries that match the va regardless of asn
221 * @param mva address to flush from cache
222 * @param secure_lookup if the operation affects the secure world
223 * @param hyp if the operation affects hyp mode
225 void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el);
227 Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain);
228 Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec,
229 bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level);
231 void printTlb() const;
233 void demapPage(Addr vaddr, uint64_t asn) override
235 // needed for x86 only
236 panic("demapPage() is not implemented.\n");
240 * Do a functional lookup on the TLB (for debugging)
241 * and don't modify any internal state
242 * @param tc thread context to get the context id from
243 * @param vaddr virtual address to translate
244 * @param pa returned physical address
245 * @return if the translation was successful
247 bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
250 * Do a functional lookup on the TLB (for checker cpu) that
251 * behaves like a normal lookup without modifying any page table state.
253 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode,
254 ArmTranslationType tranType = NormalTran);
256 /** Accessor functions for memory attributes for last accessed TLB entry
259 setAttr(uint64_t attr)
270 Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
271 Translation *translation, bool &delay,
272 bool timing, ArmTranslationType tranType, bool functional = false);
273 Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
274 Translation *translation, bool &delay, bool timing);
275 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode,
276 ArmTranslationType tranType = NormalTran);
277 Fault translateTiming(RequestPtr req, ThreadContext *tc,
278 Translation *translation, Mode mode,
279 ArmTranslationType tranType = NormalTran);
280 Fault translateComplete(RequestPtr req, ThreadContext *tc,
281 Translation *translation, Mode mode, ArmTranslationType tranType,
283 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
285 void drainResume() override;
288 void serialize(CheckpointOut &cp) const override;
289 void unserialize(CheckpointIn &cp) override;
291 void regStats() override;
293 void regProbePoints() override;
296 * Get the table walker master port. This is used for migrating
297 * port connections during a CPU takeOverFrom() call. For
298 * architectures that do not have a table walker, NULL is
299 * returned, hence the use of a pointer rather than a
300 * reference. For ARM this method will always return a valid port
303 * @return A pointer to the walker master port
305 BaseMasterPort* getMasterPort() override;
307 // Caching misc register values here.
308 // Writing to misc registers needs to invalidate them.
309 // translateFunctional/translateSe/translateFs checks if they are
310 // invalid and call updateMiscReg if necessary.
314 ExceptionLevel aarch64EL;
328 ContextID miscRegContext;
329 ArmTranslationType curTranType;
331 // Cached copies of system-level properties
333 bool haveVirtualization;
334 bool haveLargeAsid64;
336 void updateMiscReg(ThreadContext *tc,
337 ArmTranslationType tranType = NormalTran);
343 return dynamic_cast<const Params *>(_params);
345 inline void invalidateMiscReg() { miscRegValid = false; }
348 /** Remove any entries that match both a va and asn
349 * @param mva virtual address to flush
350 * @param asn contextid/asn to flush on match
351 * @param secure_lookup if the operation affects the secure world
352 * @param hyp if the operation affects hyp mode
353 * @param ignore_asn if the flush should ignore the asn
355 void _flushMva(Addr mva, uint64_t asn, bool secure_lookup,
356 bool hyp, bool ignore_asn, uint8_t target_el);
358 bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el);
361 } // namespace ArmISA
363 #endif // __ARCH_ARM_TLB_HH__