src/arch/arm/tlb.hh

   1 /*
   2  * Copyright (c) 2010-2013, 2016, 2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2001-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ali Saidi
  41  */
  42
  43 #ifndef __ARCH_ARM_TLB_HH__
  44 #define __ARCH_ARM_TLB_HH__
  45
  46
  47 #include "arch/arm/faults.hh"
  48 #include "arch/arm/isa_traits.hh"
  49 #include "arch/arm/pagetable.hh"
  50 #include "arch/arm/utility.hh"
  51 #include "arch/arm/vtophys.hh"
  52 #include "arch/generic/tlb.hh"
  53 #include "base/statistics.hh"
  54 #include "mem/request.hh"
  55 #include "params/ArmTLB.hh"
  56 #include "sim/probe/pmu.hh"
  57
  58 class ThreadContext;
  59
  60 namespace ArmISA {
  61
  62 class TableWalker;
  63 class Stage2LookUp;
  64 class Stage2MMU;
  65 class TLB;
  66
  67 class TlbTestInterface
  68 {
  69   public:
  70     TlbTestInterface() {}
  71     virtual ~TlbTestInterface() {}
  72
  73     /**
  74      * Check if a TLB translation should be forced to fail.
  75      *
  76      * @param req Request requiring a translation.
  77      * @param is_priv Access from a privileged mode (i.e., not EL0)
  78      * @param mode Access type
  79      * @param domain Domain type
  80      */
  81     virtual Fault translationCheck(const RequestPtr &req, bool is_priv,
  82                                    BaseTLB::Mode mode,
  83                                    TlbEntry::DomainType domain) = 0;
  84
  85     /**
  86      * Check if a page table walker access should be forced to fail.
  87      *
  88      * @param pa Physical address the walker is accessing
  89      * @param size Walker access size
  90      * @param va Virtual address that initiated the walk
  91      * @param is_secure Access from secure state
  92      * @param is_priv Access from a privileged mode (i.e., not EL0)
  93      * @param mode Access type
  94      * @param domain Domain type
  95      * @param lookup_level Page table walker level
  96      */
  97     virtual Fault walkCheck(Addr pa, Addr size, Addr va, bool is_secure,
  98                             Addr is_priv, BaseTLB::Mode mode,
  99                             TlbEntry::DomainType domain,
 100                             LookupLevel lookup_level) = 0;
 101 };
 102
 103 class TLB : public BaseTLB
 104 {
 105   public:
 106     enum ArmFlags {
 107         AlignmentMask = 0x7,
 108
 109         AlignByte = 0x0,
 110         AlignHalfWord = 0x1,
 111         AlignWord = 0x2,
 112         AlignDoubleWord = 0x3,
 113         AlignQuadWord = 0x4,
 114         AlignOctWord = 0x5,
 115
 116         AllowUnaligned = 0x8,
 117         // Priv code operating as if it wasn't
 118         UserMode = 0x10,
 119         // Because zero otherwise looks like a valid setting and may be used
 120         // accidentally, this bit must be non-zero to show it was used on
 121         // purpose.
 122         MustBeOne = 0x40
 123     };
 124
 125     enum ArmTranslationType {
 126         NormalTran = 0,
 127         S1CTran = 0x1,
 128         HypMode = 0x2,
 129         // Secure code operating as if it wasn't (required by some Address
 130         // Translate operations)
 131         S1S2NsTran = 0x4,
 132         // Address translation instructions (eg AT S1E0R_Xt) need to be handled
 133         // in special ways during translation because they could need to act
 134         // like a different EL than the current EL. The following flags are
 135         // for these instructions
 136         S1E0Tran = 0x8,
 137         S1E1Tran = 0x10,
 138         S1E2Tran = 0x20,
 139         S1E3Tran = 0x40,
 140         S12E0Tran = 0x80,
 141         S12E1Tran = 0x100
 142     };
 143
 144     /**
 145      * Determine the EL to use for the purpose of a translation given
 146      * a specific translation type. If the translation type doesn't
 147      * specify an EL, we use the current EL.
 148      */
 149     static ExceptionLevel tranTypeEL(CPSR cpsr, ArmTranslationType type);
 150
 151   protected:
 152     TlbEntry* table;     // the Page Table
 153     int size;            // TLB Size
 154     bool isStage2;       // Indicates this TLB is part of the second stage MMU
 155     bool stage2Req;      // Indicates whether a stage 2 lookup is also required
 156     // Indicates whether a stage 2 lookup of the table descriptors is required.
 157     // Certain address translation instructions will intercept the IPA but the
 158     // table descriptors still need to be translated by the stage2.
 159     bool stage2DescReq;
 160     uint64_t _attr;      // Memory attributes for last accessed TLB entry
 161     bool directToStage2; // Indicates whether all translation requests should
 162                          // be routed directly to the stage 2 TLB
 163
 164     TableWalker *tableWalker;
 165     TLB *stage2Tlb;
 166     Stage2MMU *stage2Mmu;
 167
 168     TlbTestInterface *test;
 169
 170     // Access Stats
 171     mutable Stats::Scalar instHits;
 172     mutable Stats::Scalar instMisses;
 173     mutable Stats::Scalar readHits;
 174     mutable Stats::Scalar readMisses;
 175     mutable Stats::Scalar writeHits;
 176     mutable Stats::Scalar writeMisses;
 177     mutable Stats::Scalar inserts;
 178     mutable Stats::Scalar flushTlb;
 179     mutable Stats::Scalar flushTlbMva;
 180     mutable Stats::Scalar flushTlbMvaAsid;
 181     mutable Stats::Scalar flushTlbAsid;
 182     mutable Stats::Scalar flushedEntries;
 183     mutable Stats::Scalar alignFaults;
 184     mutable Stats::Scalar prefetchFaults;
 185     mutable Stats::Scalar domainFaults;
 186     mutable Stats::Scalar permsFaults;
 187
 188     Stats::Formula readAccesses;
 189     Stats::Formula writeAccesses;
 190     Stats::Formula instAccesses;
 191     Stats::Formula hits;
 192     Stats::Formula misses;
 193     Stats::Formula accesses;
 194
 195     /** PMU probe for TLB refills */
 196     ProbePoints::PMUUPtr ppRefills;
 197
 198     int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
 199
 200   public:
 201     TLB(const ArmTLBParams *p);
 202     TLB(const Params *p, int _size, TableWalker *_walker);
 203
 204     /** Lookup an entry in the TLB
 205      * @param vpn virtual address
 206      * @param asn context id/address space id to use
 207      * @param vmid The virtual machine ID used for stage 2 translation
 208      * @param secure if the lookup is secure
 209      * @param hyp if the lookup is done from hyp mode
 210      * @param functional if the lookup should modify state
 211      * @param ignore_asn if on lookup asn should be ignored
 212      * @return pointer to TLB entry if it exists
 213      */
 214     TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp,
 215                      bool secure, bool functional,
 216                      bool ignore_asn, ExceptionLevel target_el);
 217
 218     virtual ~TLB();
 219
 220     void takeOverFrom(BaseTLB *otlb) override;
 221
 222     /// setup all the back pointers
 223     void init() override;
 224
 225     void setTestInterface(SimObject *ti);
 226
 227     TableWalker *getTableWalker() { return tableWalker; }
 228
 229     void setMMU(Stage2MMU *m, MasterID master_id);
 230
 231     int getsize() const { return size; }
 232
 233     void insert(Addr vaddr, TlbEntry &pte);
 234
 235     Fault getTE(TlbEntry **te, const RequestPtr &req,
 236                 ThreadContext *tc, Mode mode,
 237                 Translation *translation, bool timing, bool functional,
 238                 bool is_secure, ArmTranslationType tranType);
 239
 240     Fault getResultTe(TlbEntry **te, const RequestPtr &req,
 241                       ThreadContext *tc, Mode mode,
 242                       Translation *translation, bool timing,
 243                       bool functional, TlbEntry *mergeTe);
 244
 245     Fault checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode);
 246     Fault checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode,
 247                              ThreadContext *tc);
 248     bool checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req,
 249                   Mode mode);
 250
 251
 252     /** Reset the entire TLB
 253      * @param secure_lookup if the operation affects the secure world
 254      */
 255     void flushAllSecurity(bool secure_lookup, ExceptionLevel target_el,
 256                           bool ignore_el = false);
 257
 258     /** Remove all entries in the non secure world, depending on whether they
 259      *  were allocated in hyp mode or not
 260      */
 261     void flushAllNs(ExceptionLevel target_el, bool ignore_el = false);
 262
 263
 264     /** Reset the entire TLB. Used for CPU switching to prevent stale
 265      * translations after multiple switches
 266      */
 267     void flushAll() override
 268     {
 269         flushAllSecurity(false, EL0, true);
 270         flushAllSecurity(true, EL0, true);
 271     }
 272
 273     /** Remove any entries that match both a va and asn
 274      * @param mva virtual address to flush
 275      * @param asn contextid/asn to flush on match
 276      * @param secure_lookup if the operation affects the secure world
 277      */
 278     void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup,
 279                       ExceptionLevel target_el);
 280
 281     /** Remove any entries that match the asn
 282      * @param asn contextid/asn to flush on match
 283      * @param secure_lookup if the operation affects the secure world
 284      */
 285     void flushAsid(uint64_t asn, bool secure_lookup,
 286                    ExceptionLevel target_el);
 287
 288     /** Remove all entries that match the va regardless of asn
 289      * @param mva address to flush from cache
 290      * @param secure_lookup if the operation affects the secure world
 291      */
 292     void flushMva(Addr mva, bool secure_lookup, ExceptionLevel target_el);
 293
 294     /**
 295      * Invalidate all entries in the stage 2 TLB that match the given ipa
 296      * and the current VMID
 297      * @param ipa the address to invalidate
 298      * @param secure_lookup if the operation affects the secure world
 299      */
 300     void flushIpaVmid(Addr ipa, bool secure_lookup, ExceptionLevel target_el);
 301
 302     Fault trickBoxCheck(const RequestPtr &req, Mode mode,
 303                         TlbEntry::DomainType domain);
 304
 305     Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz,
 306                             bool is_exec, bool is_write,
 307                             TlbEntry::DomainType domain,
 308                             LookupLevel lookup_level);
 309
 310     void printTlb() const;
 311
 312     void demapPage(Addr vaddr, uint64_t asn) override
 313     {
 314         // needed for x86 only
 315         panic("demapPage() is not implemented.\n");
 316     }
 317
 318     /**
 319      * Do a functional lookup on the TLB (for debugging)
 320      * and don't modify any internal state
 321      * @param tc thread context to get the context id from
 322      * @param vaddr virtual address to translate
 323      * @param pa returned physical address
 324      * @return if the translation was successful
 325      */
 326     bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
 327
 328     /**
 329      * Do a functional lookup on the TLB (for checker cpu) that
 330      * behaves like a normal lookup without modifying any page table state.
 331      */
 332     Fault translateFunctional(const RequestPtr &req, ThreadContext *tc,
 333             Mode mode, ArmTranslationType tranType);
 334     Fault
 335     translateFunctional(const RequestPtr &req,
 336                         ThreadContext *tc, Mode mode) override
 337     {
 338         return translateFunctional(req, tc, mode, NormalTran);
 339     }
 340
 341     /** Accessor functions for memory attributes for last accessed TLB entry
 342      */
 343     void
 344     setAttr(uint64_t attr)
 345     {
 346         _attr = attr;
 347     }
 348
 349     uint64_t
 350     getAttr() const
 351     {
 352         return _attr;
 353     }
 354
 355     Fault translateMmuOff(ThreadContext *tc, const RequestPtr &req, Mode mode,
 356         TLB::ArmTranslationType tranType, Addr vaddr, bool long_desc_format);
 357     Fault translateMmuOn(ThreadContext *tc, const RequestPtr &req, Mode mode,
 358         Translation *translation, bool &delay, bool timing, bool functional,
 359         Addr vaddr, ArmFault::TranMethod tranMethod);
 360
 361     Fault translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode,
 362             Translation *translation, bool &delay,
 363             bool timing, ArmTranslationType tranType, bool functional = false);
 364     Fault translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode,
 365             Translation *translation, bool &delay, bool timing);
 366     Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode,
 367             ArmTranslationType tranType);
 368     Fault
 369     translateAtomic(const RequestPtr &req,
 370                     ThreadContext *tc, Mode mode) override
 371     {
 372         return translateAtomic(req, tc, mode, NormalTran);
 373     }
 374     void translateTiming(
 375             const RequestPtr &req, ThreadContext *tc,
 376             Translation *translation, Mode mode,
 377             ArmTranslationType tranType);
 378     void
 379     translateTiming(const RequestPtr &req, ThreadContext *tc,
 380                     Translation *translation, Mode mode) override
 381     {
 382         translateTiming(req, tc, translation, mode, NormalTran);
 383     }
 384     Fault translateComplete(const RequestPtr &req, ThreadContext *tc,
 385             Translation *translation, Mode mode, ArmTranslationType tranType,
 386             bool callFromS2);
 387     Fault finalizePhysical(
 388             const RequestPtr &req,
 389             ThreadContext *tc, Mode mode) const override;
 390
 391     void drainResume() override;
 392
 393     void regStats() override;
 394
 395     void regProbePoints() override;
 396
 397     /**
 398      * Get the table walker port. This is used for migrating
 399      * port connections during a CPU takeOverFrom() call. For
 400      * architectures that do not have a table walker, NULL is
 401      * returned, hence the use of a pointer rather than a
 402      * reference. For ARM this method will always return a valid port
 403      * pointer.
 404      *
 405      * @return A pointer to the walker master port
 406      */
 407     Port *getTableWalkerPort() override;
 408
 409     // Caching misc register values here.
 410     // Writing to misc registers needs to invalidate them.
 411     // translateFunctional/translateSe/translateFs checks if they are
 412     // invalid and call updateMiscReg if necessary.
 413 protected:
 414     CPSR cpsr;
 415     bool aarch64;
 416     ExceptionLevel aarch64EL;
 417     SCTLR sctlr;
 418     SCR scr;
 419     bool isPriv;
 420     bool isSecure;
 421     bool isHyp;
 422     TTBCR ttbcr;
 423     uint16_t asid;
 424     uint8_t vmid;
 425     PRRR prrr;
 426     NMRR nmrr;
 427     HCR hcr;
 428     uint32_t dacr;
 429     bool miscRegValid;
 430     ContextID miscRegContext;
 431     ArmTranslationType curTranType;
 432
 433     // Cached copies of system-level properties
 434     bool haveLPAE;
 435     bool haveVirtualization;
 436     bool haveLargeAsid64;
 437
 438     AddrRange m5opRange;
 439
 440     void updateMiscReg(ThreadContext *tc,
 441                        ArmTranslationType tranType = NormalTran);
 442
 443 public:
 444     const Params *
 445     params() const
 446     {
 447         return dynamic_cast<const Params *>(_params);
 448     }
 449     inline void invalidateMiscReg() { miscRegValid = false; }
 450
 451 private:
 452     /** Remove any entries that match both a va and asn
 453      * @param mva virtual address to flush
 454      * @param asn contextid/asn to flush on match
 455      * @param secure_lookup if the operation affects the secure world
 456      * @param ignore_asn if the flush should ignore the asn
 457      */
 458     void _flushMva(Addr mva, uint64_t asn, bool secure_lookup,
 459                    bool ignore_asn, ExceptionLevel target_el);
 460
 461   public: /* Testing */
 462     Fault testTranslation(const RequestPtr &req, Mode mode,
 463                           TlbEntry::DomainType domain);
 464     Fault testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode,
 465                    TlbEntry::DomainType domain,
 466                    LookupLevel lookup_level);
 467 };
 468
 469 template<typename T>
 470 TLB *
 471 getITBPtr(T *tc)
 472 {
 473     auto tlb = static_cast<TLB *>(tc->getITBPtr());
 474     assert(tlb);
 475     return tlb;
 476 }
 477
 478 template<typename T>
 479 TLB *
 480 getDTBPtr(T *tc)
 481 {
 482     auto tlb = static_cast<TLB *>(tc->getDTBPtr());
 483     assert(tlb);
 484     return tlb;
 485 }
 486
 487 } // namespace ArmISA
 488
 489 #endif // __ARCH_ARM_TLB_HH__