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43 #ifndef __ARCH_ARM_TLB_HH__
44 #define __ARCH_ARM_TLB_HH__
48 #include "arch/arm/isa_traits.hh"
49 #include "arch/arm/pagetable.hh"
50 #include "arch/arm/utility.hh"
51 #include "arch/arm/vtophys.hh"
52 #include "base/statistics.hh"
53 #include "mem/request.hh"
54 #include "params/ArmTLB.hh"
55 #include "sim/fault_fwd.hh"
64 class TLB : public BaseTLB
73 AlignDoubleWord = 0x7,
77 AllowUnaligned = 0x20,
78 // Priv code operating as if it wasn't
80 // Because zero otherwise looks like a valid setting and may be used
81 // accidentally, this bit must be non-zero to show it was used on
87 TlbEntry *table; // the Page Table
90 uint32_t _attr; // Memory attributes for last accessed TLB entry
92 TableWalker *tableWalker;
95 mutable Stats::Scalar instHits;
96 mutable Stats::Scalar instMisses;
97 mutable Stats::Scalar readHits;
98 mutable Stats::Scalar readMisses;
99 mutable Stats::Scalar writeHits;
100 mutable Stats::Scalar writeMisses;
101 mutable Stats::Scalar inserts;
102 mutable Stats::Scalar flushTlb;
103 mutable Stats::Scalar flushTlbMva;
104 mutable Stats::Scalar flushTlbMvaAsid;
105 mutable Stats::Scalar flushTlbAsid;
106 mutable Stats::Scalar flushedEntries;
107 mutable Stats::Scalar alignFaults;
108 mutable Stats::Scalar prefetchFaults;
109 mutable Stats::Scalar domainFaults;
110 mutable Stats::Scalar permsFaults;
112 Stats::Formula readAccesses;
113 Stats::Formula writeAccesses;
114 Stats::Formula instAccesses;
116 Stats::Formula misses;
117 Stats::Formula accesses;
119 int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
121 bool bootUncacheability;
124 typedef ArmTLBParams Params;
125 TLB(const Params *p);
127 /** Lookup an entry in the TLB
128 * @param vpn virtual address
129 * @param asn context id/address space id to use
130 * @param functional if the lookup should modify state
131 * @return pointer to TLB entrry if it exists
133 TlbEntry *lookup(Addr vpn, uint8_t asn, bool functional = false);
136 int getsize() const { return size; }
138 void insert(Addr vaddr, TlbEntry &pte);
140 /** Reset the entire TLB */
143 /** Remove any entries that match both a va and asn
144 * @param mva virtual address to flush
145 * @param asn contextid/asn to flush on match
147 void flushMvaAsid(Addr mva, uint64_t asn);
149 /** Remove any entries that match the asn
150 * @param asn contextid/asn to flush on match
152 void flushAsid(uint64_t asn);
154 /** Remove all entries that match the va regardless of asn
155 * @param mva address to flush from cache
157 void flushMva(Addr mva);
159 Fault trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp);
160 Fault walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
161 bool is_write, uint8_t domain, bool sNp);
165 void allCpusCaching() { bootUncacheability = true; }
166 void demapPage(Addr vaddr, uint64_t asn)
168 flushMvaAsid(vaddr, asn);
171 static bool validVirtualAddress(Addr vaddr);
174 * Do a functional lookup on the TLB (for debugging)
175 * and don't modify any internal state
176 * @param tc thread context to get the context id from
177 * @param vaddr virtual address to translate
178 * @param pa returned physical address
179 * @return if the translation was successful
181 bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
184 * Do a functional lookup on the TLB (for checker cpu) that
185 * behaves like a normal lookup without modifying any page table state.
187 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
189 /** Accessor functions for memory attributes for last accessed TLB entry
192 setAttr(uint32_t attr)
202 Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
203 Translation *translation, bool &delay,
204 bool timing, bool functional = false);
205 Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
206 Translation *translation, bool &delay, bool timing);
207 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
208 Fault translateTiming(RequestPtr req, ThreadContext *tc,
209 Translation *translation, Mode mode);
210 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
215 void serialize(std::ostream &os);
216 void unserialize(Checkpoint *cp, const std::string §ion);
221 * Get the table walker master port. This is used for migrating
222 * port connections during a CPU takeOverFrom() call. For
223 * architectures that do not have a table walker, NULL is
224 * returned, hence the use of a pointer rather than a
225 * reference. For ARM this method will always return a valid port
228 * @return A pointer to the walker master port
230 virtual BaseMasterPort* getMasterPort();
232 // Caching misc register values here.
233 // Writing to misc registers needs to invalidate them.
234 // translateFunctional/translateSe/translateFs checks if they are
235 // invalid and call updateMiscReg if necessary.
239 CONTEXTIDR contextId;
244 void updateMiscReg(ThreadContext *tc)
246 sctlr = tc->readMiscReg(MISCREG_SCTLR);
247 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
248 isPriv = cpsr.mode != MODE_USER;
249 contextId = tc->readMiscReg(MISCREG_CONTEXTIDR);
250 prrr = tc->readMiscReg(MISCREG_PRRR);
251 nmrr = tc->readMiscReg(MISCREG_NMRR);
252 dacr = tc->readMiscReg(MISCREG_DACR);
259 return dynamic_cast<const Params *>(_params);
261 inline void invalidateMiscReg() { miscRegValid = false; }
264 } // namespace ArmISA
266 #endif // __ARCH_ARM_TLB_HH__