src/arch/arm/tlb.hh

   1 /*
   2  * Copyright (c) 2010-2013, 2016, 2019-2020 ARM Limited
   3  * All rights reserved
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   5  * The license below extends only to copyright in the software and shall
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   8  * to a hardware implementation of the functionality of the software
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  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2001-2005 The Regents of The University of Michigan
  15  * All rights reserved.
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  40
  41 #ifndef __ARCH_ARM_TLB_HH__
  42 #define __ARCH_ARM_TLB_HH__
  43
  44
  45 #include "arch/arm/faults.hh"
  46 #include "arch/arm/isa_traits.hh"
  47 #include "arch/arm/pagetable.hh"
  48 #include "arch/arm/utility.hh"
  49 #include "arch/generic/tlb.hh"
  50 #include "base/statistics.hh"
  51 #include "mem/request.hh"
  52 #include "params/ArmTLB.hh"
  53 #include "sim/probe/pmu.hh"
  54
  55 class ThreadContext;
  56
  57 namespace ArmISA {
  58
  59 class TableWalker;
  60 class Stage2LookUp;
  61 class Stage2MMU;
  62 class TLB;
  63
  64 class TLBIALL;
  65 class TLBIALLEL;
  66 class TLBIVMALL;
  67 class TLBIALLN;
  68 class TLBIMVA;
  69 class TLBIASID;
  70 class TLBIMVAA;
  71 class TLBIIPA;
  72
  73 class TlbTestInterface
  74 {
  75   public:
  76     TlbTestInterface() {}
  77     virtual ~TlbTestInterface() {}
  78
  79     /**
  80      * Check if a TLB translation should be forced to fail.
  81      *
  82      * @param req Request requiring a translation.
  83      * @param is_priv Access from a privileged mode (i.e., not EL0)
  84      * @param mode Access type
  85      * @param domain Domain type
  86      */
  87     virtual Fault translationCheck(const RequestPtr &req, bool is_priv,
  88                                    BaseTLB::Mode mode,
  89                                    TlbEntry::DomainType domain) = 0;
  90
  91     /**
  92      * Check if a page table walker access should be forced to fail.
  93      *
  94      * @param pa Physical address the walker is accessing
  95      * @param size Walker access size
  96      * @param va Virtual address that initiated the walk
  97      * @param is_secure Access from secure state
  98      * @param is_priv Access from a privileged mode (i.e., not EL0)
  99      * @param mode Access type
 100      * @param domain Domain type
 101      * @param lookup_level Page table walker level
 102      */
 103     virtual Fault walkCheck(Addr pa, Addr size, Addr va, bool is_secure,
 104                             Addr is_priv, BaseTLB::Mode mode,
 105                             TlbEntry::DomainType domain,
 106                             LookupLevel lookup_level) = 0;
 107 };
 108
 109 class TLB : public BaseTLB
 110 {
 111   public:
 112     enum ArmFlags {
 113         AlignmentMask = 0x7,
 114
 115         AlignByte = 0x0,
 116         AlignHalfWord = 0x1,
 117         AlignWord = 0x2,
 118         AlignDoubleWord = 0x3,
 119         AlignQuadWord = 0x4,
 120         AlignOctWord = 0x5,
 121
 122         AllowUnaligned = 0x8,
 123         // Priv code operating as if it wasn't
 124         UserMode = 0x10
 125     };
 126
 127     enum ArmTranslationType {
 128         NormalTran = 0,
 129         S1CTran = 0x1,
 130         HypMode = 0x2,
 131         // Secure code operating as if it wasn't (required by some Address
 132         // Translate operations)
 133         S1S2NsTran = 0x4,
 134         // Address translation instructions (eg AT S1E0R_Xt) need to be handled
 135         // in special ways during translation because they could need to act
 136         // like a different EL than the current EL. The following flags are
 137         // for these instructions
 138         S1E0Tran = 0x8,
 139         S1E1Tran = 0x10,
 140         S1E2Tran = 0x20,
 141         S1E3Tran = 0x40,
 142         S12E0Tran = 0x80,
 143         S12E1Tran = 0x100
 144     };
 145
 146     /**
 147      * Determine the EL to use for the purpose of a translation given
 148      * a specific translation type. If the translation type doesn't
 149      * specify an EL, we use the current EL.
 150      */
 151     static ExceptionLevel tranTypeEL(CPSR cpsr, ArmTranslationType type);
 152
 153   protected:
 154     TlbEntry* table;     // the Page Table
 155     int size;            // TLB Size
 156     bool isStage2;       // Indicates this TLB is part of the second stage MMU
 157     bool stage2Req;      // Indicates whether a stage 2 lookup is also required
 158     // Indicates whether a stage 2 lookup of the table descriptors is required.
 159     // Certain address translation instructions will intercept the IPA but the
 160     // table descriptors still need to be translated by the stage2.
 161     bool stage2DescReq;
 162     uint64_t _attr;      // Memory attributes for last accessed TLB entry
 163     bool directToStage2; // Indicates whether all translation requests should
 164                          // be routed directly to the stage 2 TLB
 165
 166     TableWalker *tableWalker;
 167     TLB *stage2Tlb;
 168     Stage2MMU *stage2Mmu;
 169
 170     TlbTestInterface *test;
 171
 172     struct TlbStats : public Stats::Group
 173     {
 174         TlbStats(Stats::Group *parent);
 175         // Access Stats
 176         mutable Stats::Scalar instHits;
 177         mutable Stats::Scalar instMisses;
 178         mutable Stats::Scalar readHits;
 179         mutable Stats::Scalar readMisses;
 180         mutable Stats::Scalar writeHits;
 181         mutable Stats::Scalar writeMisses;
 182         mutable Stats::Scalar inserts;
 183         mutable Stats::Scalar flushTlb;
 184         mutable Stats::Scalar flushTlbMva;
 185         mutable Stats::Scalar flushTlbMvaAsid;
 186         mutable Stats::Scalar flushTlbAsid;
 187         mutable Stats::Scalar flushedEntries;
 188         mutable Stats::Scalar alignFaults;
 189         mutable Stats::Scalar prefetchFaults;
 190         mutable Stats::Scalar domainFaults;
 191         mutable Stats::Scalar permsFaults;
 192
 193         Stats::Formula readAccesses;
 194         Stats::Formula writeAccesses;
 195         Stats::Formula instAccesses;
 196         Stats::Formula hits;
 197         Stats::Formula misses;
 198         Stats::Formula accesses;
 199     } stats;
 200
 201     /** PMU probe for TLB refills */
 202     ProbePoints::PMUUPtr ppRefills;
 203
 204     int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
 205
 206   public:
 207     TLB(const ArmTLBParams &p);
 208     TLB(const Params &p, int _size, TableWalker *_walker);
 209
 210     /** Lookup an entry in the TLB
 211      * @param vpn virtual address
 212      * @param asn context id/address space id to use
 213      * @param vmid The virtual machine ID used for stage 2 translation
 214      * @param secure if the lookup is secure
 215      * @param hyp if the lookup is done from hyp mode
 216      * @param functional if the lookup should modify state
 217      * @param ignore_asn if on lookup asn should be ignored
 218      * @return pointer to TLB entry if it exists
 219      */
 220     TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp,
 221                      bool secure, bool functional,
 222                      bool ignore_asn, ExceptionLevel target_el,
 223                      bool in_host);
 224
 225     virtual ~TLB();
 226
 227     void takeOverFrom(BaseTLB *otlb) override;
 228
 229     /// setup all the back pointers
 230     void init() override;
 231
 232     void setTestInterface(SimObject *ti);
 233
 234     TableWalker *getTableWalker() { return tableWalker; }
 235
 236     void setMMU(Stage2MMU *m, RequestorID requestor_id);
 237
 238     int getsize() const { return size; }
 239
 240     void insert(Addr vaddr, TlbEntry &pte);
 241
 242     Fault getTE(TlbEntry **te, const RequestPtr &req,
 243                 ThreadContext *tc, Mode mode,
 244                 Translation *translation, bool timing, bool functional,
 245                 bool is_secure, ArmTranslationType tranType);
 246
 247     Fault getResultTe(TlbEntry **te, const RequestPtr &req,
 248                       ThreadContext *tc, Mode mode,
 249                       Translation *translation, bool timing,
 250                       bool functional, TlbEntry *mergeTe);
 251
 252     Fault checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode);
 253     Fault checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode,
 254                              ThreadContext *tc);
 255     bool checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req,
 256                   Mode mode);
 257
 258     /** Reset the entire TLB. Used for CPU switching to prevent stale
 259      * translations after multiple switches
 260      */
 261     void flushAll() override;
 262
 263
 264     /** Reset the entire TLB
 265      */
 266     void flush(const TLBIALL &tlbi_op);
 267
 268     /** Implementaton of AArch64 TLBI ALLE1(IS), ALLE2(IS), ALLE3(IS)
 269      * instructions
 270      */
 271     void flush(const TLBIALLEL &tlbi_op);
 272
 273     /** Implementaton of AArch64 TLBI VMALLE1(IS)/VMALLS112E1(IS)
 274      * instructions
 275      */
 276     void flush(const TLBIVMALL &tlbi_op);
 277
 278     /** Remove all entries in the non secure world, depending on whether they
 279      *  were allocated in hyp mode or not
 280      */
 281     void flush(const TLBIALLN &tlbi_op);
 282
 283     /** Remove any entries that match both a va and asn
 284      */
 285     void flush(const TLBIMVA &tlbi_op);
 286
 287     /** Remove any entries that match the asn
 288      */
 289     void flush(const TLBIASID &tlbi_op);
 290
 291     /** Remove all entries that match the va regardless of asn
 292      */
 293     void flush(const TLBIMVAA &tlbi_op);
 294
 295     /**
 296      * Invalidate all entries in the stage 2 TLB that match the given ipa
 297      * and the current VMID
 298      */
 299     void flush(const TLBIIPA &tlbi_op);
 300
 301     Fault trickBoxCheck(const RequestPtr &req, Mode mode,
 302                         TlbEntry::DomainType domain);
 303
 304     Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz,
 305                             bool is_exec, bool is_write,
 306                             TlbEntry::DomainType domain,
 307                             LookupLevel lookup_level);
 308
 309     void printTlb() const;
 310
 311     void demapPage(Addr vaddr, uint64_t asn) override
 312     {
 313         // needed for x86 only
 314         panic("demapPage() is not implemented.\n");
 315     }
 316
 317     /**
 318      * Do a functional lookup on the TLB (for debugging)
 319      * and don't modify any internal state
 320      * @param tc thread context to get the context id from
 321      * @param vaddr virtual address to translate
 322      * @param pa returned physical address
 323      * @return if the translation was successful
 324      */
 325     bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
 326
 327     /**
 328      * Do a functional lookup on the TLB (for checker cpu) that
 329      * behaves like a normal lookup without modifying any page table state.
 330      */
 331     Fault translateFunctional(const RequestPtr &req, ThreadContext *tc,
 332             Mode mode, ArmTranslationType tranType);
 333     Fault
 334     translateFunctional(const RequestPtr &req,
 335                         ThreadContext *tc, Mode mode) override
 336     {
 337         return translateFunctional(req, tc, mode, NormalTran);
 338     }
 339
 340     /** Accessor functions for memory attributes for last accessed TLB entry
 341      */
 342     void
 343     setAttr(uint64_t attr)
 344     {
 345         _attr = attr;
 346     }
 347
 348     uint64_t
 349     getAttr() const
 350     {
 351         return _attr;
 352     }
 353
 354     Fault translateMmuOff(ThreadContext *tc, const RequestPtr &req, Mode mode,
 355         TLB::ArmTranslationType tranType, Addr vaddr, bool long_desc_format);
 356     Fault translateMmuOn(ThreadContext *tc, const RequestPtr &req, Mode mode,
 357         Translation *translation, bool &delay, bool timing, bool functional,
 358         Addr vaddr, ArmFault::TranMethod tranMethod);
 359
 360     Fault translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode,
 361             Translation *translation, bool &delay,
 362             bool timing, ArmTranslationType tranType, bool functional = false);
 363     Fault translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode,
 364             Translation *translation, bool &delay, bool timing);
 365     Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode,
 366             ArmTranslationType tranType);
 367     Fault
 368     translateAtomic(const RequestPtr &req,
 369                     ThreadContext *tc, Mode mode) override
 370     {
 371         return translateAtomic(req, tc, mode, NormalTran);
 372     }
 373     void translateTiming(
 374             const RequestPtr &req, ThreadContext *tc,
 375             Translation *translation, Mode mode,
 376             ArmTranslationType tranType);
 377     void
 378     translateTiming(const RequestPtr &req, ThreadContext *tc,
 379                     Translation *translation, Mode mode) override
 380     {
 381         translateTiming(req, tc, translation, mode, NormalTran);
 382     }
 383     Fault translateComplete(const RequestPtr &req, ThreadContext *tc,
 384             Translation *translation, Mode mode, ArmTranslationType tranType,
 385             bool callFromS2);
 386     Fault finalizePhysical(
 387             const RequestPtr &req,
 388             ThreadContext *tc, Mode mode) const override;
 389
 390     void drainResume() override;
 391
 392     void regProbePoints() override;
 393
 394     /**
 395      * Get the table walker port. This is used for migrating
 396      * port connections during a CPU takeOverFrom() call. For
 397      * architectures that do not have a table walker, NULL is
 398      * returned, hence the use of a pointer rather than a
 399      * reference. For ARM this method will always return a valid port
 400      * pointer.
 401      *
 402      * @return A pointer to the walker request port
 403      */
 404     Port *getTableWalkerPort() override;
 405
 406     // Caching misc register values here.
 407     // Writing to misc registers needs to invalidate them.
 408     // translateFunctional/translateSe/translateFs checks if they are
 409     // invalid and call updateMiscReg if necessary.
 410 protected:
 411     CPSR cpsr;
 412     bool aarch64;
 413     ExceptionLevel aarch64EL;
 414     SCTLR sctlr;
 415     SCR scr;
 416     bool isPriv;
 417     bool isSecure;
 418     bool isHyp;
 419     TTBCR ttbcr;
 420     uint16_t asid;
 421     uint8_t vmid;
 422     PRRR prrr;
 423     NMRR nmrr;
 424     HCR hcr;
 425     uint32_t dacr;
 426     bool miscRegValid;
 427     ContextID miscRegContext;
 428     ArmTranslationType curTranType;
 429
 430     // Cached copies of system-level properties
 431     bool haveLPAE;
 432     bool haveVirtualization;
 433     bool haveLargeAsid64;
 434     uint8_t physAddrRange;
 435
 436     AddrRange m5opRange;
 437
 438     void updateMiscReg(ThreadContext *tc,
 439                        ArmTranslationType tranType = NormalTran);
 440
 441 public:
 442     const Params &
 443     params() const
 444     {
 445         return dynamic_cast<const Params &>(_params);
 446     }
 447     void invalidateMiscReg() { miscRegValid = false; }
 448
 449 private:
 450     /** Remove any entries that match both a va and asn
 451      * @param mva virtual address to flush
 452      * @param asn contextid/asn to flush on match
 453      * @param secure_lookup if the operation affects the secure world
 454      * @param ignore_asn if the flush should ignore the asn
 455      * @param in_host if hcr.e2h == 1 and hcr.tge == 1 for VHE.
 456      */
 457     void _flushMva(Addr mva, uint64_t asn, bool secure_lookup,
 458                    bool ignore_asn, ExceptionLevel target_el,
 459                    bool in_host);
 460
 461   public: /* Testing */
 462     Fault testTranslation(const RequestPtr &req, Mode mode,
 463                           TlbEntry::DomainType domain);
 464     Fault testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode,
 465                    TlbEntry::DomainType domain,
 466                    LookupLevel lookup_level);
 467 };
 468
 469 } // namespace ArmISA
 470
 471 #endif // __ARCH_ARM_TLB_HH__