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43 #ifndef __ARCH_ARM_TLB_HH__
44 #define __ARCH_ARM_TLB_HH__
48 #include "arch/arm/isa_traits.hh"
49 #include "arch/arm/utility.hh"
50 #include "arch/arm/vtophys.hh"
51 #include "arch/arm/pagetable.hh"
52 #include "base/statistics.hh"
53 #include "mem/request.hh"
54 #include "params/ArmTLB.hh"
55 #include "sim/faults.hh"
62 class TLB : public BaseTLB
71 AlignDoubleWord = 0x7,
74 // Because zero otherwise looks like a valid setting and may be used
75 // accidentally, this bit must be non-zero to show it was used on
80 typedef std::multimap<Addr, int> PageTable;
81 PageTable lookupTable; // Quick lookup into page table
83 ArmISA::PTE *table; // the Page Table
85 int nlu; // not last used entry (for replacement)
87 void nextnlu() { if (++nlu >= size) nlu = 0; }
88 ArmISA::PTE *lookup(Addr vpn, uint8_t asn) const;
91 mutable Stats::Scalar read_hits;
92 mutable Stats::Scalar read_misses;
93 mutable Stats::Scalar read_acv;
94 mutable Stats::Scalar read_accesses;
95 mutable Stats::Scalar write_hits;
96 mutable Stats::Scalar write_misses;
97 mutable Stats::Scalar write_acv;
98 mutable Stats::Scalar write_accesses;
100 Stats::Formula misses;
101 Stats::Formula invalids;
102 Stats::Formula accesses;
105 typedef ArmTLBParams Params;
106 TLB(const Params *p);
109 int getsize() const { return size; }
111 void insert(Addr vaddr, ArmISA::PTE &pte);
113 void demapPage(Addr vaddr, uint64_t asn)
115 panic("demapPage unimplemented.\n");
118 static bool validVirtualAddress(Addr vaddr);
120 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
121 void translateTiming(RequestPtr req, ThreadContext *tc,
122 Translation *translation, Mode mode);
125 void serialize(std::ostream &os);
126 void unserialize(Checkpoint *cp, const std::string §ion);
131 /* namespace ArmISA */ }
133 #endif // __ARCH_ARM_TLB_HH__