src/arch/arm/tlb.hh

   1 /*
   2  * Copyright (c) 2010 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2001-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ali Saidi
  41  */
  42
  43 #ifndef __ARCH_ARM_TLB_HH__
  44 #define __ARCH_ARM_TLB_HH__
  45
  46 #include <map>
  47
  48 #include "arch/arm/isa_traits.hh"
  49 #include "arch/arm/utility.hh"
  50 #include "arch/arm/vtophys.hh"
  51 #include "arch/arm/pagetable.hh"
  52 #include "base/statistics.hh"
  53 #include "mem/request.hh"
  54 #include "params/ArmTLB.hh"
  55 #include "sim/fault_fwd.hh"
  56 #include "sim/tlb.hh"
  57
  58 class ThreadContext;
  59
  60 namespace ArmISA {
  61
  62 class TableWalker;
  63
  64 class TLB : public BaseTLB
  65 {
  66   public:
  67     enum ArmFlags {
  68         AlignmentMask = 0x1f,
  69
  70         AlignByte = 0x0,
  71         AlignHalfWord = 0x1,
  72         AlignWord = 0x3,
  73         AlignDoubleWord = 0x7,
  74         AlignQuadWord = 0xf,
  75         AlignOctWord = 0x1f,
  76
  77         AllowUnaligned = 0x20,
  78         // Priv code operating as if it wasn't
  79         UserMode = 0x40,
  80         // Because zero otherwise looks like a valid setting and may be used
  81         // accidentally, this bit must be non-zero to show it was used on
  82         // purpose.
  83         MustBeOne = 0x80
  84     };
  85   protected:
  86
  87     TlbEntry *table;    // the Page Table
  88     int size;           // TLB Size
  89
  90     uint32_t _attr;     // Memory attributes for last accessed TLB entry
  91
  92 #if FULL_SYSTEM
  93     TableWalker *tableWalker;
  94 #endif
  95
  96     /** Lookup an entry in the TLB
  97      * @param vpn virtual address
  98      * @param asn context id/address space id to use
  99      * @param functional if the lookup should modify state
 100      * @return pointer to TLB entrry if it exists
 101      */
 102     TlbEntry *lookup(Addr vpn, uint8_t asn, bool functional = false);
 103
 104     // Access Stats
 105     mutable Stats::Scalar instHits;
 106     mutable Stats::Scalar instMisses;
 107     mutable Stats::Scalar readHits;
 108     mutable Stats::Scalar readMisses;
 109     mutable Stats::Scalar writeHits;
 110     mutable Stats::Scalar writeMisses;
 111     mutable Stats::Scalar inserts;
 112     mutable Stats::Scalar flushTlb;
 113     mutable Stats::Scalar flushTlbMva;
 114     mutable Stats::Scalar flushTlbMvaAsid;
 115     mutable Stats::Scalar flushTlbAsid;
 116     mutable Stats::Scalar flushedEntries;
 117     mutable Stats::Scalar alignFaults;
 118     mutable Stats::Scalar prefetchFaults;
 119     mutable Stats::Scalar domainFaults;
 120     mutable Stats::Scalar permsFaults;
 121
 122     Stats::Formula readAccesses;
 123     Stats::Formula writeAccesses;
 124     Stats::Formula instAccesses;
 125     Stats::Formula hits;
 126     Stats::Formula misses;
 127     Stats::Formula accesses;
 128
 129     int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
 130
 131   public:
 132     typedef ArmTLBParams Params;
 133     TLB(const Params *p);
 134
 135     virtual ~TLB();
 136     int getsize() const { return size; }
 137
 138     void insert(Addr vaddr, TlbEntry &pte);
 139
 140     /** Reset the entire TLB */
 141     void flushAll();
 142
 143     /** Remove any entries that match both a va and asn
 144      * @param mva virtual address to flush
 145      * @param asn contextid/asn to flush on match
 146      */
 147     void flushMvaAsid(Addr mva, uint64_t asn);
 148
 149     /** Remove any entries that match the asn
 150      * @param asn contextid/asn to flush on match
 151      */
 152     void flushAsid(uint64_t asn);
 153
 154     /** Remove all entries that match the va regardless of asn
 155      * @param mva address to flush from cache
 156      */
 157     void flushMva(Addr mva);
 158
 159     Fault trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp);
 160     Fault walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
 161             bool is_write, uint8_t domain, bool sNp);
 162
 163     void printTlb();
 164
 165     void demapPage(Addr vaddr, uint64_t asn)
 166     {
 167         flushMvaAsid(vaddr, asn);
 168     }
 169
 170     static bool validVirtualAddress(Addr vaddr);
 171
 172     /**
 173      * Do a functional lookup on the TLB (for debugging)
 174      * and don't modify any internal state
 175      * @param tc thread context to get the context id from
 176      * @param vaddr virtual address to translate
 177      * @param pa returned physical address
 178      * @return if the translation was successful
 179      */
 180     bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
 181
 182     /** Accessor functions for memory attributes for last accessed TLB entry
 183      */
 184     void
 185     setAttr(uint32_t attr)
 186     {
 187         _attr = attr;
 188     }
 189     uint32_t
 190     getAttr() const
 191     {
 192         return _attr;
 193     }
 194
 195 #if FULL_SYSTEM
 196     Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
 197             Translation *translation, bool &delay, bool timing);
 198 #else
 199     Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
 200             Translation *translation, bool &delay, bool timing);
 201 #endif
 202     Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
 203     Fault translateTiming(RequestPtr req, ThreadContext *tc,
 204             Translation *translation, Mode mode);
 205
 206     // Checkpointing
 207     void serialize(std::ostream &os);
 208     void unserialize(Checkpoint *cp, const std::string &section);
 209
 210     void regStats();
 211
 212     // Get the port from the table walker and return it
 213     virtual Port *getPort();
 214
 215     // Caching misc register values here.
 216     // Writing to misc registers needs to invalidate them.
 217     // translateFunctional/translateSe/translateFs checks if they are
 218     // invalid and call updateMiscReg if necessary.
 219 protected:
 220     SCTLR sctlr;
 221     bool isPriv;
 222     uint32_t contextId;
 223     PRRR prrr;
 224     NMRR nmrr;
 225     uint32_t dacr;
 226     bool miscRegValid;
 227     void updateMiscReg(ThreadContext *tc)
 228     {
 229         sctlr = tc->readMiscReg(MISCREG_SCTLR);
 230         CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 231         isPriv = cpsr.mode != MODE_USER;
 232         contextId = tc->readMiscReg(MISCREG_CONTEXTIDR);
 233         prrr = tc->readMiscReg(MISCREG_PRRR);
 234         nmrr = tc->readMiscReg(MISCREG_NMRR);
 235         dacr = tc->readMiscReg(MISCREG_DACR);
 236         miscRegValid = true;
 237     }
 238 public:
 239     inline void invalidateMiscReg() { miscRegValid = false; }
 240 };
 241
 242 } // namespace ArmISA
 243
 244 #endif // __ARCH_ARM_TLB_HH__