src/arch/arm/tlb.hh

   1 /*
   2  * Copyright (c) 2010 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2001-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ali Saidi
  41  */
  42
  43 #ifndef __ARCH_ARM_TLB_HH__
  44 #define __ARCH_ARM_TLB_HH__
  45
  46 #include <map>
  47
  48 #include "arch/arm/isa_traits.hh"
  49 #include "arch/arm/utility.hh"
  50 #include "arch/arm/vtophys.hh"
  51 #include "arch/arm/pagetable.hh"
  52 #include "base/statistics.hh"
  53 #include "mem/request.hh"
  54 #include "params/ArmTLB.hh"
  55 #include "sim/fault.hh"
  56 #include "sim/tlb.hh"
  57
  58 class ThreadContext;
  59
  60 namespace ArmISA {
  61
  62 class TableWalker;
  63
  64 class TLB : public BaseTLB
  65 {
  66   public:
  67     enum ArmFlags {
  68         AlignmentMask = 0x1f,
  69
  70         AlignByte = 0x0,
  71         AlignHalfWord = 0x1,
  72         AlignWord = 0x3,
  73         AlignDoubleWord = 0x7,
  74         AlignQuadWord = 0xf,
  75         AlignOctWord = 0x1f,
  76
  77         AllowUnaligned = 0x20,
  78         // Priv code operating as if it wasn't
  79         UserMode = 0x40,
  80         // Because zero otherwise looks like a valid setting and may be used
  81         // accidentally, this bit must be non-zero to show it was used on
  82         // purpose.
  83         MustBeOne = 0x80
  84     };
  85   protected:
  86     typedef std::multimap<Addr, int> PageTable;
  87     PageTable lookupTable;      // Quick lookup into page table
  88
  89     TlbEntry *table;    // the Page Table
  90     int size;                   // TLB Size
  91     int nlu;                    // not last used entry (for replacement)
  92
  93     uint32_t _attr;      // Memory attributes for last accessed TLB entry
  94
  95 #if FULL_SYSTEM
  96     TableWalker *tableWalker;
  97 #endif
  98
  99     void nextnlu() { if (++nlu >= size) nlu = 0; }
 100     TlbEntry *lookup(Addr vpn, uint8_t asn);
 101
 102     // Access Stats
 103     mutable Stats::Scalar read_hits;
 104     mutable Stats::Scalar read_misses;
 105     mutable Stats::Scalar read_acv;
 106     mutable Stats::Scalar read_accesses;
 107     mutable Stats::Scalar write_hits;
 108     mutable Stats::Scalar write_misses;
 109     mutable Stats::Scalar write_acv;
 110     mutable Stats::Scalar write_accesses;
 111     Stats::Formula hits;
 112     Stats::Formula misses;
 113     Stats::Formula accesses;
 114
 115
 116   public:
 117     typedef ArmTLBParams Params;
 118     TLB(const Params *p);
 119
 120     virtual ~TLB();
 121     int getsize() const { return size; }
 122
 123     void insert(Addr vaddr, TlbEntry &pte);
 124
 125     /** Reset the entire TLB */
 126     void flushAll();
 127
 128     /** Remove any entries that match both a va and asn
 129      * @param mva virtual address to flush
 130      * @param asn contextid/asn to flush on match
 131      */
 132     void flushMvaAsid(Addr mva, uint64_t asn);
 133
 134     /** Remove any entries that match the asn
 135      * @param asn contextid/asn to flush on match
 136      */
 137     void flushAsid(uint64_t asn);
 138
 139     /** Remove all entries that match the va regardless of asn
 140      * @param mva address to flush from cache
 141      */
 142     void flushMva(Addr mva);
 143
 144     Fault trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp);
 145     Fault walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
 146             bool is_write, uint8_t domain, bool sNp);
 147
 148     void printTlb();
 149
 150     void demapPage(Addr vaddr, uint64_t asn)
 151     {
 152         flushMvaAsid(vaddr, asn);
 153     }
 154
 155     static bool validVirtualAddress(Addr vaddr);
 156
 157     /** Accessor functions for memory attributes for last accessed TLB entry
 158      */
 159     void
 160     setAttr(uint32_t attr)
 161     {
 162         _attr = attr;
 163     }
 164     uint32_t
 165     getAttr() const
 166     {
 167         return _attr;
 168     }
 169
 170 #if FULL_SYSTEM
 171     Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
 172             Translation *translation, bool &delay, bool timing);
 173 #else
 174     Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
 175             Translation *translation, bool &delay, bool timing);
 176 #endif
 177     Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
 178     Fault translateTiming(RequestPtr req, ThreadContext *tc,
 179             Translation *translation, Mode mode);
 180
 181     // Checkpointing
 182     void serialize(std::ostream &os);
 183     void unserialize(Checkpoint *cp, const std::string &section);
 184
 185     void regStats();
 186 };
 187
 188 /* namespace ArmISA */ }
 189
 190 #endif // __ARCH_ARM_TLB_HH__