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43 #ifndef __ARCH_ARM_TLB_HH__
44 #define __ARCH_ARM_TLB_HH__
48 #include "arch/arm/isa_traits.hh"
49 #include "arch/arm/utility.hh"
50 #include "arch/arm/vtophys.hh"
51 #include "arch/arm/pagetable.hh"
52 #include "base/statistics.hh"
53 #include "mem/request.hh"
54 #include "params/ArmTLB.hh"
55 #include "sim/fault.hh"
64 class TLB : public BaseTLB
73 AlignDoubleWord = 0x7,
77 AllowUnaligned = 0x20,
78 // Priv code operating as if it wasn't
80 // Because zero otherwise looks like a valid setting and may be used
81 // accidentally, this bit must be non-zero to show it was used on
87 TlbEntry *table; // the Page Table
90 uint32_t _attr; // Memory attributes for last accessed TLB entry
93 TableWalker *tableWalker;
96 /** Lookup an entry in the TLB
97 * @param vpn virtual address
98 * @param asn context id/address space id to use
99 * @param functional if the lookup should modify state
100 * @return pointer to TLB entrry if it exists
102 TlbEntry *lookup(Addr vpn, uint8_t asn, bool functional = false);
105 mutable Stats::Scalar instHits;
106 mutable Stats::Scalar instMisses;
107 mutable Stats::Scalar readHits;
108 mutable Stats::Scalar readMisses;
109 mutable Stats::Scalar writeHits;
110 mutable Stats::Scalar writeMisses;
111 mutable Stats::Scalar inserts;
112 mutable Stats::Scalar flushTlb;
113 mutable Stats::Scalar flushTlbMva;
114 mutable Stats::Scalar flushTlbMvaAsid;
115 mutable Stats::Scalar flushTlbAsid;
116 mutable Stats::Scalar flushedEntries;
117 mutable Stats::Scalar alignFaults;
118 mutable Stats::Scalar prefetchFaults;
119 mutable Stats::Scalar domainFaults;
120 mutable Stats::Scalar permsFaults;
122 Stats::Formula readAccesses;
123 Stats::Formula writeAccesses;
124 Stats::Formula instAccesses;
126 Stats::Formula misses;
127 Stats::Formula accesses;
129 int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
132 typedef ArmTLBParams Params;
133 TLB(const Params *p);
136 int getsize() const { return size; }
138 void insert(Addr vaddr, TlbEntry &pte);
140 /** Reset the entire TLB */
143 /** Remove any entries that match both a va and asn
144 * @param mva virtual address to flush
145 * @param asn contextid/asn to flush on match
147 void flushMvaAsid(Addr mva, uint64_t asn);
149 /** Remove any entries that match the asn
150 * @param asn contextid/asn to flush on match
152 void flushAsid(uint64_t asn);
154 /** Remove all entries that match the va regardless of asn
155 * @param mva address to flush from cache
157 void flushMva(Addr mva);
159 Fault trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp);
160 Fault walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
161 bool is_write, uint8_t domain, bool sNp);
165 void demapPage(Addr vaddr, uint64_t asn)
167 flushMvaAsid(vaddr, asn);
170 static bool validVirtualAddress(Addr vaddr);
173 * Do a functional lookup on the TLB (for debugging)
174 * and don't modify any internal state
175 * @param tc thread context to get the context id from
176 * @param vaddr virtual address to translate
177 * @param pa returned physical address
178 * @return if the translation was successful
180 bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
182 /** Accessor functions for memory attributes for last accessed TLB entry
185 setAttr(uint32_t attr)
196 Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
197 Translation *translation, bool &delay, bool timing);
199 Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
200 Translation *translation, bool &delay, bool timing);
202 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
203 Fault translateTiming(RequestPtr req, ThreadContext *tc,
204 Translation *translation, Mode mode);
207 void serialize(std::ostream &os);
208 void unserialize(Checkpoint *cp, const std::string §ion);
212 // Get the port from the table walker and return it
213 virtual Port *getPort();
215 // Caching misc register values here.
216 // Writing to misc registers needs to invalidate them.
217 // translateFunctional/translateSe/translateFs checks if they are
218 // invalid and call updateMiscReg if necessary.
227 void updateMiscReg(ThreadContext *tc)
229 sctlr = tc->readMiscReg(MISCREG_SCTLR);
230 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
231 isPriv = cpsr.mode != MODE_USER;
232 contextId = tc->readMiscReg(MISCREG_CONTEXTIDR);
233 prrr = tc->readMiscReg(MISCREG_PRRR);
234 nmrr = tc->readMiscReg(MISCREG_NMRR);
235 dacr = tc->readMiscReg(MISCREG_DACR);
239 inline void invalidateMiscReg() { miscRegValid = false; }
242 /* namespace ArmISA */ }
244 #endif // __ARCH_ARM_TLB_HH__