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43 #ifndef __ARCH_ARM_TLB_HH__
44 #define __ARCH_ARM_TLB_HH__
47 #include "arch/arm/isa_traits.hh"
48 #include "arch/arm/pagetable.hh"
49 #include "arch/arm/utility.hh"
50 #include "arch/arm/vtophys.hh"
51 #include "base/statistics.hh"
52 #include "dev/dma_device.hh"
53 #include "mem/request.hh"
54 #include "params/ArmTLB.hh"
55 #include "sim/probe/pmu.hh"
66 class TLB : public BaseTLB
75 AlignDoubleWord = 0x3,
80 // Priv code operating as if it wasn't
82 // Because zero otherwise looks like a valid setting and may be used
83 // accidentally, this bit must be non-zero to show it was used on
88 enum ArmTranslationType {
92 // Secure code operating as if it wasn't (required by some Address
93 // Translate operations)
97 TlbEntry* table; // the Page Table
99 bool isStage2; // Indicates this TLB is part of the second stage MMU
100 bool stage2Req; // Indicates whether a stage 2 lookup is also required
101 uint64_t _attr; // Memory attributes for last accessed TLB entry
102 bool directToStage2; // Indicates whether all translation requests should
103 // be routed directly to the stage 2 TLB
105 TableWalker *tableWalker;
107 Stage2MMU *stage2Mmu;
110 mutable Stats::Scalar instHits;
111 mutable Stats::Scalar instMisses;
112 mutable Stats::Scalar readHits;
113 mutable Stats::Scalar readMisses;
114 mutable Stats::Scalar writeHits;
115 mutable Stats::Scalar writeMisses;
116 mutable Stats::Scalar inserts;
117 mutable Stats::Scalar flushTlb;
118 mutable Stats::Scalar flushTlbMva;
119 mutable Stats::Scalar flushTlbMvaAsid;
120 mutable Stats::Scalar flushTlbAsid;
121 mutable Stats::Scalar flushedEntries;
122 mutable Stats::Scalar alignFaults;
123 mutable Stats::Scalar prefetchFaults;
124 mutable Stats::Scalar domainFaults;
125 mutable Stats::Scalar permsFaults;
127 Stats::Formula readAccesses;
128 Stats::Formula writeAccesses;
129 Stats::Formula instAccesses;
131 Stats::Formula misses;
132 Stats::Formula accesses;
134 /** PMU probe for TLB refills */
135 ProbePoints::PMUUPtr ppRefills;
137 int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
139 bool bootUncacheability;
142 TLB(const ArmTLBParams *p);
143 TLB(const Params *p, int _size, TableWalker *_walker);
145 /** Lookup an entry in the TLB
146 * @param vpn virtual address
147 * @param asn context id/address space id to use
148 * @param vmid The virtual machine ID used for stage 2 translation
149 * @param secure if the lookup is secure
150 * @param hyp if the lookup is done from hyp mode
151 * @param functional if the lookup should modify state
152 * @param ignore_asn if on lookup asn should be ignored
153 * @return pointer to TLB entry if it exists
155 TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp,
156 bool secure, bool functional,
157 bool ignore_asn, uint8_t target_el);
161 void takeOverFrom(BaseTLB *otlb);
163 /// setup all the back pointers
166 void setMMU(Stage2MMU *m);
168 int getsize() const { return size; }
170 void insert(Addr vaddr, TlbEntry &pte);
172 Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode,
173 Translation *translation, bool timing, bool functional,
174 bool is_secure, ArmTranslationType tranType);
176 Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc,
177 Mode mode, Translation *translation, bool timing,
178 bool functional, TlbEntry *mergeTe);
180 Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode);
181 Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode,
185 /** Reset the entire TLB
186 * @param secure_lookup if the operation affects the secure world
188 void flushAllSecurity(bool secure_lookup, uint8_t target_el,
189 bool ignore_el = false);
191 /** Remove all entries in the non secure world, depending on whether they
192 * were allocated in hyp mode or not
193 * @param hyp if the opperation affects hyp mode
195 void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false);
198 /** Reset the entire TLB. Used for CPU switching to prevent stale
199 * translations after multiple switches
203 flushAllSecurity(false, 0, true);
204 flushAllSecurity(true, 0, true);
207 /** Remove any entries that match both a va and asn
208 * @param mva virtual address to flush
209 * @param asn contextid/asn to flush on match
210 * @param secure_lookup if the operation affects the secure world
212 void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup,
215 /** Remove any entries that match the asn
216 * @param asn contextid/asn to flush on match
217 * @param secure_lookup if the operation affects the secure world
219 void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el);
221 /** Remove all entries that match the va regardless of asn
222 * @param mva address to flush from cache
223 * @param secure_lookup if the operation affects the secure world
224 * @param hyp if the operation affects hyp mode
226 void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el);
228 Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain);
229 Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec,
230 bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level);
232 void printTlb() const;
234 void allCpusCaching() { bootUncacheability = true; }
235 void demapPage(Addr vaddr, uint64_t asn)
237 // needed for x86 only
238 panic("demapPage() is not implemented.\n");
241 static bool validVirtualAddress(Addr vaddr);
244 * Do a functional lookup on the TLB (for debugging)
245 * and don't modify any internal state
246 * @param tc thread context to get the context id from
247 * @param vaddr virtual address to translate
248 * @param pa returned physical address
249 * @return if the translation was successful
251 bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
254 * Do a functional lookup on the TLB (for checker cpu) that
255 * behaves like a normal lookup without modifying any page table state.
257 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode,
258 ArmTranslationType tranType = NormalTran);
260 /** Accessor functions for memory attributes for last accessed TLB entry
263 setAttr(uint64_t attr)
274 Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
275 Translation *translation, bool &delay,
276 bool timing, ArmTranslationType tranType, bool functional = false);
277 Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
278 Translation *translation, bool &delay, bool timing);
279 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode,
280 ArmTranslationType tranType = NormalTran);
281 Fault translateTiming(RequestPtr req, ThreadContext *tc,
282 Translation *translation, Mode mode,
283 ArmTranslationType tranType = NormalTran);
284 Fault translateComplete(RequestPtr req, ThreadContext *tc,
285 Translation *translation, Mode mode, ArmTranslationType tranType,
287 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
292 void serialize(std::ostream &os);
293 void unserialize(Checkpoint *cp, const std::string §ion);
297 void regProbePoints() M5_ATTR_OVERRIDE;
300 * Get the table walker master port. This is used for migrating
301 * port connections during a CPU takeOverFrom() call. For
302 * architectures that do not have a table walker, NULL is
303 * returned, hence the use of a pointer rather than a
304 * reference. For ARM this method will always return a valid port
307 * @return A pointer to the walker master port
309 virtual BaseMasterPort* getMasterPort();
312 * Allow the MMU (overseeing both stage 1 and stage 2 TLBs) to
313 * access the table walker port of this TLB so that it can
314 * orchestrate staged translations.
316 * @return The table walker DMA port
318 DmaPort& getWalkerPort();
320 // Caching misc register values here.
321 // Writing to misc registers needs to invalidate them.
322 // translateFunctional/translateSe/translateFs checks if they are
323 // invalid and call updateMiscReg if necessary.
326 ExceptionLevel aarch64EL;
340 ArmTranslationType curTranType;
342 // Cached copies of system-level properties
344 bool haveVirtualization;
345 bool haveLargeAsid64;
347 void updateMiscReg(ThreadContext *tc,
348 ArmTranslationType tranType = NormalTran);
354 return dynamic_cast<const Params *>(_params);
356 inline void invalidateMiscReg() { miscRegValid = false; }
359 /** Remove any entries that match both a va and asn
360 * @param mva virtual address to flush
361 * @param asn contextid/asn to flush on match
362 * @param secure_lookup if the operation affects the secure world
363 * @param hyp if the operation affects hyp mode
364 * @param ignore_asn if the flush should ignore the asn
366 void _flushMva(Addr mva, uint64_t asn, bool secure_lookup,
367 bool hyp, bool ignore_asn, uint8_t target_el);
369 bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el);
372 } // namespace ArmISA
374 #endif // __ARCH_ARM_TLB_HH__