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43 #ifndef __ARCH_ARM_TLB_HH__
44 #define __ARCH_ARM_TLB_HH__
48 #include "arch/arm/isa_traits.hh"
49 #include "arch/arm/utility.hh"
50 #include "arch/arm/vtophys.hh"
51 #include "arch/arm/pagetable.hh"
52 #include "base/statistics.hh"
53 #include "mem/request.hh"
54 #include "params/ArmTLB.hh"
55 #include "sim/faults.hh"
64 class TLB : public BaseTLB
73 AlignDoubleWord = 0x7,
76 // Priv code operating as if it wasn't
78 // Because zero otherwise looks like a valid setting and may be used
79 // accidentally, this bit must be non-zero to show it was used on
84 typedef std::multimap<Addr, int> PageTable;
85 PageTable lookupTable; // Quick lookup into page table
87 TlbEntry *table; // the Page Table
89 int nlu; // not last used entry (for replacement)
92 TableWalker *tableWalker;
95 void nextnlu() { if (++nlu >= size) nlu = 0; }
96 TlbEntry *lookup(Addr vpn, uint8_t asn);
99 mutable Stats::Scalar read_hits;
100 mutable Stats::Scalar read_misses;
101 mutable Stats::Scalar read_acv;
102 mutable Stats::Scalar read_accesses;
103 mutable Stats::Scalar write_hits;
104 mutable Stats::Scalar write_misses;
105 mutable Stats::Scalar write_acv;
106 mutable Stats::Scalar write_accesses;
108 Stats::Formula misses;
109 Stats::Formula invalids;
110 Stats::Formula accesses;
114 typedef ArmTLBParams Params;
115 TLB(const Params *p);
118 int getsize() const { return size; }
120 void insert(Addr vaddr, TlbEntry &pte);
122 /** Reset the entire TLB */
125 /** Remove any entries that match both a va and asn
126 * @param mva virtual address to flush
127 * @param asn contextid/asn to flush on match
129 void flushMvaAsid(Addr mva, uint64_t asn);
131 /** Remove any entries that match the asn
132 * @param asn contextid/asn to flush on match
134 void flushAsid(uint64_t asn);
136 /** Remove all entries that match the va regardless of asn
137 * @param mva address to flush from cache
139 void flushMva(Addr mva);
141 Fault trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp);
142 Fault walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
143 bool is_write, uint8_t domain, bool sNp);
147 void demapPage(Addr vaddr, uint64_t asn)
149 flushMvaAsid(vaddr, asn);
152 static bool validVirtualAddress(Addr vaddr);
155 Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
156 Translation *translation, bool &delay, bool timing);
158 Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
159 Translation *translation, bool &delay, bool timing);
161 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
162 Fault translateTiming(RequestPtr req, ThreadContext *tc,
163 Translation *translation, Mode mode);
166 void serialize(std::ostream &os);
167 void unserialize(Checkpoint *cp, const std::string §ion);
172 /* namespace ArmISA */ }
174 #endif // __ARCH_ARM_TLB_HH__