src/arch/arm/tlbi_op.cc

   1 /*
   2  * Copyright (c) 2018-2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #include "arch/arm/tlbi_op.hh"
  39
  40 #include "arch/arm/tlb.hh"
  41 #include "cpu/checker/cpu.hh"
  42
  43 namespace ArmISA {
  44
  45 void
  46 TLBIALL::operator()(ThreadContext* tc)
  47 {
  48     getITBPtr(tc)->flushAllSecurity(secureLookup, targetEL);
  49     getDTBPtr(tc)->flushAllSecurity(secureLookup, targetEL);
  50
  51     // If CheckerCPU is connected, need to notify it of a flush
  52     CheckerCPU *checker = tc->getCheckerCpuPtr();
  53     if (checker) {
  54         getITBPtr(checker)->flushAllSecurity(secureLookup,
  55                                                targetEL);
  56         getDTBPtr(checker)->flushAllSecurity(secureLookup,
  57                                                targetEL);
  58     }
  59 }
  60
  61 void
  62 ITLBIALL::operator()(ThreadContext* tc)
  63 {
  64     getITBPtr(tc)->flushAllSecurity(secureLookup, targetEL);
  65 }
  66
  67 void
  68 DTLBIALL::operator()(ThreadContext* tc)
  69 {
  70     getDTBPtr(tc)->flushAllSecurity(secureLookup, targetEL);
  71 }
  72
  73 void
  74 TLBIASID::operator()(ThreadContext* tc)
  75 {
  76     getITBPtr(tc)->flushAsid(asid, secureLookup, targetEL);
  77     getDTBPtr(tc)->flushAsid(asid, secureLookup, targetEL);
  78     CheckerCPU *checker = tc->getCheckerCpuPtr();
  79     if (checker) {
  80         getITBPtr(checker)->flushAsid(asid, secureLookup, targetEL);
  81         getDTBPtr(checker)->flushAsid(asid, secureLookup, targetEL);
  82     }
  83 }
  84
  85 void
  86 ITLBIASID::operator()(ThreadContext* tc)
  87 {
  88     getITBPtr(tc)->flushAsid(asid, secureLookup, targetEL);
  89 }
  90
  91 void
  92 DTLBIASID::operator()(ThreadContext* tc)
  93 {
  94     getDTBPtr(tc)->flushAsid(asid, secureLookup, targetEL);
  95 }
  96
  97 void
  98 TLBIALLN::operator()(ThreadContext* tc)
  99 {
 100     getITBPtr(tc)->flushAllNs(targetEL);
 101     getDTBPtr(tc)->flushAllNs(targetEL);
 102
 103     CheckerCPU *checker = tc->getCheckerCpuPtr();
 104     if (checker) {
 105         getITBPtr(checker)->flushAllNs(targetEL);
 106         getDTBPtr(checker)->flushAllNs(targetEL);
 107     }
 108 }
 109
 110 void
 111 TLBIMVAA::operator()(ThreadContext* tc)
 112 {
 113     getITBPtr(tc)->flushMva(addr, secureLookup, targetEL);
 114     getDTBPtr(tc)->flushMva(addr, secureLookup, targetEL);
 115
 116     CheckerCPU *checker = tc->getCheckerCpuPtr();
 117     if (checker) {
 118         getITBPtr(checker)->flushMva(addr, secureLookup, targetEL);
 119         getDTBPtr(checker)->flushMva(addr, secureLookup, targetEL);
 120     }
 121 }
 122
 123 void
 124 TLBIMVA::operator()(ThreadContext* tc)
 125 {
 126     getITBPtr(tc)->flushMvaAsid(addr, asid,
 127                                   secureLookup, targetEL);
 128     getDTBPtr(tc)->flushMvaAsid(addr, asid,
 129                                   secureLookup, targetEL);
 130
 131     CheckerCPU *checker = tc->getCheckerCpuPtr();
 132     if (checker) {
 133         getITBPtr(checker)->flushMvaAsid(
 134             addr, asid, secureLookup, targetEL);
 135         getDTBPtr(checker)->flushMvaAsid(
 136             addr, asid, secureLookup, targetEL);
 137     }
 138 }
 139
 140 void
 141 ITLBIMVA::operator()(ThreadContext* tc)
 142 {
 143     getITBPtr(tc)->flushMvaAsid(
 144         addr, asid, secureLookup, targetEL);
 145 }
 146
 147 void
 148 DTLBIMVA::operator()(ThreadContext* tc)
 149 {
 150     getDTBPtr(tc)->flushMvaAsid(
 151         addr, asid, secureLookup, targetEL);
 152 }
 153
 154 void
 155 TLBIIPA::operator()(ThreadContext* tc)
 156 {
 157     getITBPtr(tc)->flushIpaVmid(addr,
 158         secureLookup, targetEL);
 159     getDTBPtr(tc)->flushIpaVmid(addr,
 160         secureLookup, targetEL);
 161
 162     CheckerCPU *checker = tc->getCheckerCpuPtr();
 163     if (checker) {
 164         getITBPtr(checker)->flushIpaVmid(addr,
 165             secureLookup, targetEL);
 166         getDTBPtr(checker)->flushIpaVmid(addr,
 167             secureLookup, targetEL);
 168     }
 169 }
 170
 171 } // namespace ArmISA