2 * Copyright (c) 2018-2019 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 * Authors: Giacomo Travaglini
40 #include "arch/arm/tlbi_op.hh"
42 #include "arch/arm/tlb.hh"
43 #include "cpu/checker/cpu.hh"
48 TLBIALL::operator()(ThreadContext
* tc
)
50 getITBPtr(tc
)->flushAllSecurity(secureLookup
, targetEL
);
51 getDTBPtr(tc
)->flushAllSecurity(secureLookup
, targetEL
);
53 // If CheckerCPU is connected, need to notify it of a flush
54 CheckerCPU
*checker
= tc
->getCheckerCpuPtr();
56 getITBPtr(checker
)->flushAllSecurity(secureLookup
,
58 getDTBPtr(checker
)->flushAllSecurity(secureLookup
,
64 ITLBIALL::operator()(ThreadContext
* tc
)
66 getITBPtr(tc
)->flushAllSecurity(secureLookup
, targetEL
);
70 DTLBIALL::operator()(ThreadContext
* tc
)
72 getDTBPtr(tc
)->flushAllSecurity(secureLookup
, targetEL
);
76 TLBIASID::operator()(ThreadContext
* tc
)
78 getITBPtr(tc
)->flushAsid(asid
, secureLookup
, targetEL
);
79 getDTBPtr(tc
)->flushAsid(asid
, secureLookup
, targetEL
);
80 CheckerCPU
*checker
= tc
->getCheckerCpuPtr();
82 getITBPtr(checker
)->flushAsid(asid
, secureLookup
, targetEL
);
83 getDTBPtr(checker
)->flushAsid(asid
, secureLookup
, targetEL
);
88 ITLBIASID::operator()(ThreadContext
* tc
)
90 getITBPtr(tc
)->flushAsid(asid
, secureLookup
, targetEL
);
94 DTLBIASID::operator()(ThreadContext
* tc
)
96 getDTBPtr(tc
)->flushAsid(asid
, secureLookup
, targetEL
);
100 TLBIALLN::operator()(ThreadContext
* tc
)
102 getITBPtr(tc
)->flushAllNs(targetEL
);
103 getDTBPtr(tc
)->flushAllNs(targetEL
);
105 CheckerCPU
*checker
= tc
->getCheckerCpuPtr();
107 getITBPtr(checker
)->flushAllNs(targetEL
);
108 getDTBPtr(checker
)->flushAllNs(targetEL
);
113 TLBIMVAA::operator()(ThreadContext
* tc
)
115 getITBPtr(tc
)->flushMva(addr
, secureLookup
, targetEL
);
116 getDTBPtr(tc
)->flushMva(addr
, secureLookup
, targetEL
);
118 CheckerCPU
*checker
= tc
->getCheckerCpuPtr();
120 getITBPtr(checker
)->flushMva(addr
, secureLookup
, targetEL
);
121 getDTBPtr(checker
)->flushMva(addr
, secureLookup
, targetEL
);
126 TLBIMVA::operator()(ThreadContext
* tc
)
128 getITBPtr(tc
)->flushMvaAsid(addr
, asid
,
129 secureLookup
, targetEL
);
130 getDTBPtr(tc
)->flushMvaAsid(addr
, asid
,
131 secureLookup
, targetEL
);
133 CheckerCPU
*checker
= tc
->getCheckerCpuPtr();
135 getITBPtr(checker
)->flushMvaAsid(
136 addr
, asid
, secureLookup
, targetEL
);
137 getDTBPtr(checker
)->flushMvaAsid(
138 addr
, asid
, secureLookup
, targetEL
);
143 ITLBIMVA::operator()(ThreadContext
* tc
)
145 getITBPtr(tc
)->flushMvaAsid(
146 addr
, asid
, secureLookup
, targetEL
);
150 DTLBIMVA::operator()(ThreadContext
* tc
)
152 getDTBPtr(tc
)->flushMvaAsid(
153 addr
, asid
, secureLookup
, targetEL
);
157 TLBIIPA::operator()(ThreadContext
* tc
)
159 getITBPtr(tc
)->flushIpaVmid(addr
,
160 secureLookup
, targetEL
);
161 getDTBPtr(tc
)->flushIpaVmid(addr
,
162 secureLookup
, targetEL
);
164 CheckerCPU
*checker
= tc
->getCheckerCpuPtr();
166 getITBPtr(checker
)->flushIpaVmid(addr
,
167 secureLookup
, targetEL
);
168 getDTBPtr(checker
)->flushIpaVmid(addr
,
169 secureLookup
, targetEL
);
173 } // namespace ArmISA