src/arch/arm/tracers/TarmacTrace.py

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  35
  36 from m5.SimObject import SimObject
  37 from m5.params import *
  38 from m5.objects.InstTracer import InstTracer
  39
  40 class TarmacParser(InstTracer):
  41     type = 'TarmacParser'
  42     cxx_class = 'Trace::TarmacParser'
  43     cxx_header = "arch/arm/tracers/tarmac_parser.hh"
  44
  45     path_to_trace = Param.String("tarmac.log", "path to TARMAC trace")
  46
  47     start_pc = Param.Int(
  48         0x0, "tracing starts when the PC gets this value; ignored if 0x0")
  49
  50     exit_on_diff = Param.Bool(False,
  51         "stop simulation after first mismatch is detected")
  52
  53     exit_on_insn_diff = Param.Bool(False,
  54         "stop simulation after first mismatch on PC or opcode is detected")
  55
  56     mem_wr_check = Param.Bool(False,
  57         "enable check of memory write accesses")
  58
  59     cpu_id = Param.Bool(False,
  60         "true if trace format includes the CPU id")
  61
  62     ignore_mem_addr = Param.AddrRange(AddrRange(0, size=0),
  63         "Range of unverifiable memory addresses")
  64
  65 class TarmacTracer(InstTracer):
  66     type = 'TarmacTracer'
  67     cxx_class = 'Trace::TarmacTracer'
  68     cxx_header = "arch/arm/tracers/tarmac_tracer.hh"
  69
  70     start_tick = Param.Tick(0,
  71         "tracing starts when the tick time gets this value")
  72
  73     end_tick = Param.Tick(MaxTick,
  74         "tracing ends when the tick time gets this value")