src/arch/arm/tracers/tarmac_base.cc

   1 /*
   2  * Copyright (c) 2017-2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #include "arch/arm/tracers/tarmac_base.hh"
  39
  40 #include <algorithm>
  41 #include <string>
  42
  43 #include "config/the_isa.hh"
  44 #include "cpu/reg_class.hh"
  45 #include "cpu/static_inst.hh"
  46 #include "cpu/thread_context.hh"
  47
  48 using namespace ArmISA;
  49
  50 namespace Trace {
  51
  52 TarmacBaseRecord::TarmacBaseRecord(Tick _when, ThreadContext *_thread,
  53                                    const StaticInstPtr _staticInst,
  54                                    PCState _pc,
  55                                    const StaticInstPtr _macroStaticInst)
  56     : InstRecord(_when, _thread, _staticInst, _pc, _macroStaticInst)
  57 {
  58 }
  59
  60 TarmacBaseRecord::InstEntry::InstEntry(
  61     ThreadContext* thread,
  62     PCState pc,
  63     const StaticInstPtr staticInst,
  64     bool predicate)
  65         : taken(predicate) ,
  66           addr(pc.instAddr()) ,
  67           opcode(staticInst->machInst & 0xffffffff),
  68           disassemble(staticInst->disassemble(addr)),
  69           isetstate(pcToISetState(pc)),
  70           mode(MODE_USER)
  71 {
  72
  73     // Operating mode gained by reading the architectural register (CPSR)
  74     const CPSR cpsr = thread->readMiscRegNoEffect(MISCREG_CPSR);
  75     mode = (OperatingMode) (uint8_t)cpsr.mode;
  76
  77     // In Tarmac, instruction names are printed in capital
  78     // letters.
  79     std::for_each(disassemble.begin(), disassemble.end(),
  80                   [](char& c) { c = toupper(c); });
  81 }
  82
  83 TarmacBaseRecord::RegEntry::RegEntry(PCState pc)
  84   : isetstate(pcToISetState(pc)),
  85     values(2, 0)
  86 {
  87     // values vector is constructed with size = 2, for
  88     // holding Lo and Hi values.
  89 }
  90
  91 TarmacBaseRecord::MemEntry::MemEntry (
  92     uint8_t _size,
  93     Addr _addr,
  94     uint64_t _data)
  95       : size(_size), addr(_addr), data(_data)
  96 {
  97 }
  98
  99 TarmacBaseRecord::ISetState
 100 TarmacBaseRecord::pcToISetState(PCState pc)
 101 {
 102     TarmacBaseRecord::ISetState isetstate;
 103
 104     if (pc.aarch64())
 105         isetstate = TarmacBaseRecord::ISET_A64;
 106     else if (!pc.thumb() && !pc.jazelle())
 107         isetstate = TarmacBaseRecord::ISET_ARM;
 108     else if (pc.thumb() && !pc.jazelle())
 109         isetstate = TarmacBaseRecord::ISET_THUMB;
 110     else
 111         // No Jazelle state in TARMAC
 112         isetstate = TarmacBaseRecord::ISET_UNSUPPORTED;
 113
 114     return isetstate;
 115 }
 116
 117 } // namespace Trace