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misc: Replaced master/slave terminology
[gem5.git] / src / arch / arm / tracers / tarmac_parser.cc
1 /*
2 * Copyright (c) 2011,2017-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #include <algorithm>
39 #include <cctype>
40 #include <cstring>
41 #include <iomanip>
42 #include <string>
43
44 #include "arch/arm/tracers/tarmac_parser.hh"
45
46 #include "arch/arm/tlb.hh"
47 #include "arch/arm/insts/static_inst.hh"
48 #include "config/the_isa.hh"
49 #include "cpu/static_inst.hh"
50 #include "cpu/thread_context.hh"
51 #include "mem/packet.hh"
52 #include "mem/port_proxy.hh"
53 #include "sim/core.hh"
54 #include "sim/faults.hh"
55 #include "sim/sim_exit.hh"
56
57 using namespace std;
58 using namespace ArmISA;
59
60 namespace Trace {
61
62 // TARMAC Parser static variables
63 const int TarmacParserRecord::MaxLineLength;
64 int8_t TarmacParserRecord::maxVectorLength = 0;
65
66 TarmacParserRecord::ParserInstEntry TarmacParserRecord::instRecord;
67 TarmacParserRecord::ParserRegEntry TarmacParserRecord::regRecord;
68 TarmacParserRecord::ParserMemEntry TarmacParserRecord::memRecord;
69 TarmacBaseRecord::TarmacRecordType TarmacParserRecord::currRecordType;
70
71 list<TarmacParserRecord::ParserRegEntry> TarmacParserRecord::destRegRecords;
72 char TarmacParserRecord::buf[TarmacParserRecord::MaxLineLength];
73 TarmacParserRecord::MiscRegMap TarmacParserRecord::miscRegMap = {
74
75 { "cpsr", MISCREG_CPSR },
76 { "nzcv", MISCREG_NZCV },
77
78 // AArch32 CP14 registers
79 { "dbgdidr", MISCREG_DBGDIDR },
80 { "dbgdscrint", MISCREG_DBGDSCRint },
81 { "dbgdccint", MISCREG_DBGDCCINT },
82 { "dbgdtrtxint", MISCREG_DBGDTRTXint },
83 { "dbgdtrrxint", MISCREG_DBGDTRRXint },
84 { "dbgwfar", MISCREG_DBGWFAR },
85 { "dbgvcr", MISCREG_DBGVCR },
86 { "dbgdtrrxext", MISCREG_DBGDTRRXext },
87 { "dbgdscrext", MISCREG_DBGDSCRext },
88 { "dbgdtrtxext", MISCREG_DBGDTRTXext },
89 { "dbgoseccr", MISCREG_DBGOSECCR },
90 { "dbgbvr0", MISCREG_DBGBVR0 },
91 { "dbgbvr1", MISCREG_DBGBVR1 },
92 { "dbgbvr2", MISCREG_DBGBVR2 },
93 { "dbgbvr3", MISCREG_DBGBVR3 },
94 { "dbgbvr4", MISCREG_DBGBVR4 },
95 { "dbgbvr5", MISCREG_DBGBVR5 },
96 { "dbgbvr6", MISCREG_DBGBVR6 },
97 { "dbgbvr7", MISCREG_DBGBVR7 },
98 { "dbgbvr8", MISCREG_DBGBVR8 },
99 { "dbgbvr9", MISCREG_DBGBVR9 },
100 { "dbgbvr10", MISCREG_DBGBVR10 },
101 { "dbgbvr11", MISCREG_DBGBVR11 },
102 { "dbgbvr12", MISCREG_DBGBVR12 },
103 { "dbgbvr13", MISCREG_DBGBVR13 },
104 { "dbgbvr14", MISCREG_DBGBVR14 },
105 { "dbgbvr15", MISCREG_DBGBVR15 },
106 { "dbgbcr0", MISCREG_DBGBCR0 },
107 { "dbgbcr1", MISCREG_DBGBCR1 },
108 { "dbgbcr2", MISCREG_DBGBCR2 },
109 { "dbgbcr3", MISCREG_DBGBCR3 },
110 { "dbgbcr4", MISCREG_DBGBCR4 },
111 { "dbgbcr5", MISCREG_DBGBCR5 },
112 { "dbgbcr6", MISCREG_DBGBCR6 },
113 { "dbgbcr7", MISCREG_DBGBCR7 },
114 { "dbgbcr8", MISCREG_DBGBCR8 },
115 { "dbgbcr9", MISCREG_DBGBCR9 },
116 { "dbgbcr10", MISCREG_DBGBCR10 },
117 { "dbgbcr11", MISCREG_DBGBCR11 },
118 { "dbgbcr12", MISCREG_DBGBCR12 },
119 { "dbgbcr13", MISCREG_DBGBCR13 },
120 { "dbgbcr14", MISCREG_DBGBCR14 },
121 { "dbgbcr15", MISCREG_DBGBCR15 },
122 { "dbgwvr0", MISCREG_DBGWVR0 },
123 { "dbgwvr1", MISCREG_DBGWVR1 },
124 { "dbgwvr2", MISCREG_DBGWVR2 },
125 { "dbgwvr3", MISCREG_DBGWVR3 },
126 { "dbgwvr4", MISCREG_DBGWVR4 },
127 { "dbgwvr5", MISCREG_DBGWVR5 },
128 { "dbgwvr6", MISCREG_DBGWVR6 },
129 { "dbgwvr7", MISCREG_DBGWVR7 },
130 { "dbgwvr8", MISCREG_DBGWVR8 },
131 { "dbgwvr9", MISCREG_DBGWVR9 },
132 { "dbgwvr10", MISCREG_DBGWVR10 },
133 { "dbgwvr11", MISCREG_DBGWVR11 },
134 { "dbgwvr12", MISCREG_DBGWVR12 },
135 { "dbgwvr13", MISCREG_DBGWVR13 },
136 { "dbgwvr14", MISCREG_DBGWVR14 },
137 { "dbgwvr15", MISCREG_DBGWVR15 },
138 { "dbgwcr0", MISCREG_DBGWCR0 },
139 { "dbgwcr1", MISCREG_DBGWCR1 },
140 { "dbgwcr2", MISCREG_DBGWCR2 },
141 { "dbgwcr3", MISCREG_DBGWCR3 },
142 { "dbgwcr4", MISCREG_DBGWCR4 },
143 { "dbgwcr5", MISCREG_DBGWCR5 },
144 { "dbgwcr6", MISCREG_DBGWCR6 },
145 { "dbgwcr7", MISCREG_DBGWCR7 },
146 { "dbgwcr8", MISCREG_DBGWCR8 },
147 { "dbgwcr9", MISCREG_DBGWCR9 },
148 { "dbgwcr10", MISCREG_DBGWCR10 },
149 { "dbgwcr11", MISCREG_DBGWCR11 },
150 { "dbgwcr12", MISCREG_DBGWCR12 },
151 { "dbgwcr13", MISCREG_DBGWCR13 },
152 { "dbgwcr14", MISCREG_DBGWCR14 },
153 { "dbgwcr15", MISCREG_DBGWCR15 },
154 { "dbgdrar", MISCREG_DBGDRAR },
155 { "dbgbxvr0", MISCREG_DBGBXVR0 },
156 { "dbgbxvr1", MISCREG_DBGBXVR1 },
157 { "dbgbxvr2", MISCREG_DBGBXVR2 },
158 { "dbgbxvr3", MISCREG_DBGBXVR3 },
159 { "dbgbxvr4", MISCREG_DBGBXVR4 },
160 { "dbgbxvr5", MISCREG_DBGBXVR5 },
161 { "dbgbxvr6", MISCREG_DBGBXVR6 },
162 { "dbgbxvr7", MISCREG_DBGBXVR7 },
163 { "dbgbxvr8", MISCREG_DBGBXVR8 },
164 { "dbgbxvr9", MISCREG_DBGBXVR9 },
165 { "dbgbxvr10", MISCREG_DBGBXVR10 },
166 { "dbgbxvr11", MISCREG_DBGBXVR11 },
167 { "dbgbxvr12", MISCREG_DBGBXVR12 },
168 { "dbgbxvr13", MISCREG_DBGBXVR13 },
169 { "dbgbxvr14", MISCREG_DBGBXVR14 },
170 { "dbgbxvr15", MISCREG_DBGBXVR15 },
171 { "dbgoslar", MISCREG_DBGOSLAR },
172 { "dbgoslsr", MISCREG_DBGOSLSR },
173 { "dbgosdlr", MISCREG_DBGOSDLR },
174 { "dbgprcr", MISCREG_DBGPRCR },
175 { "dbgdsar", MISCREG_DBGDSAR },
176 { "dbgclaimset", MISCREG_DBGCLAIMSET },
177 { "dbgclaimclr", MISCREG_DBGCLAIMCLR },
178 { "dbgauthstatus", MISCREG_DBGAUTHSTATUS },
179 { "dbgdevid2", MISCREG_DBGDEVID2 },
180 { "dbgdevid1", MISCREG_DBGDEVID1 },
181 { "dbgdevid0", MISCREG_DBGDEVID0 },
182 { "teecr", MISCREG_TEECR },
183 { "jidr", MISCREG_JIDR },
184 { "teehbr", MISCREG_TEEHBR },
185 { "joscr", MISCREG_JOSCR },
186 { "jmcr", MISCREG_JMCR },
187
188 // AArch32 CP15 registers
189 { "midr", MISCREG_MIDR },
190 { "ctr", MISCREG_CTR },
191 { "tcmtr", MISCREG_TCMTR },
192 { "tlbtr", MISCREG_TLBTR },
193 { "mpidr", MISCREG_MPIDR },
194 { "revidr", MISCREG_REVIDR },
195 { "id_pfr0", MISCREG_ID_PFR0 },
196 { "id_pfr1", MISCREG_ID_PFR1 },
197 { "id_dfr0", MISCREG_ID_DFR0 },
198 { "id_afr0", MISCREG_ID_AFR0 },
199 { "id_mmfr0", MISCREG_ID_MMFR0 },
200 { "id_mmfr1", MISCREG_ID_MMFR1 },
201 { "id_mmfr2", MISCREG_ID_MMFR2 },
202 { "id_mmfr3", MISCREG_ID_MMFR3 },
203 { "id_isar0", MISCREG_ID_ISAR0 },
204 { "id_isar1", MISCREG_ID_ISAR1 },
205 { "id_isar2", MISCREG_ID_ISAR2 },
206 { "id_isar3", MISCREG_ID_ISAR3 },
207 { "id_isar4", MISCREG_ID_ISAR4 },
208 { "id_isar5", MISCREG_ID_ISAR5 },
209 { "ccsidr", MISCREG_CCSIDR },
210 { "clidr", MISCREG_CLIDR },
211 { "aidr", MISCREG_AIDR },
212 { "csselr_ns", MISCREG_CSSELR_NS },
213 { "csselr_s", MISCREG_CSSELR_S },
214 { "vpidr", MISCREG_VPIDR },
215 { "vmpidr", MISCREG_VMPIDR },
216 { "sctlr_ns", MISCREG_SCTLR_NS },
217 { "sctlr_s", MISCREG_SCTLR_S },
218 { "actlr_ns", MISCREG_ACTLR_NS },
219 { "actlr_s", MISCREG_ACTLR_S },
220 { "cpacr", MISCREG_CPACR },
221 { "scr", MISCREG_SCR },
222 { "sder", MISCREG_SDER },
223 { "nsacr", MISCREG_NSACR },
224 { "hsctlr", MISCREG_HSCTLR },
225 { "hactlr", MISCREG_HACTLR },
226 { "hcr", MISCREG_HCR },
227 { "hcr2", MISCREG_HCR2 },
228 { "hdcr", MISCREG_HDCR },
229 { "hcptr", MISCREG_HCPTR },
230 { "hstr", MISCREG_HSTR },
231 { "hacr", MISCREG_HACR },
232 { "ttbr0_ns", MISCREG_TTBR0_NS },
233 { "ttbr0_s", MISCREG_TTBR0_S },
234 { "ttbr1_ns", MISCREG_TTBR1_NS },
235 { "ttbr1_s", MISCREG_TTBR1_S },
236 { "ttbcr_ns", MISCREG_TTBCR_NS },
237 { "ttbcr_s", MISCREG_TTBCR_S },
238 { "htcr", MISCREG_HTCR },
239 { "vtcr", MISCREG_VTCR },
240 { "dacr_ns", MISCREG_DACR_NS },
241 { "dacr_s", MISCREG_DACR_S },
242 { "dfsr_ns", MISCREG_DFSR_NS },
243 { "dfsr_s", MISCREG_DFSR_S },
244 { "ifsr_ns", MISCREG_IFSR_NS },
245 { "ifsr_s", MISCREG_IFSR_S },
246 { "adfsr_ns", MISCREG_ADFSR_NS },
247 { "adfsr_s", MISCREG_ADFSR_S },
248 { "aifsr_ns", MISCREG_AIFSR_NS },
249 { "aifsr_s", MISCREG_AIFSR_S },
250 { "hadfsr", MISCREG_HADFSR },
251 { "haifsr", MISCREG_HAIFSR },
252 { "hsr", MISCREG_HSR },
253 { "dfar_ns", MISCREG_DFAR_NS },
254 { "dfar_s", MISCREG_DFAR_S },
255 { "ifar_ns", MISCREG_IFAR_NS },
256 { "ifar_s", MISCREG_IFAR_S },
257 { "hdfar", MISCREG_HDFAR },
258 { "hifar", MISCREG_HIFAR },
259 { "hpfar", MISCREG_HPFAR },
260 { "icialluis", MISCREG_ICIALLUIS },
261 { "bpiallis", MISCREG_BPIALLIS },
262 { "par_ns", MISCREG_PAR_NS },
263 { "par_s", MISCREG_PAR_S },
264 { "iciallu", MISCREG_ICIALLU },
265 { "icimvau", MISCREG_ICIMVAU },
266 { "cp15isb", MISCREG_CP15ISB },
267 { "bpiall", MISCREG_BPIALL },
268 { "bpimva", MISCREG_BPIMVA },
269 { "dcimvac", MISCREG_DCIMVAC },
270 { "dcisw", MISCREG_DCISW },
271 { "ats1cpr", MISCREG_ATS1CPR },
272 { "ats1cpw", MISCREG_ATS1CPW },
273 { "ats1cur", MISCREG_ATS1CUR },
274 { "ats1cuw", MISCREG_ATS1CUW },
275 { "ats12nsopr", MISCREG_ATS12NSOPR },
276 { "ats12nsopw", MISCREG_ATS12NSOPW },
277 { "ats12nsour", MISCREG_ATS12NSOUR },
278 { "ats12nsouw", MISCREG_ATS12NSOUW },
279 { "dccmvac", MISCREG_DCCMVAC },
280 { "dccsw", MISCREG_DCCSW },
281 { "cp15dsb", MISCREG_CP15DSB },
282 { "cp15dmb", MISCREG_CP15DMB },
283 { "dccmvau", MISCREG_DCCMVAU },
284 { "dccimvac", MISCREG_DCCIMVAC },
285 { "dccisw", MISCREG_DCCISW },
286 { "ats1hr", MISCREG_ATS1HR },
287 { "ats1hw", MISCREG_ATS1HW },
288 { "tlbiallis", MISCREG_TLBIALLIS },
289 { "tlbimvais", MISCREG_TLBIMVAIS },
290 { "tlbiasidis", MISCREG_TLBIASIDIS },
291 { "tlbimvaais", MISCREG_TLBIMVAAIS },
292 { "tlbimvalis", MISCREG_TLBIMVALIS },
293 { "tlbimvaalis", MISCREG_TLBIMVAALIS },
294 { "itlbiall", MISCREG_ITLBIALL },
295 { "itlbimva", MISCREG_ITLBIMVA },
296 { "itlbiasid", MISCREG_ITLBIASID },
297 { "dtlbiall", MISCREG_DTLBIALL },
298 { "dtlbimva", MISCREG_DTLBIMVA },
299 { "dtlbiasid", MISCREG_DTLBIASID },
300 { "tlbiall", MISCREG_TLBIALL },
301 { "tlbimva", MISCREG_TLBIMVA },
302 { "tlbiasid", MISCREG_TLBIASID },
303 { "tlbimvaa", MISCREG_TLBIMVAA },
304 { "tlbimval", MISCREG_TLBIMVAL },
305 { "tlbimvaal", MISCREG_TLBIMVAAL },
306 { "tlbiipas2is", MISCREG_TLBIIPAS2IS },
307 { "tlbiipas2lis", MISCREG_TLBIIPAS2LIS },
308 { "tlbiallhis", MISCREG_TLBIALLHIS },
309 { "tlbimvahis", MISCREG_TLBIMVAHIS },
310 { "tlbiallnsnhis", MISCREG_TLBIALLNSNHIS },
311 { "tlbimvalhis", MISCREG_TLBIMVALHIS },
312 { "tlbiipas2", MISCREG_TLBIIPAS2 },
313 { "tlbiipas2l", MISCREG_TLBIIPAS2L },
314 { "tlbiallh", MISCREG_TLBIALLH },
315 { "tlbimvah", MISCREG_TLBIMVAH },
316 { "tlbiallnsnh", MISCREG_TLBIALLNSNH },
317 { "tlbimvalh", MISCREG_TLBIMVALH },
318 { "pmcr", MISCREG_PMCR },
319 { "pmcntenset", MISCREG_PMCNTENSET },
320 { "pmcntenclr", MISCREG_PMCNTENCLR },
321 { "pmovsr", MISCREG_PMOVSR },
322 { "pmswinc", MISCREG_PMSWINC },
323 { "pmselr", MISCREG_PMSELR },
324 { "pmceid0", MISCREG_PMCEID0 },
325 { "pmceid1", MISCREG_PMCEID1 },
326 { "pmccntr", MISCREG_PMCCNTR },
327 { "pmxevtyper", MISCREG_PMXEVTYPER },
328 { "pmccfiltr", MISCREG_PMCCFILTR },
329 { "pmxevcntr", MISCREG_PMXEVCNTR },
330 { "pmuserenr", MISCREG_PMUSERENR },
331 { "pmintenset", MISCREG_PMINTENSET },
332 { "pmintenclr", MISCREG_PMINTENCLR },
333 { "pmovsset", MISCREG_PMOVSSET },
334 { "l2ctlr", MISCREG_L2CTLR },
335 { "l2ectlr", MISCREG_L2ECTLR },
336 { "prrr_ns", MISCREG_PRRR_NS },
337 { "prrr_s", MISCREG_PRRR_S },
338 { "mair0_ns", MISCREG_MAIR0_NS },
339 { "mair0_s", MISCREG_MAIR0_S },
340 { "nmrr_ns", MISCREG_NMRR_NS },
341 { "nmrr_s", MISCREG_NMRR_S },
342 { "mair1_ns", MISCREG_MAIR1_NS },
343 { "mair1_s", MISCREG_MAIR1_S },
344 { "amair0_ns", MISCREG_AMAIR0_NS },
345 { "amair0_s", MISCREG_AMAIR0_S },
346 { "amair1_ns", MISCREG_AMAIR1_NS },
347 { "amair1_s", MISCREG_AMAIR1_S },
348 { "hmair0", MISCREG_HMAIR0 },
349 { "hmair1", MISCREG_HMAIR1 },
350 { "hamair0", MISCREG_HAMAIR0 },
351 { "hamair1", MISCREG_HAMAIR1 },
352 { "vbar_ns", MISCREG_VBAR_NS },
353 { "vbar_s", MISCREG_VBAR_S },
354 { "mvbar", MISCREG_MVBAR },
355 { "rmr", MISCREG_RMR },
356 { "isr", MISCREG_ISR },
357 { "hvbar", MISCREG_HVBAR },
358 { "fcseidr", MISCREG_FCSEIDR },
359 { "contextidr_ns", MISCREG_CONTEXTIDR_NS },
360 { "contextidr_s", MISCREG_CONTEXTIDR_S },
361 { "tpidrurw_ns", MISCREG_TPIDRURW_NS },
362 { "tpidrurw_s", MISCREG_TPIDRURW_S },
363 { "tpidruro_ns", MISCREG_TPIDRURO_NS },
364 { "tpidruro_s", MISCREG_TPIDRURO_S },
365 { "tpidrprw_ns", MISCREG_TPIDRPRW_NS },
366 { "tpidrprw_s", MISCREG_TPIDRPRW_S },
367 { "htpidr", MISCREG_HTPIDR },
368 { "cntfrq", MISCREG_CNTFRQ },
369 { "cntkctl", MISCREG_CNTKCTL },
370 { "cntp_tval_ns", MISCREG_CNTP_TVAL_NS },
371 { "cntp_tval_s", MISCREG_CNTP_TVAL_S },
372 { "cntp_ctl_ns", MISCREG_CNTP_CTL_NS },
373 { "cntp_ctl_s", MISCREG_CNTP_CTL_S },
374 { "cntv_tval", MISCREG_CNTV_TVAL },
375 { "cntv_ctl", MISCREG_CNTV_CTL },
376 { "cnthctl", MISCREG_CNTHCTL },
377 { "cnthp_tval", MISCREG_CNTHP_TVAL },
378 { "cnthp_ctl", MISCREG_CNTHP_CTL },
379 { "il1data0", MISCREG_IL1DATA0 },
380 { "il1data1", MISCREG_IL1DATA1 },
381 { "il1data2", MISCREG_IL1DATA2 },
382 { "il1data3", MISCREG_IL1DATA3 },
383 { "dl1data0", MISCREG_DL1DATA0 },
384 { "dl1data1", MISCREG_DL1DATA1 },
385 { "dl1data2", MISCREG_DL1DATA2 },
386 { "dl1data3", MISCREG_DL1DATA3 },
387 { "dl1data4", MISCREG_DL1DATA4 },
388 { "ramindex", MISCREG_RAMINDEX },
389 { "l2actlr", MISCREG_L2ACTLR },
390 { "cbar", MISCREG_CBAR },
391 { "httbr", MISCREG_HTTBR },
392 { "vttbr", MISCREG_VTTBR },
393 { "cntpct", MISCREG_CNTPCT },
394 { "cntvct", MISCREG_CNTVCT },
395 { "cntp_cval_ns", MISCREG_CNTP_CVAL_NS },
396 { "cntp_cval_s", MISCREG_CNTP_CVAL_S },
397 { "cntv_cval", MISCREG_CNTV_CVAL },
398 { "cntvoff", MISCREG_CNTVOFF },
399 { "cnthp_cval", MISCREG_CNTHP_CVAL },
400 { "cpumerrsr", MISCREG_CPUMERRSR },
401 { "l2merrsr", MISCREG_L2MERRSR },
402
403 // AArch64 registers (Op0=2)
404 { "mdccint_el1", MISCREG_MDCCINT_EL1 },
405 { "osdtrrx_el1", MISCREG_OSDTRRX_EL1 },
406 { "mdscr_el1", MISCREG_MDSCR_EL1 },
407 { "osdtrtx_el1", MISCREG_OSDTRTX_EL1 },
408 { "oseccr_el1", MISCREG_OSECCR_EL1 },
409 { "dbgbvr0_el1", MISCREG_DBGBVR0_EL1 },
410 { "dbgbvr1_el1", MISCREG_DBGBVR1_EL1 },
411 { "dbgbvr2_el1", MISCREG_DBGBVR2_EL1 },
412 { "dbgbvr3_el1", MISCREG_DBGBVR3_EL1 },
413 { "dbgbvr4_el1", MISCREG_DBGBVR4_EL1 },
414 { "dbgbvr5_el1", MISCREG_DBGBVR5_EL1 },
415 { "dbgbvr6_el1", MISCREG_DBGBVR6_EL1 },
416 { "dbgbvr7_el1", MISCREG_DBGBVR7_EL1 },
417 { "dbgbvr8_el1", MISCREG_DBGBVR8_EL1 },
418 { "dbgbvr9_el1", MISCREG_DBGBVR9_EL1 },
419 { "dbgbvr10_el1", MISCREG_DBGBVR10_EL1 },
420 { "dbgbvr11_el1", MISCREG_DBGBVR11_EL1 },
421 { "dbgbvr12_el1", MISCREG_DBGBVR12_EL1 },
422 { "dbgbvr13_el1", MISCREG_DBGBVR13_EL1 },
423 { "dbgbvr14_el1", MISCREG_DBGBVR14_EL1 },
424 { "dbgbvr15_el1", MISCREG_DBGBVR15_EL1 },
425 { "dbgbcr0_el1", MISCREG_DBGBCR0_EL1 },
426 { "dbgbcr1_el1", MISCREG_DBGBCR1_EL1 },
427 { "dbgbcr2_el1", MISCREG_DBGBCR2_EL1 },
428 { "dbgbcr3_el1", MISCREG_DBGBCR3_EL1 },
429 { "dbgbcr4_el1", MISCREG_DBGBCR4_EL1 },
430 { "dbgbcr5_el1", MISCREG_DBGBCR5_EL1 },
431 { "dbgbcr6_el1", MISCREG_DBGBCR6_EL1 },
432 { "dbgbcr7_el1", MISCREG_DBGBCR7_EL1 },
433 { "dbgbcr8_el1", MISCREG_DBGBCR8_EL1 },
434 { "dbgbcr9_el1", MISCREG_DBGBCR9_EL1 },
435 { "dbgbcr10_el1", MISCREG_DBGBCR10_EL1 },
436 { "dbgbcr11_el1", MISCREG_DBGBCR11_EL1 },
437 { "dbgbcr12_el1", MISCREG_DBGBCR12_EL1 },
438 { "dbgbcr13_el1", MISCREG_DBGBCR13_EL1 },
439 { "dbgbcr14_el1", MISCREG_DBGBCR14_EL1 },
440 { "dbgbcr15_el1", MISCREG_DBGBCR15_EL1 },
441 { "dbgwvr0_el1", MISCREG_DBGWVR0_EL1 },
442 { "dbgwvr1_el1", MISCREG_DBGWVR1_EL1 },
443 { "dbgwvr2_el1", MISCREG_DBGWVR2_EL1 },
444 { "dbgwvr3_el1", MISCREG_DBGWVR3_EL1 },
445 { "dbgwvr4_el1", MISCREG_DBGWVR4_EL1 },
446 { "dbgwvr5_el1", MISCREG_DBGWVR5_EL1 },
447 { "dbgwvr6_el1", MISCREG_DBGWVR6_EL1 },
448 { "dbgwvr7_el1", MISCREG_DBGWVR7_EL1 },
449 { "dbgwvr8_el1", MISCREG_DBGWVR8_EL1 },
450 { "dbgwvr9_el1", MISCREG_DBGWVR9_EL1 },
451 { "dbgwvr10_el1", MISCREG_DBGWVR10_EL1 },
452 { "dbgwvr11_el1", MISCREG_DBGWVR11_EL1 },
453 { "dbgwvr12_el1", MISCREG_DBGWVR12_EL1 },
454 { "dbgwvr13_el1", MISCREG_DBGWVR13_EL1 },
455 { "dbgwvr14_el1", MISCREG_DBGWVR14_EL1 },
456 { "dbgwvr15_el1", MISCREG_DBGWVR15_EL1 },
457 { "dbgwcr0_el1", MISCREG_DBGWCR0_EL1 },
458 { "dbgwcr1_el1", MISCREG_DBGWCR1_EL1 },
459 { "dbgwcr2_el1", MISCREG_DBGWCR2_EL1 },
460 { "dbgwcr3_el1", MISCREG_DBGWCR3_EL1 },
461 { "dbgwcr4_el1", MISCREG_DBGWCR4_EL1 },
462 { "dbgwcr5_el1", MISCREG_DBGWCR5_EL1 },
463 { "dbgwcr6_el1", MISCREG_DBGWCR6_EL1 },
464 { "dbgwcr7_el1", MISCREG_DBGWCR7_EL1 },
465 { "dbgwcr8_el1", MISCREG_DBGWCR8_EL1 },
466 { "dbgwcr9_el1", MISCREG_DBGWCR9_EL1 },
467 { "dbgwcr10_el1", MISCREG_DBGWCR10_EL1 },
468 { "dbgwcr11_el1", MISCREG_DBGWCR11_EL1 },
469 { "dbgwcr12_el1", MISCREG_DBGWCR12_EL1 },
470 { "dbgwcr13_el1", MISCREG_DBGWCR13_EL1 },
471 { "dbgwcr14_el1", MISCREG_DBGWCR14_EL1 },
472 { "dbgwcr15_el1", MISCREG_DBGWCR15_EL1 },
473 { "mdccsr_el0", MISCREG_MDCCSR_EL0 },
474 { "mddtr_el0", MISCREG_MDDTR_EL0 },
475 { "mddtrtx_el0", MISCREG_MDDTRTX_EL0 },
476 { "mddtrrx_el0", MISCREG_MDDTRRX_EL0 },
477 { "dbgvcr32_el2", MISCREG_DBGVCR32_EL2 },
478 { "mdrar_el1", MISCREG_MDRAR_EL1 },
479 { "oslar_el1", MISCREG_OSLAR_EL1 },
480 { "oslsr_el1", MISCREG_OSLSR_EL1 },
481 { "osdlr_el1", MISCREG_OSDLR_EL1 },
482 { "dbgprcr_el1", MISCREG_DBGPRCR_EL1 },
483 { "dbgclaimset_el1", MISCREG_DBGCLAIMSET_EL1 },
484 { "dbgclaimclr_el1", MISCREG_DBGCLAIMCLR_EL1 },
485 { "dbgauthstatus_el1", MISCREG_DBGAUTHSTATUS_EL1 },
486 { "teecr32_el1", MISCREG_TEECR32_EL1 },
487 { "teehbr32_el1", MISCREG_TEEHBR32_EL1 },
488
489 // AArch64 registers (Op0=1,3)
490 { "midr_el1", MISCREG_MIDR_EL1 },
491 { "mpidr_el1", MISCREG_MPIDR_EL1 },
492 { "revidr_el1", MISCREG_REVIDR_EL1 },
493 { "id_pfr0_el1", MISCREG_ID_PFR0_EL1 },
494 { "id_pfr1_el1", MISCREG_ID_PFR1_EL1 },
495 { "id_dfr0_el1", MISCREG_ID_DFR0_EL1 },
496 { "id_afr0_el1", MISCREG_ID_AFR0_EL1 },
497 { "id_mmfr0_el1", MISCREG_ID_MMFR0_EL1 },
498 { "id_mmfr1_el1", MISCREG_ID_MMFR1_EL1 },
499 { "id_mmfr2_el1", MISCREG_ID_MMFR2_EL1 },
500 { "id_mmfr3_el1", MISCREG_ID_MMFR3_EL1 },
501 { "id_isar0_el1", MISCREG_ID_ISAR0_EL1 },
502 { "id_isar1_el1", MISCREG_ID_ISAR1_EL1 },
503 { "id_isar2_el1", MISCREG_ID_ISAR2_EL1 },
504 { "id_isar3_el1", MISCREG_ID_ISAR3_EL1 },
505 { "id_isar4_el1", MISCREG_ID_ISAR4_EL1 },
506 { "id_isar5_el1", MISCREG_ID_ISAR5_EL1 },
507 { "mvfr0_el1", MISCREG_MVFR0_EL1 },
508 { "mvfr1_el1", MISCREG_MVFR1_EL1 },
509 { "mvfr2_el1", MISCREG_MVFR2_EL1 },
510 { "id_aa64pfr0_el1", MISCREG_ID_AA64PFR0_EL1 },
511 { "id_aa64pfr1_el1", MISCREG_ID_AA64PFR1_EL1 },
512 { "id_aa64dfr0_el1", MISCREG_ID_AA64DFR0_EL1 },
513 { "id_aa64dfr1_el1", MISCREG_ID_AA64DFR1_EL1 },
514 { "id_aa64afr0_el1", MISCREG_ID_AA64AFR0_EL1 },
515 { "id_aa64afr1_el1", MISCREG_ID_AA64AFR1_EL1 },
516 { "id_aa64isar0_el1", MISCREG_ID_AA64ISAR0_EL1 },
517 { "id_aa64isar1_el1", MISCREG_ID_AA64ISAR1_EL1 },
518 { "id_aa64mmfr0_el1", MISCREG_ID_AA64MMFR0_EL1 },
519 { "id_aa64mmfr1_el1", MISCREG_ID_AA64MMFR1_EL1 },
520 { "id_aa64mmfr2_el1", MISCREG_ID_AA64MMFR2_EL1 },
521 { "ccsidr_el1", MISCREG_CCSIDR_EL1 },
522 { "clidr_el1", MISCREG_CLIDR_EL1 },
523 { "aidr_el1", MISCREG_AIDR_EL1 },
524 { "csselr_el1", MISCREG_CSSELR_EL1 },
525 { "ctr_el0", MISCREG_CTR_EL0 },
526 { "dczid_el0", MISCREG_DCZID_EL0 },
527 { "vpidr_el2", MISCREG_VPIDR_EL2 },
528 { "vmpidr_el2", MISCREG_VMPIDR_EL2 },
529 { "sctlr_el1", MISCREG_SCTLR_EL1 },
530 { "actlr_el1", MISCREG_ACTLR_EL1 },
531 { "cpacr_el1", MISCREG_CPACR_EL1 },
532 { "sctlr_el2", MISCREG_SCTLR_EL2 },
533 { "actlr_el2", MISCREG_ACTLR_EL2 },
534 { "hcr_el2", MISCREG_HCR_EL2 },
535 { "mdcr_el2", MISCREG_MDCR_EL2 },
536 { "cptr_el2", MISCREG_CPTR_EL2 },
537 { "hstr_el2", MISCREG_HSTR_EL2 },
538 { "hacr_el2", MISCREG_HACR_EL2 },
539 { "sctlr_el3", MISCREG_SCTLR_EL3 },
540 { "actlr_el3", MISCREG_ACTLR_EL3 },
541 { "scr_el3", MISCREG_SCR_EL3 },
542 { "sder32_el3", MISCREG_SDER32_EL3 },
543 { "cptr_el3", MISCREG_CPTR_EL3 },
544 { "mdcr_el3", MISCREG_MDCR_EL3 },
545 { "ttbr0_el1", MISCREG_TTBR0_EL1 },
546 { "ttbr1_el1", MISCREG_TTBR1_EL1 },
547 { "tcr_el1", MISCREG_TCR_EL1 },
548 { "ttbr0_el2", MISCREG_TTBR0_EL2 },
549 { "tcr_el2", MISCREG_TCR_EL2 },
550 { "vttbr_el2", MISCREG_VTTBR_EL2 },
551 { "vtcr_el2", MISCREG_VTCR_EL2 },
552 { "ttbr0_el3", MISCREG_TTBR0_EL3 },
553 { "tcr_el3", MISCREG_TCR_EL3 },
554 { "dacr32_el2", MISCREG_DACR32_EL2 },
555 { "spsr_el1", MISCREG_SPSR_EL1 },
556 { "elr_el1", MISCREG_ELR_EL1 },
557 { "sp_el0", MISCREG_SP_EL0 },
558 { "spsel", MISCREG_SPSEL },
559 { "currentel", MISCREG_CURRENTEL },
560 { "nzcv", MISCREG_NZCV },
561 { "daif", MISCREG_DAIF },
562 { "fpcr", MISCREG_FPCR },
563 { "fpsr", MISCREG_FPSR },
564 { "dspsr_el0", MISCREG_DSPSR_EL0 },
565 { "dlr_el0", MISCREG_DLR_EL0 },
566 { "spsr_el2", MISCREG_SPSR_EL2 },
567 { "elr_el2", MISCREG_ELR_EL2 },
568 { "sp_el1", MISCREG_SP_EL1 },
569 { "spsr_irq", MISCREG_SPSR_IRQ_AA64 },
570 { "spsr_abt", MISCREG_SPSR_ABT_AA64 },
571 { "spsr_und", MISCREG_SPSR_UND_AA64 },
572 { "spsr_fiq", MISCREG_SPSR_FIQ_AA64 },
573 { "spsr_el3", MISCREG_SPSR_EL3 },
574 { "elr_el3", MISCREG_ELR_EL3 },
575 { "sp_el2", MISCREG_SP_EL2 },
576 { "afsr0_el1", MISCREG_AFSR0_EL1 },
577 { "afsr1_el1", MISCREG_AFSR1_EL1 },
578 { "esr_el1", MISCREG_ESR_EL1 },
579 { "ifsr32_el2", MISCREG_IFSR32_EL2 },
580 { "afsr0_el2", MISCREG_AFSR0_EL2 },
581 { "afsr1_el2", MISCREG_AFSR1_EL2 },
582 { "esr_el2", MISCREG_ESR_EL2 },
583 { "fpexc32_el2", MISCREG_FPEXC32_EL2 },
584 { "afsr0_el3", MISCREG_AFSR0_EL3 },
585 { "afsr1_el3", MISCREG_AFSR1_EL3 },
586 { "esr_el3", MISCREG_ESR_EL3 },
587 { "far_el1", MISCREG_FAR_EL1 },
588 { "far_el2", MISCREG_FAR_EL2 },
589 { "hpfar_el2", MISCREG_HPFAR_EL2 },
590 { "far_el3", MISCREG_FAR_EL3 },
591 { "ic_ialluis", MISCREG_IC_IALLUIS },
592 { "par_el1", MISCREG_PAR_EL1 },
593 { "ic_iallu", MISCREG_IC_IALLU },
594 { "dc_ivac_xt", MISCREG_DC_IVAC_Xt },
595 { "dc_isw_xt", MISCREG_DC_ISW_Xt },
596 { "at_s1e1r_xt", MISCREG_AT_S1E1R_Xt },
597 { "at_s1e1w_xt", MISCREG_AT_S1E1W_Xt },
598 { "at_s1e0r_xt", MISCREG_AT_S1E0R_Xt },
599 { "at_s1e0w_xt", MISCREG_AT_S1E0W_Xt },
600 { "dc_csw_xt", MISCREG_DC_CSW_Xt },
601 { "dc_cisw_xt", MISCREG_DC_CISW_Xt },
602 { "dc_zva_xt", MISCREG_DC_ZVA_Xt },
603 { "ic_ivau_xt", MISCREG_IC_IVAU_Xt },
604 { "dc_cvac_xt", MISCREG_DC_CVAC_Xt },
605 { "dc_cvau_xt", MISCREG_DC_CVAU_Xt },
606 { "dc_civac_xt", MISCREG_DC_CIVAC_Xt },
607 { "at_s1e2r_xt", MISCREG_AT_S1E2R_Xt },
608 { "at_s1e2w_xt", MISCREG_AT_S1E2W_Xt },
609 { "at_s12e1r_xt", MISCREG_AT_S12E1R_Xt },
610 { "at_s12e1w_xt", MISCREG_AT_S12E1W_Xt },
611 { "at_s12e0r_xt", MISCREG_AT_S12E0R_Xt },
612 { "at_s12e0w_xt", MISCREG_AT_S12E0W_Xt },
613 { "at_s1e3r_xt", MISCREG_AT_S1E3R_Xt },
614 { "at_s1e3w_xt", MISCREG_AT_S1E3W_Xt },
615 { "tlbi_vmalle1is", MISCREG_TLBI_VMALLE1IS },
616 { "tlbi_vae1is_xt", MISCREG_TLBI_VAE1IS_Xt },
617 { "tlbi_aside1is_xt", MISCREG_TLBI_ASIDE1IS_Xt },
618 { "tlbi_vaae1is_xt", MISCREG_TLBI_VAAE1IS_Xt },
619 { "tlbi_vale1is_xt", MISCREG_TLBI_VALE1IS_Xt },
620 { "tlbi_vaale1is_xt", MISCREG_TLBI_VAALE1IS_Xt },
621 { "tlbi_vmalle1", MISCREG_TLBI_VMALLE1 },
622 { "tlbi_vae1_xt", MISCREG_TLBI_VAE1_Xt },
623 { "tlbi_aside1_xt", MISCREG_TLBI_ASIDE1_Xt },
624 { "tlbi_vaae1_xt", MISCREG_TLBI_VAAE1_Xt },
625 { "tlbi_vale1_xt", MISCREG_TLBI_VALE1_Xt },
626 { "tlbi_vaale1_xt", MISCREG_TLBI_VAALE1_Xt },
627 { "tlbi_ipas2e1is_xt", MISCREG_TLBI_IPAS2E1IS_Xt },
628 { "tlbi_ipas2le1is_xt", MISCREG_TLBI_IPAS2LE1IS_Xt },
629 { "tlbi_alle2is", MISCREG_TLBI_ALLE2IS },
630 { "tlbi_vae2is_xt", MISCREG_TLBI_VAE2IS_Xt },
631 { "tlbi_alle1is", MISCREG_TLBI_ALLE1IS },
632 { "tlbi_vale2is_xt", MISCREG_TLBI_VALE2IS_Xt },
633 { "tlbi_vmalls12e1is", MISCREG_TLBI_VMALLS12E1IS },
634 { "tlbi_ipas2e1_xt", MISCREG_TLBI_IPAS2E1_Xt },
635 { "tlbi_ipas2le1_xt", MISCREG_TLBI_IPAS2LE1_Xt },
636 { "tlbi_alle2", MISCREG_TLBI_ALLE2 },
637 { "tlbi_vae2_xt", MISCREG_TLBI_VAE2_Xt },
638 { "tlbi_alle1", MISCREG_TLBI_ALLE1 },
639 { "tlbi_vale2_xt", MISCREG_TLBI_VALE2_Xt },
640 { "tlbi_vmalls12e1", MISCREG_TLBI_VMALLS12E1 },
641 { "tlbi_alle3is", MISCREG_TLBI_ALLE3IS },
642 { "tlbi_vae3is_xt", MISCREG_TLBI_VAE3IS_Xt },
643 { "tlbi_vale3is_xt", MISCREG_TLBI_VALE3IS_Xt },
644 { "tlbi_alle3", MISCREG_TLBI_ALLE3 },
645 { "tlbi_vae3_xt", MISCREG_TLBI_VAE3_Xt },
646 { "tlbi_vale3_xt", MISCREG_TLBI_VALE3_Xt },
647 { "pmintenset_el1", MISCREG_PMINTENSET_EL1 },
648 { "pmintenclr_el1", MISCREG_PMINTENCLR_EL1 },
649 { "pmcr_el0", MISCREG_PMCR_EL0 },
650 { "pmcntenset_el0", MISCREG_PMCNTENSET_EL0 },
651 { "pmcntenclr_el0", MISCREG_PMCNTENCLR_EL0 },
652 { "pmovsclr_el0", MISCREG_PMOVSCLR_EL0 },
653 { "pmswinc_el0", MISCREG_PMSWINC_EL0 },
654 { "pmselr_el0", MISCREG_PMSELR_EL0 },
655 { "pmceid0_el0", MISCREG_PMCEID0_EL0 },
656 { "pmceid1_el0", MISCREG_PMCEID1_EL0 },
657 { "pmccntr_el0", MISCREG_PMCCNTR_EL0 },
658 { "pmxevtyper_el0", MISCREG_PMXEVTYPER_EL0 },
659 { "pmccfiltr_el0", MISCREG_PMCCFILTR_EL0 },
660 { "pmxevcntr_el0", MISCREG_PMXEVCNTR_EL0 },
661 { "pmuserenr_el0", MISCREG_PMUSERENR_EL0 },
662 { "pmovsset_el0", MISCREG_PMOVSSET_EL0 },
663 { "mair_el1", MISCREG_MAIR_EL1 },
664 { "amair_el1", MISCREG_AMAIR_EL1 },
665 { "mair_el2", MISCREG_MAIR_EL2 },
666 { "amair_el2", MISCREG_AMAIR_EL2 },
667 { "mair_el3", MISCREG_MAIR_EL3 },
668 { "amair_el3", MISCREG_AMAIR_EL3 },
669 { "l2ctlr_el1", MISCREG_L2CTLR_EL1 },
670 { "l2ectlr_el1", MISCREG_L2ECTLR_EL1 },
671 { "vbar_el1", MISCREG_VBAR_EL1 },
672 { "rvbar_el1", MISCREG_RVBAR_EL1 },
673 { "isr_el1", MISCREG_ISR_EL1 },
674 { "vbar_el2", MISCREG_VBAR_EL2 },
675 { "rvbar_el2", MISCREG_RVBAR_EL2 },
676 { "vbar_el3", MISCREG_VBAR_EL3 },
677 { "rvbar_el3", MISCREG_RVBAR_EL3 },
678 { "rmr_el3", MISCREG_RMR_EL3 },
679 { "contextidr_el1", MISCREG_CONTEXTIDR_EL1 },
680 { "contextidr_el2", MISCREG_CONTEXTIDR_EL2 },
681 { "tpidr_el1", MISCREG_TPIDR_EL1 },
682 { "tpidr_el0", MISCREG_TPIDR_EL0 },
683 { "tpidrro_el0", MISCREG_TPIDRRO_EL0 },
684 { "tpidr_el2", MISCREG_TPIDR_EL2 },
685 { "tpidr_el3", MISCREG_TPIDR_EL3 },
686 { "cntkctl_el1", MISCREG_CNTKCTL_EL1 },
687 { "cntfrq_el0", MISCREG_CNTFRQ_EL0 },
688 { "cntpct_el0", MISCREG_CNTPCT_EL0 },
689 { "cntvct_el0", MISCREG_CNTVCT_EL0 },
690 { "cntp_tval_el0", MISCREG_CNTP_TVAL_EL0 },
691 { "cntp_ctl_el0", MISCREG_CNTP_CTL_EL0 },
692 { "cntp_cval_el0", MISCREG_CNTP_CVAL_EL0 },
693 { "cntv_tval_el0", MISCREG_CNTV_TVAL_EL0 },
694 { "cntv_ctl_el0", MISCREG_CNTV_CTL_EL0 },
695 { "cntv_cval_el0", MISCREG_CNTV_CVAL_EL0 },
696 { "pmevcntr0_el0", MISCREG_PMEVCNTR0_EL0 },
697 { "pmevcntr1_el0", MISCREG_PMEVCNTR1_EL0 },
698 { "pmevcntr2_el0", MISCREG_PMEVCNTR2_EL0 },
699 { "pmevcntr3_el0", MISCREG_PMEVCNTR3_EL0 },
700 { "pmevcntr4_el0", MISCREG_PMEVCNTR4_EL0 },
701 { "pmevcntr5_el0", MISCREG_PMEVCNTR5_EL0 },
702 { "pmevtyper0_el0", MISCREG_PMEVTYPER0_EL0 },
703 { "pmevtyper1_el0", MISCREG_PMEVTYPER1_EL0 },
704 { "pmevtyper2_el0", MISCREG_PMEVTYPER2_EL0 },
705 { "pmevtyper3_el0", MISCREG_PMEVTYPER3_EL0 },
706 { "pmevtyper4_el0", MISCREG_PMEVTYPER4_EL0 },
707 { "pmevtyper5_el0", MISCREG_PMEVTYPER5_EL0 },
708 { "cntvoff_el2", MISCREG_CNTVOFF_EL2 },
709 { "cnthctl_el2", MISCREG_CNTHCTL_EL2 },
710 { "cnthp_tval_el2", MISCREG_CNTHP_TVAL_EL2 },
711 { "cnthp_ctl_el2", MISCREG_CNTHP_CTL_EL2 },
712 { "cnthp_cval_el2", MISCREG_CNTHP_CVAL_EL2 },
713 { "cntps_tval_el1", MISCREG_CNTPS_TVAL_EL1 },
714 { "cntps_ctl_el1", MISCREG_CNTPS_CTL_EL1 },
715 { "cntps_cval_el1", MISCREG_CNTPS_CVAL_EL1 },
716 { "il1data0_el1", MISCREG_IL1DATA0_EL1 },
717 { "il1data1_el1", MISCREG_IL1DATA1_EL1 },
718 { "il1data2_el1", MISCREG_IL1DATA2_EL1 },
719 { "il1data3_el1", MISCREG_IL1DATA3_EL1 },
720 { "dl1data0_el1", MISCREG_DL1DATA0_EL1 },
721 { "dl1data1_el1", MISCREG_DL1DATA1_EL1 },
722 { "dl1data2_el1", MISCREG_DL1DATA2_EL1 },
723 { "dl1data3_el1", MISCREG_DL1DATA3_EL1 },
724 { "dl1data4_el1", MISCREG_DL1DATA4_EL1 },
725 { "l2actlr_el1", MISCREG_L2ACTLR_EL1 },
726 { "cpuactlr_el1", MISCREG_CPUACTLR_EL1 },
727 { "cpuectlr_el1", MISCREG_CPUECTLR_EL1 },
728 { "cpumerrsr_el1", MISCREG_CPUMERRSR_EL1 },
729 { "l2merrsr_el1", MISCREG_L2MERRSR_EL1 },
730 { "cbar_el1", MISCREG_CBAR_EL1 },
731 };
732
733 void
734 TarmacParserRecord::TarmacParserRecordEvent::process()
735 {
736 ostream &outs = Trace::output();
737
738 list<ParserRegEntry>::iterator it = destRegRecords.begin(),
739 end = destRegRecords.end();
740
741 std::vector<uint64_t> values;
742
743 for (; it != end; ++it) {
744 values.clear();
745 switch (it->type) {
746 case REG_R:
747 case REG_X:
748 values.push_back(thread->readIntReg(it->index));
749 break;
750 case REG_S:
751 if (instRecord.isetstate == ISET_A64) {
752 const ArmISA::VecRegContainer& vc = thread->readVecReg(
753 RegId(VecRegClass, it->index));
754 auto vv = vc.as<uint32_t>();
755 values.push_back(vv[0]);
756 } else {
757 const VecElem elem = thread->readVecElem(
758 RegId(VecElemClass,
759 it->index / NumVecElemPerNeonVecReg,
760 it->index % NumVecElemPerNeonVecReg));
761 values.push_back(elem);
762 }
763 break;
764 case REG_D:
765 if (instRecord.isetstate == ISET_A64) {
766 const ArmISA::VecRegContainer& vc = thread->readVecReg(
767 RegId(VecRegClass, it->index));
768 auto vv = vc.as<uint64_t>();
769 values.push_back(vv[0]);
770 } else {
771 const VecElem w0 = thread->readVecElem(
772 RegId(VecElemClass,
773 it->index / NumVecElemPerNeonVecReg,
774 it->index % NumVecElemPerNeonVecReg));
775 const VecElem w1 = thread->readVecElem(
776 RegId(VecElemClass,
777 (it->index + 1) / NumVecElemPerNeonVecReg,
778 (it->index + 1) % NumVecElemPerNeonVecReg));
779
780 values.push_back((uint64_t)(w1) << 32 | w0);
781 }
782 break;
783 case REG_P:
784 {
785 const ArmISA::VecPredRegContainer& pc =
786 thread->readVecPredReg(RegId(VecPredRegClass, it->index));
787 auto pv = pc.as<uint8_t>();
788 uint64_t p = 0;
789 for (int i = maxVectorLength * 8; i > 0; ) {
790 p = (p << 1) | pv[--i];
791 }
792 values.push_back(p);
793 }
794 break;
795 case REG_Q:
796 if (instRecord.isetstate == ISET_A64) {
797 const ArmISA::VecRegContainer& vc = thread->readVecReg(
798 RegId(VecRegClass, it->index));
799 auto vv = vc.as<uint64_t>();
800 values.push_back(vv[0]);
801 values.push_back(vv[1]);
802 } else {
803 const VecElem w0 = thread->readVecElem(
804 RegId(VecElemClass,
805 it->index / NumVecElemPerNeonVecReg,
806 it->index % NumVecElemPerNeonVecReg));
807 const VecElem w1 = thread->readVecElem(
808 RegId(VecElemClass,
809 (it->index + 1) / NumVecElemPerNeonVecReg,
810 (it->index + 1) % NumVecElemPerNeonVecReg));
811 const VecElem w2 = thread->readVecElem(
812 RegId(VecElemClass,
813 (it->index + 2) / NumVecElemPerNeonVecReg,
814 (it->index + 2) % NumVecElemPerNeonVecReg));
815 const VecElem w3 = thread->readVecElem(
816 RegId(VecElemClass,
817 (it->index + 3) / NumVecElemPerNeonVecReg,
818 (it->index + 3) % NumVecElemPerNeonVecReg));
819
820 values.push_back((uint64_t)(w1) << 32 | w0);
821 values.push_back((uint64_t)(w3) << 32 | w2);
822 }
823 break;
824 case REG_Z:
825 {
826 int8_t i = maxVectorLength;
827 const TheISA::VecRegContainer& vc = thread->readVecReg(
828 RegId(VecRegClass, it->index));
829 auto vv = vc.as<uint64_t>();
830 while (i > 0) {
831 values.push_back(vv[--i]);
832 }
833 }
834 break;
835 case REG_MISC:
836 if (it->index == MISCREG_CPSR) {
837 // Read condition codes from aliased integer regs
838 CPSR cpsr = thread->readMiscRegNoEffect(it->index);
839 cpsr.nz = thread->readCCReg(CCREG_NZ);
840 cpsr.c = thread->readCCReg(CCREG_C);
841 cpsr.v = thread->readCCReg(CCREG_V);
842 cpsr.ge = thread->readCCReg(CCREG_GE);
843 values.push_back(cpsr);
844 } else if (it->index == MISCREG_NZCV) {
845 CPSR cpsr = 0;
846 cpsr.nz = thread->readCCReg(CCREG_NZ);
847 cpsr.c = thread->readCCReg(CCREG_C);
848 cpsr.v = thread->readCCReg(CCREG_V);
849 values.push_back(cpsr);
850 } else if (it->index == MISCREG_FPCR) {
851 // Read FPSCR and extract FPCR value
852 FPSCR fpscr = thread->readMiscRegNoEffect(MISCREG_FPSCR);
853 const uint32_t ones = (uint32_t)(-1);
854 FPSCR fpcrMask = 0;
855 fpcrMask.ioe = ones;
856 fpcrMask.dze = ones;
857 fpcrMask.ofe = ones;
858 fpcrMask.ufe = ones;
859 fpcrMask.ixe = ones;
860 fpcrMask.ide = ones;
861 fpcrMask.len = ones;
862 fpcrMask.stride = ones;
863 fpcrMask.rMode = ones;
864 fpcrMask.fz = ones;
865 fpcrMask.dn = ones;
866 fpcrMask.ahp = ones;
867 values.push_back(fpscr & fpcrMask);
868 } else if (it->index == MISCREG_FPSR) {
869 // Read FPSCR and extract FPSR value
870 FPSCR fpscr = thread->readMiscRegNoEffect(MISCREG_FPSCR);
871 const uint32_t ones = (uint32_t)(-1);
872 FPSCR fpsrMask = 0;
873 fpsrMask.ioc = ones;
874 fpsrMask.dzc = ones;
875 fpsrMask.ofc = ones;
876 fpsrMask.ufc = ones;
877 fpsrMask.ixc = ones;
878 fpsrMask.idc = ones;
879 fpsrMask.qc = ones;
880 fpsrMask.v = ones;
881 fpsrMask.c = ones;
882 fpsrMask.z = ones;
883 fpsrMask.n = ones;
884 values.push_back(fpscr & fpsrMask);
885 } else {
886 values.push_back(thread->readMiscRegNoEffect(it->index));
887 }
888 break;
889 default:
890 panic("Unknown TARMAC trace record type!");
891 }
892
893 bool same = true;
894 if (values.size() != it->values.size()) same = false;
895
896 uint32_t size = values.size();
897 if (size > it->values.size())
898 size = it->values.size();
899
900 if (same) {
901 for (int i = 0; i < size; ++i) {
902 if (values[i] != it->values[i]) {
903 same = false;
904 break;
905 }
906 }
907 }
908
909 if (!same) {
910 if (!mismatch) {
911 TarmacParserRecord::printMismatchHeader(inst, pc);
912 mismatch = true;
913 }
914 outs << "diff> [" << it->repr << "] gem5: 0x" << hex;
915 for (auto v : values)
916 outs << setw(16) << setfill('0') << v;
917
918 outs << ", TARMAC: 0x" << hex;
919 for (auto v : it->values)
920 outs << setw(16) << setfill('0') << v;
921 outs << endl;
922 }
923 }
924 destRegRecords.clear();
925
926 if (mismatchOnPcOrOpcode && (parent.exitOnDiff ||
927 parent.exitOnInsnDiff))
928 exitSimLoop("a mismatch with the TARMAC trace has been detected "
929 "on PC or opcode", 1);
930 if (mismatch && parent.exitOnDiff)
931 exitSimLoop("a mismatch with the TARMAC trace has been detected "
932 "on data value", 1);
933 }
934
935 const char *
936 TarmacParserRecord::TarmacParserRecordEvent::description() const
937 {
938 return "TARMAC parser record event";
939 }
940
941
942 void
943 TarmacParserRecord::printMismatchHeader(const StaticInstPtr staticInst,
944 ArmISA::PCState pc)
945 {
946 ostream &outs = Trace::output();
947 outs << "\nMismatch between gem5 and TARMAC trace @ " << dec << curTick()
948 << " ticks\n"
949 << "[seq_num: " << dec << instRecord.seq_num
950 << ", opcode: 0x" << hex << (staticInst->machInst & 0xffffffff)
951 << ", PC: 0x" << pc.pc()
952 << ", disasm: " << staticInst->disassemble(pc.pc()) << "]"
953 << endl;
954 }
955
956 TarmacParserRecord::TarmacParserRecord(Tick _when, ThreadContext *_thread,
957 const StaticInstPtr _staticInst,
958 PCState _pc,
959 TarmacParser& _parent,
960 const StaticInstPtr _macroStaticInst)
961 : TarmacBaseRecord(_when, _thread, _staticInst,
962 _pc, _macroStaticInst),
963 parsingStarted(false), mismatch(false),
964 mismatchOnPcOrOpcode(false), parent(_parent)
965 {
966 memReq = std::make_shared<Request>();
967 if (maxVectorLength == 0) {
968 maxVectorLength = ArmStaticInst::getCurSveVecLen<uint64_t>(_thread);
969 }
970 }
971
972 void
973 TarmacParserRecord::dump()
974 {
975 ostream &outs = Trace::output();
976
977 uint64_t written_data = 0;
978 unsigned mem_flags = 3 | ArmISA::TLB::AllowUnaligned;
979
980 ISetState isetstate;
981
982 if (!staticInst->isMicroop() || staticInst->isLastMicroop()) {
983
984 if (parent.macroopInProgress && !staticInst->isLastMicroop()) {
985 // A microop faulted and it was not the last microop -> advance
986 // TARMAC trace to next instruction
987 advanceTrace();
988 }
989
990 parent.macroopInProgress = false;
991
992 auto arm_inst = static_cast<const ArmStaticInst*>(
993 staticInst.get()
994 );
995
996 while (advanceTrace()) {
997 switch (currRecordType) {
998
999 case TARMAC_INST:
1000 parsingStarted = true;
1001 if (pc.instAddr() != instRecord.addr) {
1002 if (!mismatch)
1003 printMismatchHeader(staticInst, pc);
1004 outs << "diff> [PC] gem5: 0x" << hex << pc.instAddr()
1005 << ", TARMAC: 0x" << instRecord.addr << endl;
1006 mismatch = true;
1007 mismatchOnPcOrOpcode = true;
1008 }
1009
1010 if (arm_inst->encoding() != instRecord.opcode) {
1011 if (!mismatch)
1012 printMismatchHeader(staticInst, pc);
1013 outs << "diff> [opcode] gem5: 0x" << hex
1014 << arm_inst->encoding()
1015 << ", TARMAC: 0x" << instRecord.opcode << endl;
1016 mismatch = true;
1017 mismatchOnPcOrOpcode = true;
1018 }
1019
1020 // Set the Instruction set state.
1021 isetstate = pcToISetState(pc);
1022
1023 if (instRecord.isetstate != isetstate &&
1024 isetstate != ISET_UNSUPPORTED) {
1025 if (!mismatch)
1026 printMismatchHeader(staticInst, pc);
1027 outs << "diff> [iset_state] gem5: "
1028 << iSetStateToStr(isetstate)
1029 << ", TARMAC: "
1030 << iSetStateToStr(instRecord.isetstate);
1031 mismatch = true;
1032 }
1033
1034 // TODO(Giacomo): add support for predicate and mode checking
1035 break;
1036
1037 case TARMAC_REG:
1038 destRegRecords.push_back(regRecord);
1039 break;
1040
1041 case TARMAC_MEM:
1042 if (!readMemNoEffect(memRecord.addr, (uint8_t*) &written_data,
1043 memRecord.size, mem_flags))
1044 break;
1045 if (written_data != memRecord.data) {
1046 if (!mismatch)
1047 printMismatchHeader(staticInst, pc);
1048 outs << "diff> [mem(0x" << hex << memRecord.addr
1049 << ")] gem5: 0x" << written_data
1050 << ", TARMAC: 0x" << memRecord.data
1051 << endl;
1052 }
1053 break;
1054
1055 case TARMAC_UNSUPPORTED:
1056 break;
1057
1058 default:
1059 panic("Unknown TARMAC trace record type!");
1060 }
1061 }
1062 // We are done with the current instruction, i.e. all the corresponding
1063 // entries in the TARMAC trace have been parsed
1064 if (destRegRecords.size()) {
1065 TarmacParserRecordEvent *event = new TarmacParserRecordEvent(
1066 parent, thread, staticInst, pc, mismatch,
1067 mismatchOnPcOrOpcode);
1068 mainEventQueue[0]->schedule(event, curTick());
1069 } else if (mismatchOnPcOrOpcode && (parent.exitOnDiff ||
1070 parent.exitOnInsnDiff)) {
1071 exitSimLoop("a mismatch with the TARMAC trace has been detected "
1072 "on PC or opcode", 1);
1073 }
1074 } else {
1075 parent.macroopInProgress = true;
1076 }
1077 }
1078
1079 bool
1080 TarmacParserRecord::advanceTrace()
1081 {
1082 ifstream& trace = parent.trace;
1083 trace >> hex; // All integer values are in hex base
1084
1085 if (buf[0] != 'I') {
1086 trace >> buf;
1087 if (trace.eof())
1088 return false;
1089 trace >> buf >> buf;
1090 if (parent.cpuId) {
1091 assert((buf[0] == 'c') && (buf[1] == 'p') && (buf[2] == 'u'));
1092 trace >> buf;
1093 }
1094 }
1095
1096 if (trace.eof())
1097 return false;
1098
1099 if (buf[0] == 'I') {
1100 // Instruction trace record
1101 if (parsingStarted)
1102 return false;
1103 currRecordType = TARMAC_INST;
1104 instRecord.taken = (buf[1] == 'T');
1105 trace >> buf;
1106 instRecord.seq_num = atoi(&buf[1]);
1107 trace >> instRecord.addr;
1108 char c = trace.peek();
1109 if (c == ':') {
1110 // Skip phys. address and _S/_NS suffix
1111 trace >> c >> buf;
1112 }
1113 trace >> instRecord.opcode;
1114 trace >> buf;
1115 switch (buf[0]) {
1116 case 'A':
1117 instRecord.isetstate = ISET_ARM;
1118 break;
1119 case 'T':
1120 instRecord.isetstate = ISET_THUMB;
1121 break;
1122 case 'O':
1123 instRecord.isetstate = ISET_A64;
1124 break;
1125 default:
1126 warn("Invalid TARMAC trace record (seq_num: %lld)",
1127 instRecord.seq_num);
1128 instRecord.isetstate = ISET_UNSUPPORTED;
1129 currRecordType = TARMAC_UNSUPPORTED;
1130 break;
1131 }
1132 trace.ignore(MaxLineLength, '\n');
1133 buf[0] = 0;
1134 } else if (buf[0] == 'R') {
1135 // Register trace record
1136 currRecordType = TARMAC_REG;
1137 regRecord.values.clear();
1138 trace >> buf;
1139 strcpy(regRecord.repr, buf);
1140 if (std::tolower(buf[0]) == 'r' && isdigit(buf[1])) {
1141 // R register
1142 regRecord.type = REG_R;
1143 int base_index = atoi(&buf[1]);
1144 char* pch = strchr(buf, '_');
1145 if (pch == NULL) {
1146 regRecord.index = INTREG_USR(base_index);
1147 } else {
1148 ++pch;
1149 if (strncmp(pch, "usr", 3) == 0)
1150 regRecord.index = INTREG_USR(base_index);
1151 else if (strncmp(pch, "fiq", 3) == 0)
1152 regRecord.index = INTREG_FIQ(base_index);
1153 else if (strncmp(pch, "irq", 3) == 0)
1154 regRecord.index = INTREG_IRQ(base_index);
1155 else if (strncmp(pch, "svc", 3) == 0)
1156 regRecord.index = INTREG_SVC(base_index);
1157 else if (strncmp(pch, "mon", 3) == 0)
1158 regRecord.index = INTREG_MON(base_index);
1159 else if (strncmp(pch, "abt", 3) == 0)
1160 regRecord.index = INTREG_ABT(base_index);
1161 else if (strncmp(pch, "und", 3) == 0)
1162 regRecord.index = INTREG_UND(base_index);
1163 else if (strncmp(pch, "hyp", 3) == 0)
1164 regRecord.index = INTREG_HYP(base_index);
1165 }
1166 } else if (std::tolower(buf[0]) == 'x' && isdigit(buf[1])) {
1167 // X register (A64)
1168 regRecord.type = REG_X;
1169 regRecord.index = atoi(&buf[1]);
1170 } else if (std::tolower(buf[0]) == 's' && isdigit(buf[1])) {
1171 // S register
1172 regRecord.type = REG_S;
1173 regRecord.index = atoi(&buf[1]);
1174 } else if (std::tolower(buf[0]) == 'd' && isdigit(buf[1])) {
1175 // D register
1176 regRecord.type = REG_D;
1177 regRecord.index = atoi(&buf[1]);
1178 } else if (std::tolower(buf[0]) == 'q' && isdigit(buf[1])) {
1179 // Q register
1180 regRecord.type = REG_Q;
1181 regRecord.index = atoi(&buf[1]);
1182 } else if (std::tolower(buf[0]) == 'z' && isdigit(buf[1])) {
1183 // Z (SVE vector) register
1184 regRecord.type = REG_Z;
1185 regRecord.index = atoi(&buf[1]);
1186 } else if (std::tolower(buf[0]) == 'p' && isdigit(buf[1])) {
1187 // P (SVE predicate) register
1188 regRecord.type = REG_P;
1189 regRecord.index = atoi(&buf[1]);
1190 } else if (strncmp(buf, "SP_EL", 5) == 0) {
1191 // A64 stack pointer
1192 regRecord.type = REG_X;
1193 regRecord.index = INTREG_SP0 + atoi(&buf[5]);
1194 } else if (miscRegMap.count(buf)) {
1195 // Misc. register
1196 regRecord.type = REG_MISC;
1197 regRecord.index = miscRegMap[buf];
1198 } else {
1199 // Try match with upper case name (misc. register)
1200 string reg_name = buf;
1201 transform(reg_name.begin(), reg_name.end(), reg_name.begin(),
1202 ::tolower);
1203 if (miscRegMap.count(reg_name.c_str())) {
1204 regRecord.type = REG_MISC;
1205 regRecord.index = miscRegMap[reg_name.c_str()];
1206 } else {
1207 warn("Unknown register in TARMAC trace (%s).\n", buf);
1208 currRecordType = TARMAC_UNSUPPORTED;
1209 trace.ignore(MaxLineLength, '\n');
1210 buf[0] = 0;
1211 return true;
1212 }
1213 }
1214 if (regRecord.type == REG_Q) {
1215 trace.ignore();
1216 trace.get(buf, 17);
1217 uint64_t hi = strtoull(buf, NULL, 16);
1218 trace.get(buf, 17);
1219 uint64_t lo = strtoull(buf, NULL, 16);
1220 regRecord.values.push_back(lo);
1221 regRecord.values.push_back(hi);
1222 } else if (regRecord.type == REG_Z) {
1223 regRecord.values.resize(maxVectorLength);
1224 for (uint8_t i = 0; i < maxVectorLength; ++i) {
1225 uint64_t v;
1226 trace >> v;
1227 char c;
1228 trace >> c;
1229 assert(c == '_');
1230
1231 uint64_t lsw = 0;
1232 trace >> lsw;
1233 v = (v << 32) | lsw;
1234 if (i < maxVectorLength - 1) trace >> c;
1235 regRecord.values[i] = v;
1236 }
1237 } else {
1238 // REG_P values are also parsed here
1239 uint64_t v;
1240 trace >> v;
1241 char c = trace.peek();
1242 if ((c == ':') || (c == '_')) {
1243 // 64-bit value with : or _ in the middle
1244 uint64_t lsw = 0;
1245 trace >> c >> lsw;
1246 v = (v << 32) | lsw;
1247 }
1248 regRecord.values.push_back(v);
1249 }
1250 trace.ignore(MaxLineLength, '\n');
1251 buf[0] = 0;
1252 } else if (buf[0] == 'M' && (parent.memWrCheck && buf[1] == 'W')) {
1253 currRecordType = TARMAC_MEM;
1254 memRecord.size = atoi(&buf[2]);
1255 trace >> memRecord.addr;
1256 char c = trace.peek();
1257 if (c == ':') {
1258 // Skip phys. address and _S/_NS suffix
1259 trace >> c >> buf;
1260 }
1261 uint64_t data = 0;
1262 trace >> data;
1263 c = trace.peek();
1264 if (c == '_') {
1265 // 64-bit value with _ in the middle
1266 uint64_t lsw = 0;
1267 trace >> c >> lsw;
1268 data = (data << 32) | lsw;
1269 }
1270 memRecord.data = data;
1271 trace.ignore(MaxLineLength, '\n');
1272 buf[0] = 0;
1273 } else {
1274 currRecordType = TARMAC_UNSUPPORTED;
1275 trace.ignore(MaxLineLength, '\n');
1276 buf[0] = 0;
1277 }
1278
1279 return true;
1280 }
1281
1282 bool
1283 TarmacParserRecord::readMemNoEffect(Addr addr, uint8_t *data, unsigned size,
1284 unsigned flags)
1285 {
1286 const RequestPtr &req = memReq;
1287 ArmISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
1288
1289 req->setVirt(addr, size, flags, thread->pcState().instAddr(),
1290 Request::funcRequestorId);
1291
1292 // Translate to physical address
1293 Fault fault = dtb->translateAtomic(req, thread, BaseTLB::Read);
1294
1295 // Ignore read if the address falls into the ignored range
1296 if (parent.ignoredAddrRange.contains(addr))
1297 return false;
1298
1299 // Now do the access
1300 if (fault == NoFault &&
1301 !req->getFlags().isSet(Request::NO_ACCESS)) {
1302 if (req->isLLSC() || req->isLocalAccess())
1303 // LLSCs and local accesses are ignored
1304 return false;
1305 // the translating proxy will perform the virtual to physical
1306 // translation again
1307 thread->getVirtProxy().readBlob(addr, data, size);
1308 } else {
1309 return false;
1310 }
1311
1312 if (fault != NoFault) {
1313 return false;
1314 }
1315
1316 return true;
1317 }
1318
1319 void
1320 TarmacParser::advanceTraceToStartPc()
1321 {
1322 char buf[TarmacParserRecord::MaxLineLength];
1323 Addr pc;
1324 int saved_offset;
1325
1326 trace >> hex; // All integer values are in hex base
1327
1328 while (true) {
1329 saved_offset = trace.tellg();
1330 trace >> buf >> buf >> buf;
1331 if (cpuId)
1332 trace >> buf;
1333 if (buf[0] == 'I') {
1334 trace >> buf >> pc;
1335 if (pc == startPc) {
1336 // Set file pointer to the beginning of this line
1337 trace.seekg(saved_offset, ios::beg);
1338 return;
1339 } else {
1340 trace.ignore(TarmacParserRecord::MaxLineLength, '\n');
1341 }
1342 } else {
1343 trace.ignore(TarmacParserRecord::MaxLineLength, '\n');
1344 }
1345 if (trace.eof())
1346 panic("End of TARMAC trace reached before start PC\n");
1347 }
1348 }
1349
1350 const char*
1351 TarmacParserRecord::iSetStateToStr(ISetState isetstate) const
1352 {
1353 switch (isetstate) {
1354 case ISET_ARM:
1355 return "ARM (A32)";
1356 case ISET_THUMB:
1357 return "Thumb (A32)";
1358 case ISET_A64:
1359 return "A64";
1360 default:
1361 return "UNSUPPORTED";
1362 }
1363 }
1364
1365 } // namespace Trace
1366
1367 Trace::TarmacParser *
1368 TarmacParserParams::create()
1369 {
1370 return new Trace::TarmacParser(this);
1371 }