src/arch/arm/tracers/tarmac_record_v8.hh

   1 /*
   2  * Copyright (c) 2017-2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Giacomo Travaglini
  38  */
  39
  40 /**
  41  * @file: The file contains the informations used to generate records
  42  *        for ARMv8 cores.
  43  */
  44
  45 #ifndef __ARCH_ARM_TRACERS_TARMAC_RECORD_V8_HH__
  46 #define __ARCH_ARM_TRACERS_TARMAC_RECORD_V8_HH__
  47
  48 #include "tarmac_record.hh"
  49
  50 namespace Trace {
  51
  52 /**
  53  * TarmacTracer record for ARMv8 CPUs:
  54  * The record is adding some data to the base TarmacTracer
  55  * record.
  56  */
  57 class TarmacTracerRecordV8 : public TarmacTracerRecord
  58 {
  59   public:
  60
  61     /**
  62      * General data shared by all v8 entries
  63      */
  64     struct TraceEntryV8
  65     {
  66       public:
  67         TraceEntryV8(std::string _cpuName)
  68           : cpuName(_cpuName)
  69         {}
  70
  71       protected:
  72         std::string cpuName;
  73     };
  74
  75     /**
  76      * Instruction entry for v8 records
  77      */
  78     struct TraceInstEntryV8: public TraceInstEntry, TraceEntryV8
  79     {
  80       public:
  81         TraceInstEntryV8(const TarmacContext& tarmCtx, bool predicate);
  82
  83         virtual void print(std::ostream& outs,
  84                            int verbosity = 0,
  85                            const std::string &prefix = "") const override;
  86
  87       protected:
  88         Addr paddr;
  89         bool paddrValid;
  90     };
  91
  92     /**
  93      * Register entry for v8 records
  94      */
  95     struct TraceRegEntryV8: public TraceRegEntry, TraceEntryV8
  96     {
  97       public:
  98         TraceRegEntryV8(const TarmacContext& tarmCtx, const RegId& reg);
  99
 100         virtual void print(std::ostream& outs,
 101                            int verbosity = 0,
 102                            const std::string &prefix = "") const override;
 103
 104       protected:
 105         void updateInt(const TarmacContext& tarmCtx,
 106                        RegIndex regRelIdx) override;
 107
 108         void updateMisc(const TarmacContext& tarmCtx,
 109                         RegIndex regRelIdx) override;
 110
 111         void updateVec(const TarmacContext& tarmCtx,
 112                        RegIndex regRelIdx) override;
 113
 114         void updatePred(const TarmacContext& tarmCtx,
 115                         RegIndex regRelIdx) override;
 116
 117         /**
 118          * Returning a string which contains the formatted
 119          * register value: transformed in hex, 0 padded or/and
 120          * split in chunks separated by underscores in case of
 121          * vector register.
 122          * @return str formatted string
 123          */
 124         std::string formatReg() const;
 125
 126         /** Size in bits of arch register */
 127         uint16_t regWidth;
 128     };
 129
 130     /**
 131      * Memory Entry for V8
 132      */
 133     struct TraceMemEntryV8: public TraceMemEntry, TraceEntryV8
 134     {
 135       public:
 136         TraceMemEntryV8(const TarmacContext& tarmCtx,
 137                         uint8_t _size, Addr _addr, uint64_t _data);
 138
 139         virtual void print(std::ostream& outs,
 140                            int verbosity = 0,
 141                            const std::string &prefix = "") const override;
 142
 143       protected:
 144         Addr paddr;
 145     };
 146
 147   public:
 148     TarmacTracerRecordV8(Tick _when, ThreadContext *_thread,
 149                          const StaticInstPtr _staticInst, ArmISA::PCState _pc,
 150                          TarmacTracer& _parent,
 151                          const StaticInstPtr _macroStaticInst = NULL)
 152       : TarmacTracerRecord(_when, _thread, _staticInst, _pc,
 153                            _parent, _macroStaticInst)
 154     {}
 155
 156   protected:
 157     /** Generates an Entry for the executed instruction. */
 158     void addInstEntry(std::vector<InstPtr>& queue, const TarmacContext& ptr);
 159
 160     /** Generates an Entry for every memory access triggered */
 161     void addMemEntry(std::vector<MemPtr>& queue, const TarmacContext& ptr);
 162
 163     /** Generate a Record for every register being written */
 164     void addRegEntry(std::vector<RegPtr>& queue, const TarmacContext& ptr);
 165 };
 166
 167 } // namespace Trace
 168
 169 #endif // __ARCH_ARM_TRACERS_TARMAC_RECORD_V8_HH__