src/arch/arm/types.hh

   1 /*
   2  * Copyright (c) 2007-2008 The Florida State University
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Stephen Hines
  29  */
  30
  31 #ifndef __ARCH_ARM_TYPES_HH__
  32 #define __ARCH_ARM_TYPES_HH__
  33
  34 #include "base/bitunion.hh"
  35 #include "base/types.hh"
  36
  37 namespace ArmISA
  38 {
  39     typedef uint32_t MachInst;
  40
  41     BitUnion64(ExtMachInst)
  42         // Made up bitfields that make life easier.
  43         Bitfield<33>     sevenAndFour;
  44         Bitfield<32>     isMisc;
  45
  46         // All the different types of opcode fields.
  47         Bitfield<27, 25> encoding;
  48         Bitfield<24, 21> opcode;
  49         Bitfield<24, 20> mediaOpcode;
  50         Bitfield<24>     opcode24;
  51         Bitfield<23, 20> opcode23_20;
  52         Bitfield<23, 21> opcode23_21;
  53         Bitfield<22>     opcode22;
  54         Bitfield<19>     opcode19;
  55         Bitfield<15, 12> opcode15_12;
  56         Bitfield<15>     opcode15;
  57         Bitfield<7,  4>  miscOpcode;
  58         Bitfield<7>      opcode7;
  59         Bitfield<4>      opcode4;
  60
  61         Bitfield<31, 28> condCode;
  62         Bitfield<20>     sField;
  63         Bitfield<19, 16> rn;
  64         Bitfield<15, 12> rd;
  65         Bitfield<11, 7>  shiftSize;
  66         Bitfield<6,  5>  shift;
  67         Bitfield<3,  0>  rm;
  68
  69         Bitfield<11, 8>  rs;
  70
  71         SubBitUnion(puswl, 24, 20)
  72             Bitfield<24> prepost;
  73             Bitfield<23> up;
  74             Bitfield<22> psruser;
  75             Bitfield<21> writeback;
  76             Bitfield<20> loadOp;
  77         EndSubBitUnion(puswl)
  78
  79         Bitfield<24, 20> pubwl;
  80
  81         Bitfield<7, 0> imm;
  82
  83         Bitfield<11, 8>  rotate;
  84
  85         Bitfield<11, 0>  immed11_0;
  86         Bitfield<7,  0>  immed7_0;
  87
  88         Bitfield<11, 8>  immedHi11_8;
  89         Bitfield<3,  0>  immedLo3_0;
  90
  91         Bitfield<15, 0>  regList;
  92
  93         Bitfield<23, 0>  offset;
  94
  95         Bitfield<23, 0>  immed23_0;
  96
  97         Bitfield<11, 8>  cpNum;
  98         Bitfield<18, 16> fn;
  99         Bitfield<14, 12> fd;
 100         Bitfield<3>      fpRegImm;
 101         Bitfield<3,  0>  fm;
 102         Bitfield<2,  0>  fpImm;
 103         Bitfield<24, 20> punwl;
 104
 105         Bitfield<7,  0>  m5Func;
 106     EndBitUnion(ExtMachInst)
 107
 108     // Shift types for ARM instructions
 109     enum ArmShiftType {
 110         LSL = 0,
 111         LSR,
 112         ASR,
 113         ROR
 114     };
 115
 116     typedef uint64_t LargestRead;
 117     // Need to use 64 bits to make sure that read requests get handled properly
 118
 119     typedef int RegContextParam;
 120     typedef int RegContextVal;
 121
 122     //used in FP convert & round function
 123     enum ConvertType{
 124         SINGLE_TO_DOUBLE,
 125         SINGLE_TO_WORD,
 126         SINGLE_TO_LONG,
 127
 128         DOUBLE_TO_SINGLE,
 129         DOUBLE_TO_WORD,
 130         DOUBLE_TO_LONG,
 131
 132         LONG_TO_SINGLE,
 133         LONG_TO_DOUBLE,
 134         LONG_TO_WORD,
 135         LONG_TO_PS,
 136
 137         WORD_TO_SINGLE,
 138         WORD_TO_DOUBLE,
 139         WORD_TO_LONG,
 140         WORD_TO_PS,
 141
 142         PL_TO_SINGLE,
 143         PU_TO_SINGLE
 144     };
 145
 146     //used in FP convert & round function
 147     enum RoundMode{
 148         RND_ZERO,
 149         RND_DOWN,
 150         RND_UP,
 151         RND_NEAREST
 152     };
 153
 154     enum OperatingMode {
 155         MODE_USER = 16,
 156         MODE_FIQ = 17,
 157         MODE_IRQ = 18,
 158         MODE_SVC = 19,
 159         MODE_ABORT = 23,
 160         MODE_UNDEFINED = 27,
 161         MODE_SYSTEM = 31
 162     };
 163
 164     struct CoreSpecific {
 165         // Empty for now on the ARM
 166     };
 167
 168 } // namespace ArmISA
 169
 170 #endif