2 * Copyright (c) 2010 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Stephen Hines
43 #ifndef __ARCH_ARM_TYPES_HH__
44 #define __ARCH_ARM_TYPES_HH__
46 #include "arch/generic/types.hh"
47 #include "base/bitunion.hh"
48 #include "base/hashmap.hh"
49 #include "base/misc.hh"
50 #include "base/types.hh"
51 #include "debug/Decoder.hh"
55 typedef uint32_t MachInst;
58 /* Note that the split (cond, mask) below is not as in ARM ARM.
59 * But it is more convenient for simulation. The condition
60 * is always the concatenation of the top 3 bits and the next bit,
61 * which applies when one of the bottom 4 bits is set.
62 * Refer to predecoder.cc for the use case.
66 // Bitfields for moving to/from CPSR
68 Bitfield<1, 0> bottom2;
72 BitUnion64(ExtMachInst)
74 Bitfield<55, 48> itstate;
75 Bitfield<55, 52> itstateCond;
76 Bitfield<51, 48> itstateMask;
79 Bitfield<41, 40> fpscrStride;
80 Bitfield<39, 37> fpscrLen;
82 // Bitfields to select mode.
84 Bitfield<35> bigThumb;
86 // Made up bitfields that make life easier.
87 Bitfield<33> sevenAndFour;
92 // All the different types of opcode fields.
93 Bitfield<27, 25> encoding;
95 Bitfield<24, 21> opcode;
96 Bitfield<24, 20> mediaOpcode;
97 Bitfield<24> opcode24;
98 Bitfield<24, 23> opcode24_23;
99 Bitfield<23, 20> opcode23_20;
100 Bitfield<23, 21> opcode23_21;
101 Bitfield<20> opcode20;
102 Bitfield<22> opcode22;
103 Bitfield<19, 16> opcode19_16;
104 Bitfield<19> opcode19;
105 Bitfield<18> opcode18;
106 Bitfield<15, 12> opcode15_12;
107 Bitfield<15> opcode15;
108 Bitfield<7, 4> miscOpcode;
114 Bitfield<31, 28> condCode;
119 Bitfield<11, 7> shiftSize;
120 Bitfield<6, 5> shift;
125 SubBitUnion(puswl, 24, 20)
126 Bitfield<24> prepost;
128 Bitfield<22> psruser;
129 Bitfield<21> writeback;
131 EndSubBitUnion(puswl)
133 Bitfield<24, 20> pubwl;
137 Bitfield<11, 8> rotate;
139 Bitfield<11, 0> immed11_0;
140 Bitfield<7, 0> immed7_0;
142 Bitfield<11, 8> immedHi11_8;
143 Bitfield<3, 0> immedLo3_0;
145 Bitfield<15, 0> regList;
147 Bitfield<23, 0> offset;
149 Bitfield<23, 0> immed23_0;
151 Bitfield<11, 8> cpNum;
154 Bitfield<3> fpRegImm;
156 Bitfield<2, 0> fpImm;
157 Bitfield<24, 20> punwl;
159 Bitfield<15, 8> m5Func;
161 // 16 bit thumb bitfields
162 Bitfield<15, 13> topcode15_13;
163 Bitfield<13, 11> topcode13_11;
164 Bitfield<12, 11> topcode12_11;
165 Bitfield<12, 10> topcode12_10;
166 Bitfield<11, 9> topcode11_9;
167 Bitfield<11, 8> topcode11_8;
168 Bitfield<10, 9> topcode10_9;
169 Bitfield<10, 8> topcode10_8;
170 Bitfield<9, 6> topcode9_6;
171 Bitfield<7> topcode7;
172 Bitfield<7, 6> topcode7_6;
173 Bitfield<7, 5> topcode7_5;
174 Bitfield<7, 4> topcode7_4;
175 Bitfield<3, 0> topcode3_0;
177 // 32 bit thumb bitfields
178 Bitfield<28, 27> htopcode12_11;
179 Bitfield<26, 25> htopcode10_9;
180 Bitfield<25> htopcode9;
181 Bitfield<25, 24> htopcode9_8;
182 Bitfield<25, 21> htopcode9_5;
183 Bitfield<25, 20> htopcode9_4;
184 Bitfield<24> htopcode8;
185 Bitfield<24, 23> htopcode8_7;
186 Bitfield<24, 22> htopcode8_6;
187 Bitfield<24, 21> htopcode8_5;
188 Bitfield<23> htopcode7;
189 Bitfield<23, 21> htopcode7_5;
190 Bitfield<22> htopcode6;
191 Bitfield<22, 21> htopcode6_5;
192 Bitfield<21, 20> htopcode5_4;
193 Bitfield<20> htopcode4;
195 Bitfield<19, 16> htrn;
198 Bitfield<15> ltopcode15;
199 Bitfield<11, 8> ltopcode11_8;
200 Bitfield<7, 6> ltopcode7_6;
201 Bitfield<7, 4> ltopcode7_4;
202 Bitfield<4> ltopcode4;
204 Bitfield<11, 8> ltrd;
205 Bitfield<11, 8> ltcoproc;
206 EndBitUnion(ExtMachInst)
208 class PCState : public GenericISA::UPCState<MachInst>
212 typedef GenericISA::UPCState<MachInst> Base;
216 JazelleBit = (1 << 1)
221 uint8_t _nextItstate;
224 PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0)
231 npc(val + (thumb() ? 2 : 4));
234 PCState(Addr val) : flags(0), nextFlags(0), _itstate(0), _nextItstate(0)
240 return flags & ThumbBit;
255 return nextFlags & ThumbBit;
262 nextFlags |= ThumbBit;
264 nextFlags &= ~ThumbBit;
267 void size(uint8_t s) { _size = s; }
268 uint8_t size() const { return _size; }
273 return ((this->pc() + this->size()) != this->npc());
280 return flags & JazelleBit;
289 flags &= ~JazelleBit;
295 return nextFlags & JazelleBit;
299 nextJazelle(bool val)
302 nextFlags |= JazelleBit;
304 nextFlags &= ~JazelleBit;
314 itstate(uint8_t value)
326 nextItstate(uint8_t value)
328 _nextItstate = value;
336 npc(pc() + (thumb() ? 2 : 4));
339 _itstate = _nextItstate;
341 } else if (_itstate) {
342 ITSTATE it = _itstate;
343 uint8_t cond_mask = it.mask;
344 uint8_t thumb_cond = it.cond;
345 DPRINTF(Decoder, "Advancing ITSTATE from %#x,%#x.\n",
346 thumb_cond, cond_mask);
348 uint8_t new_bit = bits(cond_mask, 4);
349 cond_mask &= mask(4);
353 replaceBits(thumb_cond, 0, new_bit);
354 DPRINTF(Decoder, "Advancing ITSTATE to %#x,%#x.\n",
355 thumb_cond, cond_mask);
357 it.cond = thumb_cond;
373 return pc() + (thumb() ? 4 : 8);
377 instNPC(uint32_t val)
379 npc(val &~ mask(nextThumb() ? 1 : 2));
388 // Perform an interworking branch.
390 instIWNPC(uint32_t val)
392 bool thumbEE = (thumb() && jazelle());
396 if (bits(newPC, 0)) {
397 newPC = newPC & ~mask(1);
398 } // else we have a bad interworking address; do not call
399 // panic() since the instruction could be executed
402 if (bits(newPC, 0)) {
404 newPC = newPC & ~mask(1);
405 } else if (!bits(newPC, 1)) {
408 // This state is UNPREDICTABLE in the ARM architecture
409 // The easy thing to do is just mask off the bit and
410 // stay in the current mode, so we'll do that.
417 // Perform an interworking branch in ARM mode, a regular branch
420 instAIWNPC(uint32_t val)
422 if (!thumb() && !jazelle())
429 operator == (const PCState &opc) const
431 return Base::operator == (opc) &&
432 flags == opc.flags && nextFlags == opc.nextFlags &&
433 _itstate == opc._itstate && _nextItstate == opc._nextItstate;
437 operator != (const PCState &opc) const
439 return !(*this == opc);
443 serialize(std::ostream &os)
446 SERIALIZE_SCALAR(flags);
447 SERIALIZE_SCALAR(_size);
448 SERIALIZE_SCALAR(nextFlags);
449 SERIALIZE_SCALAR(_itstate);
450 SERIALIZE_SCALAR(_nextItstate);
454 unserialize(Checkpoint *cp, const std::string §ion)
456 Base::unserialize(cp, section);
457 UNSERIALIZE_SCALAR(flags);
458 UNSERIALIZE_SCALAR(_size);
459 UNSERIALIZE_SCALAR(nextFlags);
460 UNSERIALIZE_SCALAR(_itstate);
461 UNSERIALIZE_SCALAR(_nextItstate);
465 // Shift types for ARM instructions
473 typedef uint64_t LargestRead;
474 // Need to use 64 bits to make sure that read requests get handled properly
476 typedef int RegContextParam;
477 typedef int RegContextVal;
479 //used in FP convert & round function
503 //used in FP convert & round function
520 MODE_MAXMODE = MODE_SYSTEM
524 badMode(OperatingMode mode)
541 } // namespace ArmISA
543 __hash_namespace_begin
545 struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
546 size_t operator()(const ArmISA::ExtMachInst &emi) const {
547 return hash<uint32_t>::operator()((uint32_t)emi);