src/arch/arm/types.hh

   1 /*
   2  * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2007-2008 The Florida State University
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Stephen Hines
  41  */
  42
  43 #ifndef __ARCH_ARM_TYPES_HH__
  44 #define __ARCH_ARM_TYPES_HH__
  45
  46 #include "arch/generic/types.hh"
  47 #include "base/bitunion.hh"
  48 #include "base/logging.hh"
  49 #include "base/types.hh"
  50 #include "debug/Decoder.hh"
  51
  52 namespace ArmISA
  53 {
  54     typedef uint32_t MachInst;
  55
  56     BitUnion8(ITSTATE)
  57         /* Note that the split (cond, mask) below is not as in ARM ARM.
  58          * But it is more convenient for simulation. The condition
  59          * is always the concatenation of the top 3 bits and the next bit,
  60          * which applies when one of the bottom 4 bits is set.
  61          * Refer to predecoder.cc for the use case.
  62          */
  63         Bitfield<7, 4> cond;
  64         Bitfield<3, 0> mask;
  65         // Bitfields for moving to/from CPSR
  66         Bitfield<7, 2> top6;
  67         Bitfield<1, 0> bottom2;
  68     EndBitUnion(ITSTATE)
  69
  70     BitUnion64(ExtMachInst)
  71         // Decoder state
  72         Bitfield<63, 62> decoderFault; // See DecoderFault
  73         Bitfield<61> illegalExecution;
  74
  75         // SVE vector length, encoded in the same format as the ZCR_EL<x>.LEN
  76         // bitfields
  77         Bitfield<59, 56> sveLen;
  78
  79         // ITSTATE bits
  80         Bitfield<55, 48> itstate;
  81         Bitfield<55, 52> itstateCond;
  82         Bitfield<51, 48> itstateMask;
  83
  84         // FPSCR fields
  85         Bitfield<41, 40> fpscrStride;
  86         Bitfield<39, 37> fpscrLen;
  87
  88         // Bitfields to select mode.
  89         Bitfield<36>     thumb;
  90         Bitfield<35>     bigThumb;
  91         Bitfield<34>     aarch64;
  92
  93         // Made up bitfields that make life easier.
  94         Bitfield<33>     sevenAndFour;
  95         Bitfield<32>     isMisc;
  96
  97         uint32_t         instBits;
  98
  99         // All the different types of opcode fields.
 100         Bitfield<27, 25> encoding;
 101         Bitfield<25>     useImm;
 102         Bitfield<24, 21> opcode;
 103         Bitfield<24, 20> mediaOpcode;
 104         Bitfield<24>     opcode24;
 105         Bitfield<24, 23> opcode24_23;
 106         Bitfield<23, 20> opcode23_20;
 107         Bitfield<23, 21> opcode23_21;
 108         Bitfield<20>     opcode20;
 109         Bitfield<22>     opcode22;
 110         Bitfield<19, 16> opcode19_16;
 111         Bitfield<19>     opcode19;
 112         Bitfield<18>     opcode18;
 113         Bitfield<15, 12> opcode15_12;
 114         Bitfield<15>     opcode15;
 115         Bitfield<7,  4>  miscOpcode;
 116         Bitfield<7,5>    opc2;
 117         Bitfield<7>      opcode7;
 118         Bitfield<6>      opcode6;
 119         Bitfield<4>      opcode4;
 120
 121         Bitfield<31, 28> condCode;
 122         Bitfield<20>     sField;
 123         Bitfield<19, 16> rn;
 124         Bitfield<15, 12> rd;
 125         Bitfield<15, 12> rt;
 126         Bitfield<11, 7>  shiftSize;
 127         Bitfield<6,  5>  shift;
 128         Bitfield<3,  0>  rm;
 129
 130         Bitfield<11, 8>  rs;
 131
 132         SubBitUnion(puswl, 24, 20)
 133             Bitfield<24> prepost;
 134             Bitfield<23> up;
 135             Bitfield<22> psruser;
 136             Bitfield<21> writeback;
 137             Bitfield<20> loadOp;
 138         EndSubBitUnion(puswl)
 139
 140         Bitfield<24, 20> pubwl;
 141
 142         Bitfield<7, 0> imm;
 143
 144         Bitfield<11, 8>  rotate;
 145
 146         Bitfield<11, 0>  immed11_0;
 147         Bitfield<7,  0>  immed7_0;
 148
 149         Bitfield<11, 8>  immedHi11_8;
 150         Bitfield<3,  0>  immedLo3_0;
 151
 152         Bitfield<15, 0>  regList;
 153
 154         Bitfield<23, 0>  offset;
 155
 156         Bitfield<23, 0>  immed23_0;
 157
 158         Bitfield<11, 8>  cpNum;
 159         Bitfield<18, 16> fn;
 160         Bitfield<14, 12> fd;
 161         Bitfield<3>      fpRegImm;
 162         Bitfield<3,  0>  fm;
 163         Bitfield<2,  0>  fpImm;
 164         Bitfield<24, 20> punwl;
 165
 166         Bitfield<15,  8>  m5Func;
 167
 168         // 16 bit thumb bitfields
 169         Bitfield<15, 13> topcode15_13;
 170         Bitfield<13, 11> topcode13_11;
 171         Bitfield<12, 11> topcode12_11;
 172         Bitfield<12, 10> topcode12_10;
 173         Bitfield<11, 9>  topcode11_9;
 174         Bitfield<11, 8>  topcode11_8;
 175         Bitfield<10, 9>  topcode10_9;
 176         Bitfield<10, 8>  topcode10_8;
 177         Bitfield<9,  6>  topcode9_6;
 178         Bitfield<7>      topcode7;
 179         Bitfield<7, 6>   topcode7_6;
 180         Bitfield<7, 5>   topcode7_5;
 181         Bitfield<7, 4>   topcode7_4;
 182         Bitfield<3, 0>   topcode3_0;
 183
 184         // 32 bit thumb bitfields
 185         Bitfield<28, 27> htopcode12_11;
 186         Bitfield<26, 25> htopcode10_9;
 187         Bitfield<25>     htopcode9;
 188         Bitfield<25, 24> htopcode9_8;
 189         Bitfield<25, 21> htopcode9_5;
 190         Bitfield<25, 20> htopcode9_4;
 191         Bitfield<24>     htopcode8;
 192         Bitfield<24, 23> htopcode8_7;
 193         Bitfield<24, 22> htopcode8_6;
 194         Bitfield<24, 21> htopcode8_5;
 195         Bitfield<23>     htopcode7;
 196         Bitfield<23, 21> htopcode7_5;
 197         Bitfield<22>     htopcode6;
 198         Bitfield<22, 21> htopcode6_5;
 199         Bitfield<21, 20> htopcode5_4;
 200         Bitfield<20>     htopcode4;
 201
 202         Bitfield<19, 16> htrn;
 203         Bitfield<20>     hts;
 204
 205         Bitfield<15>     ltopcode15;
 206         Bitfield<11, 8>  ltopcode11_8;
 207         Bitfield<7,  6>  ltopcode7_6;
 208         Bitfield<7,  4>  ltopcode7_4;
 209         Bitfield<4>      ltopcode4;
 210
 211         Bitfield<11, 8>  ltrd;
 212         Bitfield<11, 8>  ltcoproc;
 213     EndBitUnion(ExtMachInst)
 214
 215     class PCState : public GenericISA::UPCState<MachInst>
 216     {
 217       protected:
 218
 219         typedef GenericISA::UPCState<MachInst> Base;
 220
 221         enum FlagBits {
 222             ThumbBit = (1 << 0),
 223             JazelleBit = (1 << 1),
 224             AArch64Bit = (1 << 2)
 225         };
 226
 227         uint8_t flags;
 228         uint8_t nextFlags;
 229         uint8_t _itstate;
 230         uint8_t _nextItstate;
 231         uint8_t _size;
 232         bool _illegalExec;
 233       public:
 234         PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0),
 235                     _size(0), _illegalExec(false)
 236         {}
 237
 238         void
 239         set(Addr val)
 240         {
 241             Base::set(val);
 242             npc(val + (thumb() ? 2 : 4));
 243         }
 244
 245         PCState(Addr val) : flags(0), nextFlags(0), _itstate(0),
 246                             _nextItstate(0), _size(0), _illegalExec(false)
 247         { set(val); }
 248
 249         bool
 250         illegalExec() const
 251         {
 252             return _illegalExec;
 253         }
 254
 255         void
 256         illegalExec(bool val)
 257         {
 258             _illegalExec = val;
 259         }
 260
 261         bool
 262         thumb() const
 263         {
 264             return flags & ThumbBit;
 265         }
 266
 267         void
 268         thumb(bool val)
 269         {
 270             if (val)
 271                 flags |= ThumbBit;
 272             else
 273                 flags &= ~ThumbBit;
 274         }
 275
 276         bool
 277         nextThumb() const
 278         {
 279             return nextFlags & ThumbBit;
 280         }
 281
 282         void
 283         nextThumb(bool val)
 284         {
 285             if (val)
 286                 nextFlags |= ThumbBit;
 287             else
 288                 nextFlags &= ~ThumbBit;
 289         }
 290
 291         void size(uint8_t s) { _size = s; }
 292         uint8_t size() const { return _size; }
 293
 294         bool
 295         branching() const
 296         {
 297             return ((this->pc() + this->size()) != this->npc());
 298         }
 299
 300
 301         bool
 302         jazelle() const
 303         {
 304             return flags & JazelleBit;
 305         }
 306
 307         void
 308         jazelle(bool val)
 309         {
 310             if (val)
 311                 flags |= JazelleBit;
 312             else
 313                 flags &= ~JazelleBit;
 314         }
 315
 316         bool
 317         nextJazelle() const
 318         {
 319             return nextFlags & JazelleBit;
 320         }
 321
 322         void
 323         nextJazelle(bool val)
 324         {
 325             if (val)
 326                 nextFlags |= JazelleBit;
 327             else
 328                 nextFlags &= ~JazelleBit;
 329         }
 330
 331         bool
 332         aarch64() const
 333         {
 334             return flags & AArch64Bit;
 335         }
 336
 337         void
 338         aarch64(bool val)
 339         {
 340             if (val)
 341                 flags |= AArch64Bit;
 342             else
 343                 flags &= ~AArch64Bit;
 344         }
 345
 346         bool
 347         nextAArch64() const
 348         {
 349             return nextFlags & AArch64Bit;
 350         }
 351
 352         void
 353         nextAArch64(bool val)
 354         {
 355             if (val)
 356                 nextFlags |= AArch64Bit;
 357             else
 358                 nextFlags &= ~AArch64Bit;
 359         }
 360
 361
 362         uint8_t
 363         itstate() const
 364         {
 365             return _itstate;
 366         }
 367
 368         void
 369         itstate(uint8_t value)
 370         {
 371             _itstate = value;
 372         }
 373
 374         uint8_t
 375         nextItstate() const
 376         {
 377             return _nextItstate;
 378         }
 379
 380         void
 381         nextItstate(uint8_t value)
 382         {
 383             _nextItstate = value;
 384         }
 385
 386         void
 387         advance()
 388         {
 389             Base::advance();
 390             flags = nextFlags;
 391             npc(pc() + (thumb() ? 2 : 4));
 392
 393             if (_nextItstate) {
 394                 _itstate = _nextItstate;
 395                 _nextItstate = 0;
 396             } else if (_itstate) {
 397                 ITSTATE it = _itstate;
 398                 uint8_t cond_mask = it.mask;
 399                 uint8_t thumb_cond = it.cond;
 400                 DPRINTF(Decoder, "Advancing ITSTATE from %#x,%#x.\n",
 401                         thumb_cond, cond_mask);
 402                 cond_mask <<= 1;
 403                 uint8_t new_bit = bits(cond_mask, 4);
 404                 cond_mask &= mask(4);
 405                 if (cond_mask == 0)
 406                     thumb_cond = 0;
 407                 else
 408                     replaceBits(thumb_cond, 0, new_bit);
 409                 DPRINTF(Decoder, "Advancing ITSTATE to %#x,%#x.\n",
 410                         thumb_cond, cond_mask);
 411                 it.mask = cond_mask;
 412                 it.cond = thumb_cond;
 413                 _itstate = it;
 414             }
 415         }
 416
 417         void
 418         uEnd()
 419         {
 420             advance();
 421             upc(0);
 422             nupc(1);
 423         }
 424
 425         Addr
 426         instPC() const
 427         {
 428             return pc() + (thumb() ? 4 : 8);
 429         }
 430
 431         void
 432         instNPC(Addr val)
 433         {
 434             // @todo: review this when AArch32/64 interprocessing is
 435             // supported
 436             if (aarch64())
 437                 npc(val);  // AArch64 doesn't force PC alignment, a PC
 438                            // Alignment Fault can be raised instead
 439             else
 440                 npc(val &~ mask(nextThumb() ? 1 : 2));
 441         }
 442
 443         Addr
 444         instNPC() const
 445         {
 446             return npc();
 447         }
 448
 449         // Perform an interworking branch.
 450         void
 451         instIWNPC(Addr val)
 452         {
 453             bool thumbEE = (thumb() && jazelle());
 454
 455             Addr newPC = val;
 456             if (thumbEE) {
 457                 if (bits(newPC, 0)) {
 458                     newPC = newPC & ~mask(1);
 459                 }  // else we have a bad interworking address; do not call
 460                    // panic() since the instruction could be executed
 461                    // speculatively
 462             } else {
 463                 if (bits(newPC, 0)) {
 464                     nextThumb(true);
 465                     newPC = newPC & ~mask(1);
 466                 } else if (!bits(newPC, 1)) {
 467                     nextThumb(false);
 468                 } else {
 469                     // This state is UNPREDICTABLE in the ARM architecture
 470                     // The easy thing to do is just mask off the bit and
 471                     // stay in the current mode, so we'll do that.
 472                     newPC &= ~mask(2);
 473                 }
 474             }
 475             npc(newPC);
 476         }
 477
 478         // Perform an interworking branch in ARM mode, a regular branch
 479         // otherwise.
 480         void
 481         instAIWNPC(Addr val)
 482         {
 483             if (!thumb() && !jazelle())
 484                 instIWNPC(val);
 485             else
 486                 instNPC(val);
 487         }
 488
 489         bool
 490         operator == (const PCState &opc) const
 491         {
 492             return Base::operator == (opc) &&
 493                 flags == opc.flags && nextFlags == opc.nextFlags &&
 494                 _itstate == opc._itstate &&
 495                 _nextItstate == opc._nextItstate &&
 496                 _illegalExec == opc._illegalExec;
 497         }
 498
 499         bool
 500         operator != (const PCState &opc) const
 501         {
 502             return !(*this == opc);
 503         }
 504
 505         void
 506         serialize(CheckpointOut &cp) const override
 507         {
 508             Base::serialize(cp);
 509             SERIALIZE_SCALAR(flags);
 510             SERIALIZE_SCALAR(_size);
 511             SERIALIZE_SCALAR(nextFlags);
 512             SERIALIZE_SCALAR(_itstate);
 513             SERIALIZE_SCALAR(_nextItstate);
 514             SERIALIZE_SCALAR(_illegalExec);
 515         }
 516
 517         void
 518         unserialize(CheckpointIn &cp) override
 519         {
 520             Base::unserialize(cp);
 521             UNSERIALIZE_SCALAR(flags);
 522             UNSERIALIZE_SCALAR(_size);
 523             UNSERIALIZE_SCALAR(nextFlags);
 524             UNSERIALIZE_SCALAR(_itstate);
 525             UNSERIALIZE_SCALAR(_nextItstate);
 526             UNSERIALIZE_SCALAR(_illegalExec);
 527         }
 528     };
 529
 530     // Shift types for ARM instructions
 531     enum ArmShiftType {
 532         LSL = 0,
 533         LSR,
 534         ASR,
 535         ROR
 536     };
 537
 538     // Extension types for ARM instructions
 539     enum ArmExtendType {
 540         UXTB = 0,
 541         UXTH = 1,
 542         UXTW = 2,
 543         UXTX = 3,
 544         SXTB = 4,
 545         SXTH = 5,
 546         SXTW = 6,
 547         SXTX = 7
 548     };
 549
 550     typedef int RegContextParam;
 551     typedef int RegContextVal;
 552
 553     //used in FP convert & round function
 554     enum ConvertType{
 555         SINGLE_TO_DOUBLE,
 556         SINGLE_TO_WORD,
 557         SINGLE_TO_LONG,
 558
 559         DOUBLE_TO_SINGLE,
 560         DOUBLE_TO_WORD,
 561         DOUBLE_TO_LONG,
 562
 563         LONG_TO_SINGLE,
 564         LONG_TO_DOUBLE,
 565         LONG_TO_WORD,
 566         LONG_TO_PS,
 567
 568         WORD_TO_SINGLE,
 569         WORD_TO_DOUBLE,
 570         WORD_TO_LONG,
 571         WORD_TO_PS,
 572
 573         PL_TO_SINGLE,
 574         PU_TO_SINGLE
 575     };
 576
 577     //used in FP convert & round function
 578     enum RoundMode{
 579         RND_ZERO,
 580         RND_DOWN,
 581         RND_UP,
 582         RND_NEAREST
 583     };
 584
 585     enum ExceptionLevel {
 586         EL0 = 0,
 587         EL1,
 588         EL2,
 589         EL3
 590     };
 591
 592     enum OperatingMode {
 593         MODE_EL0T = 0x0,
 594         MODE_EL1T = 0x4,
 595         MODE_EL1H = 0x5,
 596         MODE_EL2T = 0x8,
 597         MODE_EL2H = 0x9,
 598         MODE_EL3T = 0xC,
 599         MODE_EL3H = 0xD,
 600         MODE_USER = 16,
 601         MODE_FIQ = 17,
 602         MODE_IRQ = 18,
 603         MODE_SVC = 19,
 604         MODE_MON = 22,
 605         MODE_ABORT = 23,
 606         MODE_HYP = 26,
 607         MODE_UNDEFINED = 27,
 608         MODE_SYSTEM = 31,
 609         MODE_MAXMODE = MODE_SYSTEM
 610     };
 611
 612     enum ExceptionClass {
 613         EC_INVALID                 = -1,
 614         EC_UNKNOWN                 = 0x0,
 615         EC_TRAPPED_WFI_WFE         = 0x1,
 616         EC_TRAPPED_CP15_MCR_MRC    = 0x3,
 617         EC_TRAPPED_CP15_MCRR_MRRC  = 0x4,
 618         EC_TRAPPED_CP14_MCR_MRC    = 0x5,
 619         EC_TRAPPED_CP14_LDC_STC    = 0x6,
 620         EC_TRAPPED_HCPTR           = 0x7,
 621         EC_TRAPPED_SIMD_FP         = 0x7,   // AArch64 alias
 622         EC_TRAPPED_CP10_MRC_VMRS   = 0x8,
 623         EC_TRAPPED_BXJ             = 0xA,
 624         EC_TRAPPED_CP14_MCRR_MRRC  = 0xC,
 625         EC_ILLEGAL_INST            = 0xE,
 626         EC_SVC_TO_HYP              = 0x11,
 627         EC_SVC                     = 0x11,  // AArch64 alias
 628         EC_HVC                     = 0x12,
 629         EC_SMC_TO_HYP              = 0x13,
 630         EC_SMC                     = 0x13,  // AArch64 alias
 631         EC_SVC_64                  = 0x15,
 632         EC_HVC_64                  = 0x16,
 633         EC_SMC_64                  = 0x17,
 634         EC_TRAPPED_MSR_MRS_64      = 0x18,
 635         EC_TRAPPED_SVE             = 0x19,
 636         EC_PREFETCH_ABORT_TO_HYP   = 0x20,
 637         EC_PREFETCH_ABORT_LOWER_EL = 0x20,  // AArch64 alias
 638         EC_PREFETCH_ABORT_FROM_HYP = 0x21,
 639         EC_PREFETCH_ABORT_CURR_EL  = 0x21,  // AArch64 alias
 640         EC_PC_ALIGNMENT            = 0x22,
 641         EC_DATA_ABORT_TO_HYP       = 0x24,
 642         EC_DATA_ABORT_LOWER_EL     = 0x24,  // AArch64 alias
 643         EC_DATA_ABORT_FROM_HYP     = 0x25,
 644         EC_DATA_ABORT_CURR_EL      = 0x25,  // AArch64 alias
 645         EC_STACK_PTR_ALIGNMENT     = 0x26,
 646         EC_FP_EXCEPTION            = 0x28,
 647         EC_FP_EXCEPTION_64         = 0x2C,
 648         EC_SERROR                  = 0x2F,
 649         EC_SOFTWARE_BREAKPOINT     = 0x38,
 650         EC_SOFTWARE_BREAKPOINT_64  = 0x3C,
 651     };
 652
 653     /**
 654      * Instruction decoder fault codes in ExtMachInst.
 655      */
 656     enum DecoderFault : std::uint8_t {
 657         OK = 0x0, ///< No fault
 658         UNALIGNED = 0x1, ///< Unaligned instruction fault
 659
 660         PANIC = 0x3, ///< Internal gem5 error
 661     };
 662
 663     BitUnion8(OperatingMode64)
 664         Bitfield<0> spX;
 665         Bitfield<3, 2> el;
 666         Bitfield<4> width;
 667     EndBitUnion(OperatingMode64)
 668
 669     static bool inline
 670     opModeIs64(OperatingMode mode)
 671     {
 672         return ((OperatingMode64)(uint8_t)mode).width == 0;
 673     }
 674
 675     static bool inline
 676     opModeIsH(OperatingMode mode)
 677     {
 678         return (mode == MODE_EL1H || mode == MODE_EL2H || mode == MODE_EL3H);
 679     }
 680
 681     static bool inline
 682     opModeIsT(OperatingMode mode)
 683     {
 684         return (mode == MODE_EL0T || mode == MODE_EL1T || mode == MODE_EL2T ||
 685                 mode == MODE_EL3T);
 686     }
 687
 688     static ExceptionLevel inline
 689     opModeToEL(OperatingMode mode)
 690     {
 691         bool aarch32 = ((mode >> 4) & 1) ? true : false;
 692         if (aarch32) {
 693             switch (mode) {
 694               case MODE_USER:
 695                 return EL0;
 696               case MODE_FIQ:
 697               case MODE_IRQ:
 698               case MODE_SVC:
 699               case MODE_ABORT:
 700               case MODE_UNDEFINED:
 701               case MODE_SYSTEM:
 702                 return EL1;
 703               case MODE_HYP:
 704                 return EL2;
 705               case MODE_MON:
 706                 return EL3;
 707               default:
 708                 panic("Invalid operating mode: %d", mode);
 709                 break;
 710             }
 711         } else {
 712             // aarch64
 713             return (ExceptionLevel) ((mode >> 2) & 3);
 714         }
 715     }
 716
 717     static inline bool
 718     unknownMode(OperatingMode mode)
 719     {
 720         switch (mode) {
 721           case MODE_EL0T:
 722           case MODE_EL1T:
 723           case MODE_EL1H:
 724           case MODE_EL2T:
 725           case MODE_EL2H:
 726           case MODE_EL3T:
 727           case MODE_EL3H:
 728           case MODE_USER:
 729           case MODE_FIQ:
 730           case MODE_IRQ:
 731           case MODE_SVC:
 732           case MODE_MON:
 733           case MODE_ABORT:
 734           case MODE_HYP:
 735           case MODE_UNDEFINED:
 736           case MODE_SYSTEM:
 737             return false;
 738           default:
 739             return true;
 740         }
 741     }
 742
 743     static inline bool
 744     unknownMode32(OperatingMode mode)
 745     {
 746         switch (mode) {
 747           case MODE_USER:
 748           case MODE_FIQ:
 749           case MODE_IRQ:
 750           case MODE_SVC:
 751           case MODE_MON:
 752           case MODE_ABORT:
 753           case MODE_HYP:
 754           case MODE_UNDEFINED:
 755           case MODE_SYSTEM:
 756             return false;
 757           default:
 758             return true;
 759         }
 760     }
 761
 762     constexpr unsigned MaxSveVecLenInBits = 2048;
 763     static_assert(MaxSveVecLenInBits >= 128 &&
 764                   MaxSveVecLenInBits <= 2048 &&
 765                   MaxSveVecLenInBits % 128 == 0,
 766                   "Unsupported max. SVE vector length");
 767     constexpr unsigned MaxSveVecLenInBytes  = MaxSveVecLenInBits >> 3;
 768     constexpr unsigned MaxSveVecLenInWords  = MaxSveVecLenInBits >> 5;
 769     constexpr unsigned MaxSveVecLenInDWords = MaxSveVecLenInBits >> 6;
 770
 771     constexpr unsigned VecRegSizeBytes = MaxSveVecLenInBytes;
 772     constexpr unsigned VecPredRegSizeBits = MaxSveVecLenInBytes;
 773     constexpr unsigned VecPredRegHasPackedRepr = false;
 774 } // namespace ArmISA
 775
 776 #endif