2 * Copyright (c) 2010, 2012-2013, 2017 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
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18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Stephen Hines
43 #ifndef __ARCH_ARM_TYPES_HH__
44 #define __ARCH_ARM_TYPES_HH__
46 #include "arch/generic/types.hh"
47 #include "base/bitunion.hh"
48 #include "base/misc.hh"
49 #include "base/types.hh"
50 #include "debug/Decoder.hh"
54 typedef uint32_t MachInst;
57 /* Note that the split (cond, mask) below is not as in ARM ARM.
58 * But it is more convenient for simulation. The condition
59 * is always the concatenation of the top 3 bits and the next bit,
60 * which applies when one of the bottom 4 bits is set.
61 * Refer to predecoder.cc for the use case.
65 // Bitfields for moving to/from CPSR
67 Bitfield<1, 0> bottom2;
70 BitUnion64(ExtMachInst)
72 Bitfield<63, 62> decoderFault; // See DecoderFault
75 Bitfield<55, 48> itstate;
76 Bitfield<55, 52> itstateCond;
77 Bitfield<51, 48> itstateMask;
80 Bitfield<41, 40> fpscrStride;
81 Bitfield<39, 37> fpscrLen;
83 // Bitfields to select mode.
85 Bitfield<35> bigThumb;
88 // Made up bitfields that make life easier.
89 Bitfield<33> sevenAndFour;
94 // All the different types of opcode fields.
95 Bitfield<27, 25> encoding;
97 Bitfield<24, 21> opcode;
98 Bitfield<24, 20> mediaOpcode;
99 Bitfield<24> opcode24;
100 Bitfield<24, 23> opcode24_23;
101 Bitfield<23, 20> opcode23_20;
102 Bitfield<23, 21> opcode23_21;
103 Bitfield<20> opcode20;
104 Bitfield<22> opcode22;
105 Bitfield<19, 16> opcode19_16;
106 Bitfield<19> opcode19;
107 Bitfield<18> opcode18;
108 Bitfield<15, 12> opcode15_12;
109 Bitfield<15> opcode15;
110 Bitfield<7, 4> miscOpcode;
116 Bitfield<31, 28> condCode;
121 Bitfield<11, 7> shiftSize;
122 Bitfield<6, 5> shift;
127 SubBitUnion(puswl, 24, 20)
128 Bitfield<24> prepost;
130 Bitfield<22> psruser;
131 Bitfield<21> writeback;
133 EndSubBitUnion(puswl)
135 Bitfield<24, 20> pubwl;
139 Bitfield<11, 8> rotate;
141 Bitfield<11, 0> immed11_0;
142 Bitfield<7, 0> immed7_0;
144 Bitfield<11, 8> immedHi11_8;
145 Bitfield<3, 0> immedLo3_0;
147 Bitfield<15, 0> regList;
149 Bitfield<23, 0> offset;
151 Bitfield<23, 0> immed23_0;
153 Bitfield<11, 8> cpNum;
156 Bitfield<3> fpRegImm;
158 Bitfield<2, 0> fpImm;
159 Bitfield<24, 20> punwl;
161 Bitfield<15, 8> m5Func;
163 // 16 bit thumb bitfields
164 Bitfield<15, 13> topcode15_13;
165 Bitfield<13, 11> topcode13_11;
166 Bitfield<12, 11> topcode12_11;
167 Bitfield<12, 10> topcode12_10;
168 Bitfield<11, 9> topcode11_9;
169 Bitfield<11, 8> topcode11_8;
170 Bitfield<10, 9> topcode10_9;
171 Bitfield<10, 8> topcode10_8;
172 Bitfield<9, 6> topcode9_6;
173 Bitfield<7> topcode7;
174 Bitfield<7, 6> topcode7_6;
175 Bitfield<7, 5> topcode7_5;
176 Bitfield<7, 4> topcode7_4;
177 Bitfield<3, 0> topcode3_0;
179 // 32 bit thumb bitfields
180 Bitfield<28, 27> htopcode12_11;
181 Bitfield<26, 25> htopcode10_9;
182 Bitfield<25> htopcode9;
183 Bitfield<25, 24> htopcode9_8;
184 Bitfield<25, 21> htopcode9_5;
185 Bitfield<25, 20> htopcode9_4;
186 Bitfield<24> htopcode8;
187 Bitfield<24, 23> htopcode8_7;
188 Bitfield<24, 22> htopcode8_6;
189 Bitfield<24, 21> htopcode8_5;
190 Bitfield<23> htopcode7;
191 Bitfield<23, 21> htopcode7_5;
192 Bitfield<22> htopcode6;
193 Bitfield<22, 21> htopcode6_5;
194 Bitfield<21, 20> htopcode5_4;
195 Bitfield<20> htopcode4;
197 Bitfield<19, 16> htrn;
200 Bitfield<15> ltopcode15;
201 Bitfield<11, 8> ltopcode11_8;
202 Bitfield<7, 6> ltopcode7_6;
203 Bitfield<7, 4> ltopcode7_4;
204 Bitfield<4> ltopcode4;
206 Bitfield<11, 8> ltrd;
207 Bitfield<11, 8> ltcoproc;
208 EndBitUnion(ExtMachInst)
210 class PCState : public GenericISA::UPCState<MachInst>
214 typedef GenericISA::UPCState<MachInst> Base;
218 JazelleBit = (1 << 1),
219 AArch64Bit = (1 << 2)
224 uint8_t _nextItstate;
227 PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0),
235 npc(val + (thumb() ? 2 : 4));
238 PCState(Addr val) : flags(0), nextFlags(0), _itstate(0),
239 _nextItstate(0), _size(0)
245 return flags & ThumbBit;
260 return nextFlags & ThumbBit;
267 nextFlags |= ThumbBit;
269 nextFlags &= ~ThumbBit;
272 void size(uint8_t s) { _size = s; }
273 uint8_t size() const { return _size; }
278 return ((this->pc() + this->size()) != this->npc());
285 return flags & JazelleBit;
294 flags &= ~JazelleBit;
300 return nextFlags & JazelleBit;
304 nextJazelle(bool val)
307 nextFlags |= JazelleBit;
309 nextFlags &= ~JazelleBit;
315 return flags & AArch64Bit;
324 flags &= ~AArch64Bit;
330 return nextFlags & AArch64Bit;
334 nextAArch64(bool val)
337 nextFlags |= AArch64Bit;
339 nextFlags &= ~AArch64Bit;
350 itstate(uint8_t value)
362 nextItstate(uint8_t value)
364 _nextItstate = value;
372 npc(pc() + (thumb() ? 2 : 4));
375 _itstate = _nextItstate;
377 } else if (_itstate) {
378 ITSTATE it = _itstate;
379 uint8_t cond_mask = it.mask;
380 uint8_t thumb_cond = it.cond;
381 DPRINTF(Decoder, "Advancing ITSTATE from %#x,%#x.\n",
382 thumb_cond, cond_mask);
384 uint8_t new_bit = bits(cond_mask, 4);
385 cond_mask &= mask(4);
389 replaceBits(thumb_cond, 0, new_bit);
390 DPRINTF(Decoder, "Advancing ITSTATE to %#x,%#x.\n",
391 thumb_cond, cond_mask);
393 it.cond = thumb_cond;
409 return pc() + (thumb() ? 4 : 8);
415 // @todo: review this when AArch32/64 interprocessing is
418 npc(val); // AArch64 doesn't force PC alignment, a PC
419 // Alignment Fault can be raised instead
421 npc(val &~ mask(nextThumb() ? 1 : 2));
430 // Perform an interworking branch.
434 bool thumbEE = (thumb() && jazelle());
438 if (bits(newPC, 0)) {
439 newPC = newPC & ~mask(1);
440 } // else we have a bad interworking address; do not call
441 // panic() since the instruction could be executed
444 if (bits(newPC, 0)) {
446 newPC = newPC & ~mask(1);
447 } else if (!bits(newPC, 1)) {
450 // This state is UNPREDICTABLE in the ARM architecture
451 // The easy thing to do is just mask off the bit and
452 // stay in the current mode, so we'll do that.
459 // Perform an interworking branch in ARM mode, a regular branch
464 if (!thumb() && !jazelle())
471 operator == (const PCState &opc) const
473 return Base::operator == (opc) &&
474 flags == opc.flags && nextFlags == opc.nextFlags &&
475 _itstate == opc._itstate && _nextItstate == opc._nextItstate;
479 operator != (const PCState &opc) const
481 return !(*this == opc);
485 serialize(CheckpointOut &cp) const override
488 SERIALIZE_SCALAR(flags);
489 SERIALIZE_SCALAR(_size);
490 SERIALIZE_SCALAR(nextFlags);
491 SERIALIZE_SCALAR(_itstate);
492 SERIALIZE_SCALAR(_nextItstate);
496 unserialize(CheckpointIn &cp) override
498 Base::unserialize(cp);
499 UNSERIALIZE_SCALAR(flags);
500 UNSERIALIZE_SCALAR(_size);
501 UNSERIALIZE_SCALAR(nextFlags);
502 UNSERIALIZE_SCALAR(_itstate);
503 UNSERIALIZE_SCALAR(_nextItstate);
507 // Shift types for ARM instructions
515 // Extension types for ARM instructions
527 typedef int RegContextParam;
528 typedef int RegContextVal;
530 //used in FP convert & round function
554 //used in FP convert & round function
562 enum ExceptionLevel {
586 MODE_MAXMODE = MODE_SYSTEM
589 enum ExceptionClass {
592 EC_TRAPPED_WFI_WFE = 0x1,
593 EC_TRAPPED_CP15_MCR_MRC = 0x3,
594 EC_TRAPPED_CP15_MCRR_MRRC = 0x4,
595 EC_TRAPPED_CP14_MCR_MRC = 0x5,
596 EC_TRAPPED_CP14_LDC_STC = 0x6,
597 EC_TRAPPED_HCPTR = 0x7,
598 EC_TRAPPED_SIMD_FP = 0x7, // AArch64 alias
599 EC_TRAPPED_CP10_MRC_VMRS = 0x8,
600 EC_TRAPPED_BXJ = 0xA,
601 EC_TRAPPED_CP14_MCRR_MRRC = 0xC,
602 EC_ILLEGAL_INST = 0xE,
603 EC_SVC_TO_HYP = 0x11,
604 EC_SVC = 0x11, // AArch64 alias
606 EC_SMC_TO_HYP = 0x13,
607 EC_SMC = 0x13, // AArch64 alias
611 EC_TRAPPED_MSR_MRS_64 = 0x18,
612 EC_PREFETCH_ABORT_TO_HYP = 0x20,
613 EC_PREFETCH_ABORT_LOWER_EL = 0x20, // AArch64 alias
614 EC_PREFETCH_ABORT_FROM_HYP = 0x21,
615 EC_PREFETCH_ABORT_CURR_EL = 0x21, // AArch64 alias
616 EC_PC_ALIGNMENT = 0x22,
617 EC_DATA_ABORT_TO_HYP = 0x24,
618 EC_DATA_ABORT_LOWER_EL = 0x24, // AArch64 alias
619 EC_DATA_ABORT_FROM_HYP = 0x25,
620 EC_DATA_ABORT_CURR_EL = 0x25, // AArch64 alias
621 EC_STACK_PTR_ALIGNMENT = 0x26,
622 EC_FP_EXCEPTION = 0x28,
623 EC_FP_EXCEPTION_64 = 0x2C,
625 EC_SOFTWARE_BREAKPOINT = 0x38,
629 * Instruction decoder fault codes in ExtMachInst.
631 enum DecoderFault : std::uint8_t {
632 OK = 0x0, ///< No fault
633 UNALIGNED = 0x1, ///< Unaligned instruction fault
635 PANIC = 0x3, ///< Internal gem5 error
638 BitUnion8(OperatingMode64)
642 EndBitUnion(OperatingMode64)
645 opModeIs64(OperatingMode mode)
647 return ((OperatingMode64)(uint8_t)mode).width == 0;
651 opModeIsH(OperatingMode mode)
653 return (mode == MODE_EL1H || mode == MODE_EL2H || mode == MODE_EL3H);
657 opModeIsT(OperatingMode mode)
659 return (mode == MODE_EL0T || mode == MODE_EL1T || mode == MODE_EL2T ||
663 static ExceptionLevel inline
664 opModeToEL(OperatingMode mode)
666 bool aarch32 = ((mode >> 4) & 1) ? true : false;
683 panic("Invalid operating mode: %d", mode);
688 return (ExceptionLevel) ((mode >> 2) & 3);
693 badMode(OperatingMode mode)
720 badMode32(OperatingMode mode)
738 } // namespace ArmISA
743 struct hash<ArmISA::ExtMachInst> :
744 public hash<ArmISA::ExtMachInst::__DataType> {
746 size_t operator()(const ArmISA::ExtMachInst &emi) const {
747 return hash<ArmISA::ExtMachInst::__DataType>::operator()(emi);