2 * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
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8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
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12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
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18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
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25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Stephen Hines
43 #ifndef __ARCH_ARM_TYPES_HH__
44 #define __ARCH_ARM_TYPES_HH__
46 #include "arch/generic/types.hh"
47 #include "base/bitunion.hh"
48 #include "base/logging.hh"
49 #include "base/types.hh"
50 #include "debug/Decoder.hh"
54 typedef uint32_t MachInst;
57 /* Note that the split (cond, mask) below is not as in ARM ARM.
58 * But it is more convenient for simulation. The condition
59 * is always the concatenation of the top 3 bits and the next bit,
60 * which applies when one of the bottom 4 bits is set.
61 * Refer to predecoder.cc for the use case.
65 // Bitfields for moving to/from CPSR
67 Bitfield<1, 0> bottom2;
70 BitUnion64(ExtMachInst)
72 Bitfield<63, 62> decoderFault; // See DecoderFault
73 Bitfield<61> illegalExecution;
76 Bitfield<55, 48> itstate;
77 Bitfield<55, 52> itstateCond;
78 Bitfield<51, 48> itstateMask;
81 Bitfield<41, 40> fpscrStride;
82 Bitfield<39, 37> fpscrLen;
84 // Bitfields to select mode.
86 Bitfield<35> bigThumb;
89 // Made up bitfields that make life easier.
90 Bitfield<33> sevenAndFour;
95 // All the different types of opcode fields.
96 Bitfield<27, 25> encoding;
98 Bitfield<24, 21> opcode;
99 Bitfield<24, 20> mediaOpcode;
100 Bitfield<24> opcode24;
101 Bitfield<24, 23> opcode24_23;
102 Bitfield<23, 20> opcode23_20;
103 Bitfield<23, 21> opcode23_21;
104 Bitfield<20> opcode20;
105 Bitfield<22> opcode22;
106 Bitfield<19, 16> opcode19_16;
107 Bitfield<19> opcode19;
108 Bitfield<18> opcode18;
109 Bitfield<15, 12> opcode15_12;
110 Bitfield<15> opcode15;
111 Bitfield<7, 4> miscOpcode;
117 Bitfield<31, 28> condCode;
122 Bitfield<11, 7> shiftSize;
123 Bitfield<6, 5> shift;
128 SubBitUnion(puswl, 24, 20)
129 Bitfield<24> prepost;
131 Bitfield<22> psruser;
132 Bitfield<21> writeback;
134 EndSubBitUnion(puswl)
136 Bitfield<24, 20> pubwl;
140 Bitfield<11, 8> rotate;
142 Bitfield<11, 0> immed11_0;
143 Bitfield<7, 0> immed7_0;
145 Bitfield<11, 8> immedHi11_8;
146 Bitfield<3, 0> immedLo3_0;
148 Bitfield<15, 0> regList;
150 Bitfield<23, 0> offset;
152 Bitfield<23, 0> immed23_0;
154 Bitfield<11, 8> cpNum;
157 Bitfield<3> fpRegImm;
159 Bitfield<2, 0> fpImm;
160 Bitfield<24, 20> punwl;
162 Bitfield<15, 8> m5Func;
164 // 16 bit thumb bitfields
165 Bitfield<15, 13> topcode15_13;
166 Bitfield<13, 11> topcode13_11;
167 Bitfield<12, 11> topcode12_11;
168 Bitfield<12, 10> topcode12_10;
169 Bitfield<11, 9> topcode11_9;
170 Bitfield<11, 8> topcode11_8;
171 Bitfield<10, 9> topcode10_9;
172 Bitfield<10, 8> topcode10_8;
173 Bitfield<9, 6> topcode9_6;
174 Bitfield<7> topcode7;
175 Bitfield<7, 6> topcode7_6;
176 Bitfield<7, 5> topcode7_5;
177 Bitfield<7, 4> topcode7_4;
178 Bitfield<3, 0> topcode3_0;
180 // 32 bit thumb bitfields
181 Bitfield<28, 27> htopcode12_11;
182 Bitfield<26, 25> htopcode10_9;
183 Bitfield<25> htopcode9;
184 Bitfield<25, 24> htopcode9_8;
185 Bitfield<25, 21> htopcode9_5;
186 Bitfield<25, 20> htopcode9_4;
187 Bitfield<24> htopcode8;
188 Bitfield<24, 23> htopcode8_7;
189 Bitfield<24, 22> htopcode8_6;
190 Bitfield<24, 21> htopcode8_5;
191 Bitfield<23> htopcode7;
192 Bitfield<23, 21> htopcode7_5;
193 Bitfield<22> htopcode6;
194 Bitfield<22, 21> htopcode6_5;
195 Bitfield<21, 20> htopcode5_4;
196 Bitfield<20> htopcode4;
198 Bitfield<19, 16> htrn;
201 Bitfield<15> ltopcode15;
202 Bitfield<11, 8> ltopcode11_8;
203 Bitfield<7, 6> ltopcode7_6;
204 Bitfield<7, 4> ltopcode7_4;
205 Bitfield<4> ltopcode4;
207 Bitfield<11, 8> ltrd;
208 Bitfield<11, 8> ltcoproc;
209 EndBitUnion(ExtMachInst)
211 class PCState : public GenericISA::UPCState<MachInst>
215 typedef GenericISA::UPCState<MachInst> Base;
219 JazelleBit = (1 << 1),
220 AArch64Bit = (1 << 2)
226 uint8_t _nextItstate;
230 PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0),
231 _size(0), _illegalExec(false)
238 npc(val + (thumb() ? 2 : 4));
241 PCState(Addr val) : flags(0), nextFlags(0), _itstate(0),
242 _nextItstate(0), _size(0), _illegalExec(false)
252 illegalExec(bool val)
260 return flags & ThumbBit;
275 return nextFlags & ThumbBit;
282 nextFlags |= ThumbBit;
284 nextFlags &= ~ThumbBit;
287 void size(uint8_t s) { _size = s; }
288 uint8_t size() const { return _size; }
293 return ((this->pc() + this->size()) != this->npc());
300 return flags & JazelleBit;
309 flags &= ~JazelleBit;
315 return nextFlags & JazelleBit;
319 nextJazelle(bool val)
322 nextFlags |= JazelleBit;
324 nextFlags &= ~JazelleBit;
330 return flags & AArch64Bit;
339 flags &= ~AArch64Bit;
345 return nextFlags & AArch64Bit;
349 nextAArch64(bool val)
352 nextFlags |= AArch64Bit;
354 nextFlags &= ~AArch64Bit;
365 itstate(uint8_t value)
377 nextItstate(uint8_t value)
379 _nextItstate = value;
387 npc(pc() + (thumb() ? 2 : 4));
390 _itstate = _nextItstate;
392 } else if (_itstate) {
393 ITSTATE it = _itstate;
394 uint8_t cond_mask = it.mask;
395 uint8_t thumb_cond = it.cond;
396 DPRINTF(Decoder, "Advancing ITSTATE from %#x,%#x.\n",
397 thumb_cond, cond_mask);
399 uint8_t new_bit = bits(cond_mask, 4);
400 cond_mask &= mask(4);
404 replaceBits(thumb_cond, 0, new_bit);
405 DPRINTF(Decoder, "Advancing ITSTATE to %#x,%#x.\n",
406 thumb_cond, cond_mask);
408 it.cond = thumb_cond;
424 return pc() + (thumb() ? 4 : 8);
430 // @todo: review this when AArch32/64 interprocessing is
433 npc(val); // AArch64 doesn't force PC alignment, a PC
434 // Alignment Fault can be raised instead
436 npc(val &~ mask(nextThumb() ? 1 : 2));
445 // Perform an interworking branch.
449 bool thumbEE = (thumb() && jazelle());
453 if (bits(newPC, 0)) {
454 newPC = newPC & ~mask(1);
455 } // else we have a bad interworking address; do not call
456 // panic() since the instruction could be executed
459 if (bits(newPC, 0)) {
461 newPC = newPC & ~mask(1);
462 } else if (!bits(newPC, 1)) {
465 // This state is UNPREDICTABLE in the ARM architecture
466 // The easy thing to do is just mask off the bit and
467 // stay in the current mode, so we'll do that.
474 // Perform an interworking branch in ARM mode, a regular branch
479 if (!thumb() && !jazelle())
486 operator == (const PCState &opc) const
488 return Base::operator == (opc) &&
489 flags == opc.flags && nextFlags == opc.nextFlags &&
490 _itstate == opc._itstate &&
491 _nextItstate == opc._nextItstate &&
492 _illegalExec == opc._illegalExec;
496 operator != (const PCState &opc) const
498 return !(*this == opc);
502 serialize(CheckpointOut &cp) const override
505 SERIALIZE_SCALAR(flags);
506 SERIALIZE_SCALAR(_size);
507 SERIALIZE_SCALAR(nextFlags);
508 SERIALIZE_SCALAR(_itstate);
509 SERIALIZE_SCALAR(_nextItstate);
510 SERIALIZE_SCALAR(_illegalExec);
514 unserialize(CheckpointIn &cp) override
516 Base::unserialize(cp);
517 UNSERIALIZE_SCALAR(flags);
518 UNSERIALIZE_SCALAR(_size);
519 UNSERIALIZE_SCALAR(nextFlags);
520 UNSERIALIZE_SCALAR(_itstate);
521 UNSERIALIZE_SCALAR(_nextItstate);
522 UNSERIALIZE_SCALAR(_illegalExec);
526 // Shift types for ARM instructions
534 // Extension types for ARM instructions
546 typedef int RegContextParam;
547 typedef int RegContextVal;
549 //used in FP convert & round function
573 //used in FP convert & round function
581 enum ExceptionLevel {
605 MODE_MAXMODE = MODE_SYSTEM
608 enum ExceptionClass {
611 EC_TRAPPED_WFI_WFE = 0x1,
612 EC_TRAPPED_CP15_MCR_MRC = 0x3,
613 EC_TRAPPED_CP15_MCRR_MRRC = 0x4,
614 EC_TRAPPED_CP14_MCR_MRC = 0x5,
615 EC_TRAPPED_CP14_LDC_STC = 0x6,
616 EC_TRAPPED_HCPTR = 0x7,
617 EC_TRAPPED_SIMD_FP = 0x7, // AArch64 alias
618 EC_TRAPPED_CP10_MRC_VMRS = 0x8,
619 EC_TRAPPED_BXJ = 0xA,
620 EC_TRAPPED_CP14_MCRR_MRRC = 0xC,
621 EC_ILLEGAL_INST = 0xE,
622 EC_SVC_TO_HYP = 0x11,
623 EC_SVC = 0x11, // AArch64 alias
625 EC_SMC_TO_HYP = 0x13,
626 EC_SMC = 0x13, // AArch64 alias
630 EC_TRAPPED_MSR_MRS_64 = 0x18,
631 EC_PREFETCH_ABORT_TO_HYP = 0x20,
632 EC_PREFETCH_ABORT_LOWER_EL = 0x20, // AArch64 alias
633 EC_PREFETCH_ABORT_FROM_HYP = 0x21,
634 EC_PREFETCH_ABORT_CURR_EL = 0x21, // AArch64 alias
635 EC_PC_ALIGNMENT = 0x22,
636 EC_DATA_ABORT_TO_HYP = 0x24,
637 EC_DATA_ABORT_LOWER_EL = 0x24, // AArch64 alias
638 EC_DATA_ABORT_FROM_HYP = 0x25,
639 EC_DATA_ABORT_CURR_EL = 0x25, // AArch64 alias
640 EC_STACK_PTR_ALIGNMENT = 0x26,
641 EC_FP_EXCEPTION = 0x28,
642 EC_FP_EXCEPTION_64 = 0x2C,
644 EC_SOFTWARE_BREAKPOINT = 0x38,
645 EC_SOFTWARE_BREAKPOINT_64 = 0x3C,
649 * Instruction decoder fault codes in ExtMachInst.
651 enum DecoderFault : std::uint8_t {
652 OK = 0x0, ///< No fault
653 UNALIGNED = 0x1, ///< Unaligned instruction fault
655 PANIC = 0x3, ///< Internal gem5 error
658 BitUnion8(OperatingMode64)
662 EndBitUnion(OperatingMode64)
665 opModeIs64(OperatingMode mode)
667 return ((OperatingMode64)(uint8_t)mode).width == 0;
671 opModeIsH(OperatingMode mode)
673 return (mode == MODE_EL1H || mode == MODE_EL2H || mode == MODE_EL3H);
677 opModeIsT(OperatingMode mode)
679 return (mode == MODE_EL0T || mode == MODE_EL1T || mode == MODE_EL2T ||
683 static ExceptionLevel inline
684 opModeToEL(OperatingMode mode)
686 bool aarch32 = ((mode >> 4) & 1) ? true : false;
703 panic("Invalid operating mode: %d", mode);
708 return (ExceptionLevel) ((mode >> 2) & 3);
713 unknownMode(OperatingMode mode)
739 unknownMode32(OperatingMode mode)
757 } // namespace ArmISA