2 * Copyright (c) 2009-2014 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
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15 * modification, are permitted provided that the following conditions are
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17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
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23 * this software without specific prior written permission.
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 #include "arch/arm/faults.hh"
42 #include "arch/arm/isa_traits.hh"
43 #include "arch/arm/system.hh"
44 #include "arch/arm/tlb.hh"
45 #include "arch/arm/utility.hh"
46 #include "arch/arm/vtophys.hh"
47 #include "cpu/checker/cpu.hh"
48 #include "cpu/base.hh"
49 #include "cpu/thread_context.hh"
50 #include "mem/fs_translating_port_proxy.hh"
51 #include "sim/full_system.hh"
56 initCPU(ThreadContext
*tc
, int cpuId
)
58 // Reset CP15?? What does that mean -- ali
62 static Fault reset
= new Reset
;
67 getArgument(ThreadContext
*tc
, int &number
, uint16_t size
, bool fp
)
70 panic("getArgument() only implemented for full system mode.\n");
75 panic("getArgument(): Floating point arguments not implemented\n");
78 if (size
== (uint16_t)(-1))
79 size
= sizeof(uint64_t);
81 if (number
< 8 /*NumArgumentRegs64*/) {
82 return tc
->readIntReg(number
);
84 panic("getArgument(): No support reading stack args for AArch64\n");
87 if (size
== (uint16_t)(-1))
88 // todo: should this not be sizeof(uint32_t) rather?
89 size
= ArmISA::MachineBytes
;
91 if (number
< NumArgumentRegs
) {
92 // If the argument is 64 bits, it must be in an even regiser
93 // number. Increment the number here if it isn't even.
94 if (size
== sizeof(uint64_t)) {
95 if ((number
% 2) != 0)
97 // Read the two halves of the data. Number is inc here to
98 // get the second half of the 64 bit reg.
100 tmp
= tc
->readIntReg(number
++);
101 tmp
|= tc
->readIntReg(number
) << 32;
104 return tc
->readIntReg(number
);
107 Addr sp
= tc
->readIntReg(StackPointerReg
);
108 FSTranslatingPortProxy
&vp
= tc
->getVirtProxy();
110 if (size
== sizeof(uint64_t)) {
111 // If the argument is even it must be aligned
112 if ((number
% 2) != 0)
114 arg
= vp
.read
<uint64_t>(sp
+
115 (number
-NumArgumentRegs
) * sizeof(uint32_t));
116 // since two 32 bit args == 1 64 bit arg, increment number
119 arg
= vp
.read
<uint32_t>(sp
+
120 (number
-NumArgumentRegs
) * sizeof(uint32_t));
125 panic("getArgument() should always return\n");
129 skipFunction(ThreadContext
*tc
)
131 PCState newPC
= tc
->pcState();
133 newPC
.set(tc
->readIntReg(INTREG_X30
));
135 newPC
.set(tc
->readIntReg(ReturnAddressReg
) & ~ULL(1));
138 CheckerCPU
*checker
= tc
->getCheckerCpuPtr();
140 tc
->pcStateNoRecord(newPC
);
147 copyRegs(ThreadContext
*src
, ThreadContext
*dest
)
149 for (int i
= 0; i
< NumIntRegs
; i
++)
150 dest
->setIntRegFlat(i
, src
->readIntRegFlat(i
));
152 for (int i
= 0; i
< NumFloatRegs
; i
++)
153 dest
->setFloatRegFlat(i
, src
->readFloatRegFlat(i
));
155 for (int i
= 0; i
< NumCCRegs
; i
++)
156 dest
->setCCReg(i
, src
->readCCReg(i
));
158 for (int i
= 0; i
< NumMiscRegs
; i
++)
159 dest
->setMiscRegNoEffect(i
, src
->readMiscRegNoEffect(i
));
161 // setMiscReg "with effect" will set the misc register mapping correctly.
162 // e.g. updateRegMap(val)
163 dest
->setMiscReg(MISCREG_CPSR
, src
->readMiscRegNoEffect(MISCREG_CPSR
));
165 // Copy over the PC State
166 dest
->pcState(src
->pcState());
168 // Invalidate the tlb misc register cache
169 dest
->getITBPtr()->invalidateMiscReg();
170 dest
->getDTBPtr()->invalidateMiscReg();
174 inSecureState(ThreadContext
*tc
)
176 SCR scr
= inAArch64(tc
) ? tc
->readMiscReg(MISCREG_SCR_EL3
) :
177 tc
->readMiscReg(MISCREG_SCR
);
178 return ArmSystem::haveSecurity(tc
) && inSecureState(
179 scr
, tc
->readMiscReg(MISCREG_CPSR
));
183 inAArch64(ThreadContext
*tc
)
185 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
186 return opModeIs64((OperatingMode
) (uint8_t) cpsr
.mode
);
190 longDescFormatInUse(ThreadContext
*tc
)
192 TTBCR ttbcr
= tc
->readMiscReg(MISCREG_TTBCR
);
193 return ArmSystem::haveLPAE(tc
) && ttbcr
.eae
;
197 getMPIDR(ArmSystem
*arm_sys
, ThreadContext
*tc
)
199 // Multiprocessor Affinity Register MPIDR from Cortex(tm)-A15 Technical
202 // bit 31 - Multi-processor extensions available
203 // bit 30 - Uni-processor system
204 // bit 24 - Multi-threaded cores
205 // bit 11-8 - Cluster ID
208 // We deliberately extend both the Cluster ID and CPU ID fields to allow
209 // for simulation of larger systems
210 assert((0 <= tc
->cpuId()) && (tc
->cpuId() < 256));
211 assert((0 <= tc
->socketId()) && (tc
->socketId() < 65536));
212 if (arm_sys
->multiProc
) {
213 return 0x80000000 | // multiprocessor extensions available
214 tc
->cpuId() | tc
->socketId() << 8;
216 return 0x80000000 | // multiprocessor extensions available
217 0x40000000 | // in up system
218 tc
->cpuId() | tc
->socketId() << 8;
223 ELIs64(ThreadContext
*tc
, ExceptionLevel el
)
225 if (ArmSystem::highestEL(tc
) == el
)
226 // Register width is hard-wired
227 return ArmSystem::highestELIs64(tc
);
231 return opModeIs64(currOpMode(tc
));
234 // @todo: uncomment this to enable Virtualization
235 // if (ArmSystem::haveVirtualization(tc)) {
236 // HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
239 assert(ArmSystem::haveSecurity(tc
));
240 SCR scr
= tc
->readMiscReg(MISCREG_SCR_EL3
);
245 assert(ArmSystem::haveSecurity(tc
));
246 SCR scr
= tc
->readMiscReg(MISCREG_SCR_EL3
);
250 panic("Invalid exception level");
256 isBigEndian64(ThreadContext
*tc
)
258 switch (opModeToEL(currOpMode(tc
))) {
260 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL3
)).ee
;
262 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL2
)).ee
;
264 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL1
)).ee
;
266 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL1
)).e0e
;
268 panic("Invalid exception level");
274 purifyTaggedAddr(Addr addr
, ThreadContext
*tc
, ExceptionLevel el
)
281 tcr
= tc
->readMiscReg(MISCREG_TCR_EL1
);
282 if (bits(addr
, 55, 48) == 0xFF && tcr
.tbi1
)
283 return addr
| mask(63, 55);
284 else if (!bits(addr
, 55, 48) && tcr
.tbi0
)
285 return bits(addr
,55, 0);
287 // @todo: uncomment this to enable Virtualization
289 // assert(ArmSystem::haveVirtualization());
290 // tcr = tc->readMiscReg(MISCREG_TCR_EL2);
292 // return addr & mask(56);
295 assert(ArmSystem::haveSecurity(tc
));
296 tcr
= tc
->readMiscReg(MISCREG_TCR_EL3
);
298 return addr
& mask(56);
301 panic("Invalid exception level");
305 return addr
; // Nothing to do if this is not a tagged address
311 return addr
& ~(PageBytes
- 1);
317 return (addr
+ PageBytes
- 1) & ~(PageBytes
- 1);
321 mcrMrc15TrapToHyp(const MiscRegIndex miscReg
, HCR hcr
, CPSR cpsr
, SCR scr
,
322 HDCR hdcr
, HSTR hstr
, HCPTR hcptr
, uint32_t iss
)
330 bool trapToHype
= false;
333 if (!inSecureState(scr
, cpsr
) && (cpsr
.mode
!= MODE_HYP
)) {
334 mcrMrcIssExtract(iss
, isRead
, crm
, rt
, crn
, opc1
, opc2
);
335 trapToHype
= ((uint32_t) hstr
) & (1 << crn
);
336 trapToHype
|= hdcr
.tpm
&& (crn
== 9) && (crm
>= 12);
337 trapToHype
|= hcr
.tidcp
&& (
338 ((crn
== 9) && ((crm
<= 2) || ((crm
>= 5) && (crm
<= 8)))) ||
339 ((crn
== 10) && ((crm
<= 1) || (crm
== 4) || (crm
== 8))) ||
340 ((crn
== 11) && ((crm
<= 8) || (crm
== 15))) );
343 switch (unflattenMiscReg(miscReg
)) {
345 trapToHype
= hcptr
.tcpac
;
351 trapToHype
= hcr
.tid1
;
357 trapToHype
= hcr
.tid2
;
359 case MISCREG_ID_PFR0
:
360 case MISCREG_ID_PFR1
:
361 case MISCREG_ID_DFR0
:
362 case MISCREG_ID_AFR0
:
363 case MISCREG_ID_MMFR0
:
364 case MISCREG_ID_MMFR1
:
365 case MISCREG_ID_MMFR2
:
366 case MISCREG_ID_MMFR3
:
367 case MISCREG_ID_ISAR0
:
368 case MISCREG_ID_ISAR1
:
369 case MISCREG_ID_ISAR2
:
370 case MISCREG_ID_ISAR3
:
371 case MISCREG_ID_ISAR4
:
372 case MISCREG_ID_ISAR5
:
373 trapToHype
= hcr
.tid3
;
378 trapToHype
= hcr
.tsw
;
380 case MISCREG_DCIMVAC
:
381 case MISCREG_DCCIMVAC
:
382 case MISCREG_DCCMVAC
:
383 trapToHype
= hcr
.tpc
;
385 case MISCREG_ICIMVAU
:
386 case MISCREG_ICIALLU
:
387 case MISCREG_ICIALLUIS
:
388 case MISCREG_DCCMVAU
:
389 trapToHype
= hcr
.tpu
;
391 case MISCREG_TLBIALLIS
:
392 case MISCREG_TLBIMVAIS
:
393 case MISCREG_TLBIASIDIS
:
394 case MISCREG_TLBIMVAAIS
:
395 case MISCREG_DTLBIALL
:
396 case MISCREG_ITLBIALL
:
397 case MISCREG_DTLBIMVA
:
398 case MISCREG_ITLBIMVA
:
399 case MISCREG_DTLBIASID
:
400 case MISCREG_ITLBIASID
:
401 case MISCREG_TLBIMVAA
:
402 case MISCREG_TLBIALL
:
403 case MISCREG_TLBIMVA
:
404 case MISCREG_TLBIASID
:
405 trapToHype
= hcr
.ttlb
;
408 trapToHype
= hcr
.tac
;
425 case MISCREG_CONTEXTIDR
:
426 trapToHype
= hcr
.tvm
& !isRead
;
429 trapToHype
= hdcr
.tpmcr
;
431 // No default action needed
442 mcrMrc14TrapToHyp(const MiscRegIndex miscReg
, HCR hcr
, CPSR cpsr
, SCR scr
,
443 HDCR hdcr
, HSTR hstr
, HCPTR hcptr
, uint32_t iss
)
451 bool trapToHype
= false;
453 if (!inSecureState(scr
, cpsr
) && (cpsr
.mode
!= MODE_HYP
)) {
454 mcrMrcIssExtract(iss
, isRead
, crm
, rt
, crn
, opc1
, opc2
);
455 inform("trap check M:%x N:%x 1:%x 2:%x hdcr %x, hcptr %x, hstr %x\n",
456 crm
, crn
, opc1
, opc2
, hdcr
, hcptr
, hstr
);
457 trapToHype
= hdcr
.tda
&& (opc1
== 0);
458 trapToHype
|= hcptr
.tta
&& (opc1
== 1);
460 switch (unflattenMiscReg(miscReg
)) {
461 case MISCREG_DBGOSLSR
:
462 case MISCREG_DBGOSLAR
:
463 case MISCREG_DBGOSDLR
:
464 case MISCREG_DBGPRCR
:
465 trapToHype
= hdcr
.tdosa
;
467 case MISCREG_DBGDRAR
:
468 case MISCREG_DBGDSAR
:
469 trapToHype
= hdcr
.tdra
;
472 trapToHype
= hcr
.tid0
;
476 trapToHype
= hstr
.tjdbx
;
480 trapToHype
= hstr
.ttee
;
482 // No default action needed
492 mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg
, CPSR cpsr
, SCR scr
, HSTR hstr
,
493 HCR hcr
, uint32_t iss
)
501 bool trapToHype
= false;
503 if (!inSecureState(scr
, cpsr
) && (cpsr
.mode
!= MODE_HYP
)) {
504 // This is technically the wrong function, but we can re-use it for
505 // the moment because we only need one field, which overlaps with the
507 mcrMrcIssExtract(iss
, isRead
, crm
, rt
, crn
, opc1
, opc2
);
508 trapToHype
= ((uint32_t) hstr
) & (1 << crm
);
511 switch (unflattenMiscReg(miscReg
)) {
527 case MISCREG_CONTEXTIDR
:
528 trapToHype
= hcr
.tvm
& !isRead
;
530 // No default action needed
540 msrMrs64TrapToSup(const MiscRegIndex miscReg
, ExceptionLevel el
,
541 CPACR cpacr
/* CPACR_EL1 */)
543 bool trapToSup
= false;
547 case MISCREG_FPEXC32_EL2
:
548 if ((el
== EL0
&& cpacr
.fpen
!= 0x3) ||
549 (el
== EL1
&& !(cpacr
.fpen
& 0x1)))
559 msrMrs64TrapToHyp(const MiscRegIndex miscReg
, bool isRead
,
560 CPTR cptr
/* CPTR_EL2 */,
561 HCR hcr
/* HCR_EL2 */,
564 bool trapToHyp
= false;
571 case MISCREG_FPEXC32_EL2
:
572 trapToHyp
= cptr
.tfp
;
576 case MISCREG_CPACR_EL1
:
577 trapToHyp
= cptr
.tcpac
;
579 // Virtual memory control regs
580 case MISCREG_SCTLR_EL1
:
581 case MISCREG_TTBR0_EL1
:
582 case MISCREG_TTBR1_EL1
:
583 case MISCREG_TCR_EL1
:
584 case MISCREG_ESR_EL1
:
585 case MISCREG_FAR_EL1
:
586 case MISCREG_AFSR0_EL1
:
587 case MISCREG_AFSR1_EL1
:
588 case MISCREG_MAIR_EL1
:
589 case MISCREG_AMAIR_EL1
:
590 case MISCREG_CONTEXTIDR_EL1
:
591 trapToHyp
= (hcr
.trvm
&& isRead
) || (hcr
.tvm
&& !isRead
);
593 // TLB maintenance instructions
594 case MISCREG_TLBI_VMALLE1
:
595 case MISCREG_TLBI_VAE1_Xt
:
596 case MISCREG_TLBI_ASIDE1_Xt
:
597 case MISCREG_TLBI_VAAE1_Xt
:
598 case MISCREG_TLBI_VALE1_Xt
:
599 case MISCREG_TLBI_VAALE1_Xt
:
600 case MISCREG_TLBI_VMALLE1IS
:
601 case MISCREG_TLBI_VAE1IS_Xt
:
602 case MISCREG_TLBI_ASIDE1IS_Xt
:
603 case MISCREG_TLBI_VAAE1IS_Xt
:
604 case MISCREG_TLBI_VALE1IS_Xt
:
605 case MISCREG_TLBI_VAALE1IS_Xt
:
606 trapToHyp
= hcr
.ttlb
;
608 // Cache maintenance instructions to the point of unification
609 case MISCREG_IC_IVAU_Xt
:
610 case MISCREG_ICIALLU
:
611 case MISCREG_ICIALLUIS
:
612 case MISCREG_DC_CVAU_Xt
:
615 // Data/Unified cache maintenance instructions to the point of coherency
616 case MISCREG_DC_IVAC_Xt
:
617 case MISCREG_DC_CIVAC_Xt
:
618 case MISCREG_DC_CVAC_Xt
:
621 // Data/Unified cache maintenance instructions by set/way
622 case MISCREG_DC_ISW_Xt
:
623 case MISCREG_DC_CSW_Xt
:
624 case MISCREG_DC_CISW_Xt
:
628 case MISCREG_ACTLR_EL1
:
629 trapToHyp
= hcr
.tacr
;
632 // @todo: Trap implementation-dependent functionality based on
636 case MISCREG_ID_PFR0_EL1
:
637 case MISCREG_ID_PFR1_EL1
:
638 case MISCREG_ID_DFR0_EL1
:
639 case MISCREG_ID_AFR0_EL1
:
640 case MISCREG_ID_MMFR0_EL1
:
641 case MISCREG_ID_MMFR1_EL1
:
642 case MISCREG_ID_MMFR2_EL1
:
643 case MISCREG_ID_MMFR3_EL1
:
644 case MISCREG_ID_ISAR0_EL1
:
645 case MISCREG_ID_ISAR1_EL1
:
646 case MISCREG_ID_ISAR2_EL1
:
647 case MISCREG_ID_ISAR3_EL1
:
648 case MISCREG_ID_ISAR4_EL1
:
649 case MISCREG_ID_ISAR5_EL1
:
650 case MISCREG_MVFR0_EL1
:
651 case MISCREG_MVFR1_EL1
:
652 case MISCREG_MVFR2_EL1
:
653 case MISCREG_ID_AA64PFR0_EL1
:
654 case MISCREG_ID_AA64PFR1_EL1
:
655 case MISCREG_ID_AA64DFR0_EL1
:
656 case MISCREG_ID_AA64DFR1_EL1
:
657 case MISCREG_ID_AA64ISAR0_EL1
:
658 case MISCREG_ID_AA64ISAR1_EL1
:
659 case MISCREG_ID_AA64MMFR0_EL1
:
660 case MISCREG_ID_AA64MMFR1_EL1
:
661 case MISCREG_ID_AA64AFR0_EL1
:
662 case MISCREG_ID_AA64AFR1_EL1
:
664 trapToHyp
= hcr
.tid3
;
667 case MISCREG_CTR_EL0
:
668 case MISCREG_CCSIDR_EL1
:
669 case MISCREG_CLIDR_EL1
:
670 case MISCREG_CSSELR_EL1
:
671 trapToHyp
= hcr
.tid2
;
674 case MISCREG_AIDR_EL1
:
675 case MISCREG_REVIDR_EL1
:
677 trapToHyp
= hcr
.tid1
;
686 msrMrs64TrapToMon(const MiscRegIndex miscReg
, CPTR cptr
/* CPTR_EL3 */,
687 ExceptionLevel el
, bool * isVfpNeon
)
689 bool trapToMon
= false;
696 case MISCREG_FPEXC32_EL2
:
697 trapToMon
= cptr
.tfp
;
701 case MISCREG_CPACR_EL1
:
703 trapToMon
= cptr
.tcpac
;
706 case MISCREG_CPTR_EL2
:
708 trapToMon
= cptr
.tcpac
;
718 decodeMrsMsrBankedReg(uint8_t sysM
, bool r
, bool &isIntReg
, int ®Idx
,
719 CPSR cpsr
, SCR scr
, NSACR nsacr
, bool checkSecurity
)
721 OperatingMode mode
= MODE_UNDEFINED
;
724 // R mostly indicates if its a int register or a misc reg, we override
725 // below if the few corner cases
727 // Loosely based on ARM ARM issue C section B9.3.10
732 regIdx
= MISCREG_SPSR_FIQ
;
736 regIdx
= MISCREG_SPSR_IRQ
;
740 regIdx
= MISCREG_SPSR_SVC
;
744 regIdx
= MISCREG_SPSR_ABT
;
748 regIdx
= MISCREG_SPSR_UND
;
749 mode
= MODE_UNDEFINED
;
752 regIdx
= MISCREG_SPSR_MON
;
756 regIdx
= MISCREG_SPSR_HYP
;
764 int sysM4To3
= bits(sysM
, 4, 3);
768 regIdx
= intRegInMode(mode
, bits(sysM
, 2, 0) + 8);
769 } else if (sysM4To3
== 1) {
771 regIdx
= intRegInMode(mode
, bits(sysM
, 2, 0) + 8);
772 } else if (sysM4To3
== 3) {
773 if (bits(sysM
, 1) == 0) {
775 regIdx
= intRegInMode(mode
, 14 - bits(sysM
, 0));
778 if (bits(sysM
, 0) == 1) {
779 regIdx
= intRegInMode(mode
, 13); // R13 in HYP
782 regIdx
= MISCREG_ELR_HYP
;
785 } else { // Other Banked registers
786 int sysM2
= bits(sysM
, 2);
787 int sysM1
= bits(sysM
, 1);
789 mode
= (OperatingMode
) ( ((sysM2
|| sysM1
) << 0) |
791 ((sysM2
&& !sysM1
) << 2) |
792 ((sysM2
&& sysM1
) << 3) |
794 regIdx
= intRegInMode(mode
, 14 - bits(sysM
, 0));
795 // Don't flatten the register here. This is going to go through
796 // setIntReg() which will do the flattening
797 ok
&= mode
!= cpsr
.mode
;
801 // Check that the requested register is accessable from the current mode
802 if (ok
&& checkSecurity
&& mode
!= cpsr
.mode
) {
809 ok
&= mode
!= MODE_HYP
;
810 ok
&= (mode
!= MODE_MON
) || !scr
.ns
;
813 ok
&= mode
!= MODE_MON
;
814 ok
&= (mode
!= MODE_FIQ
) || !nsacr
.rfr
;
821 ok
&= mode
!= MODE_HYP
;
822 ok
&= (mode
!= MODE_MON
) || !scr
.ns
;
823 ok
&= (mode
!= MODE_FIQ
) || !nsacr
.rfr
;
825 // can access everything, no further checks required
829 panic("unknown Mode 0x%x\n", cpsr
.mode
);
837 vfpNeonEnabled(uint32_t &seq
, HCPTR hcptr
, NSACR nsacr
, CPACR cpacr
, CPSR cpsr
,
838 uint32_t &iss
, bool &trap
, ThreadContext
*tc
, FPEXC fpexc
,
843 bool undefined
= false;
844 bool haveSecurity
= ArmSystem::haveSecurity(tc
);
845 bool haveVirtualization
= ArmSystem::haveVirtualization(tc
);
846 bool isSecure
= inSecureState(tc
);
848 // Non-secure view of CPACR and HCPTR determines behavior
849 // Copy register values
850 uint8_t cpacr_cp10
= cpacr
.cp10
;
851 bool cpacr_asedis
= cpacr
.asedis
;
852 bool hcptr_cp10
= false;
853 bool hcptr_tase
= false;
855 bool cp10_enabled
= cpacr
.cp10
== 0x3
856 || (cpacr
.cp10
== 0x1 && inPrivilegedMode(cpsr
));
858 bool cp11_enabled
= cpacr
.cp11
== 0x3
859 || (cpacr
.cp11
== 0x1 && inPrivilegedMode(cpsr
));
862 undefined
|= !(fpexc
.en
&& cp10_enabled
);
864 undefined
|= !(fpexc
.en
&& cp10_enabled
&& (cpacr
.cp11
== cpacr
.cp10
));
867 if (haveVirtualization
) {
868 hcptr_cp10
= hcptr
.tcp10
;
869 undefined
|= hcptr
.tcp10
!= hcptr
.tcp11
;
870 hcptr_tase
= hcptr
.tase
;
874 undefined
|= nsacr
.cp10
!= nsacr
.cp11
;
876 // Modify register values to the Non-secure view
879 if (haveVirtualization
) {
883 if (nsacr
.nsasedis
) {
885 if (haveVirtualization
) {
892 // Check Coprocessor Access Control Register for permission to use CP10/11.
893 if (!haveVirtualization
|| (cpsr
.mode
!= MODE_HYP
)) {
900 undefined
|= inUserMode(cpsr
);
904 // Check if SIMD operations are disabled
905 if (isSIMD
&& cpacr_asedis
) undefined
= true;
908 // If required, check FPEXC enabled bit.
909 undefined
|= !fpexc
.en
;
911 if (haveSecurity
&& haveVirtualization
&& !isSecure
) {
912 if (hcptr_cp10
|| (isSIMD
&& hcptr_tase
)) {
913 iss
= isSIMD
? (1 << 5) : 0xA;
922 SPAlignmentCheckEnabled(ThreadContext
* tc
)
924 switch (opModeToEL(currOpMode(tc
))) {
926 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL3
)).sa
;
928 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL2
)).sa
;
930 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL1
)).sa
;
932 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL1
)).sa0
;
934 panic("Invalid exception level");
940 decodePhysAddrRange64(uint8_t pa_enc
)
958 panic("Invalid phys. address range encoding");
963 encodePhysAddrRange64(int pa_size
)
979 panic("Invalid phys. address range");
983 } // namespace ArmISA