2 * Copyright (c) 2009-2014 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include "arch/arm/faults.hh"
43 #include "arch/arm/isa_traits.hh"
44 #include "arch/arm/system.hh"
45 #include "arch/arm/tlb.hh"
46 #include "arch/arm/utility.hh"
47 #include "arch/arm/vtophys.hh"
48 #include "cpu/checker/cpu.hh"
49 #include "cpu/base.hh"
50 #include "cpu/thread_context.hh"
51 #include "mem/fs_translating_port_proxy.hh"
52 #include "sim/full_system.hh"
57 initCPU(ThreadContext
*tc
, int cpuId
)
59 // Reset CP15?? What does that mean -- ali
63 static Fault reset
= std::make_shared
<Reset
>();
68 getArgument(ThreadContext
*tc
, int &number
, uint16_t size
, bool fp
)
71 panic("getArgument() only implemented for full system mode.\n");
76 panic("getArgument(): Floating point arguments not implemented\n");
79 if (size
== (uint16_t)(-1))
80 size
= sizeof(uint64_t);
82 if (number
< 8 /*NumArgumentRegs64*/) {
83 return tc
->readIntReg(number
);
85 panic("getArgument(): No support reading stack args for AArch64\n");
88 if (size
== (uint16_t)(-1))
89 // todo: should this not be sizeof(uint32_t) rather?
90 size
= ArmISA::MachineBytes
;
92 if (number
< NumArgumentRegs
) {
93 // If the argument is 64 bits, it must be in an even regiser
94 // number. Increment the number here if it isn't even.
95 if (size
== sizeof(uint64_t)) {
96 if ((number
% 2) != 0)
98 // Read the two halves of the data. Number is inc here to
99 // get the second half of the 64 bit reg.
101 tmp
= tc
->readIntReg(number
++);
102 tmp
|= tc
->readIntReg(number
) << 32;
105 return tc
->readIntReg(number
);
108 Addr sp
= tc
->readIntReg(StackPointerReg
);
109 FSTranslatingPortProxy
&vp
= tc
->getVirtProxy();
111 if (size
== sizeof(uint64_t)) {
112 // If the argument is even it must be aligned
113 if ((number
% 2) != 0)
115 arg
= vp
.read
<uint64_t>(sp
+
116 (number
-NumArgumentRegs
) * sizeof(uint32_t));
117 // since two 32 bit args == 1 64 bit arg, increment number
120 arg
= vp
.read
<uint32_t>(sp
+
121 (number
-NumArgumentRegs
) * sizeof(uint32_t));
126 panic("getArgument() should always return\n");
130 skipFunction(ThreadContext
*tc
)
132 PCState newPC
= tc
->pcState();
134 newPC
.set(tc
->readIntReg(INTREG_X30
));
136 newPC
.set(tc
->readIntReg(ReturnAddressReg
) & ~ULL(1));
139 CheckerCPU
*checker
= tc
->getCheckerCpuPtr();
141 tc
->pcStateNoRecord(newPC
);
148 copyRegs(ThreadContext
*src
, ThreadContext
*dest
)
150 for (int i
= 0; i
< NumIntRegs
; i
++)
151 dest
->setIntRegFlat(i
, src
->readIntRegFlat(i
));
153 for (int i
= 0; i
< NumFloatRegs
; i
++)
154 dest
->setFloatRegFlat(i
, src
->readFloatRegFlat(i
));
156 for (int i
= 0; i
< NumCCRegs
; i
++)
157 dest
->setCCReg(i
, src
->readCCReg(i
));
159 for (int i
= 0; i
< NumMiscRegs
; i
++)
160 dest
->setMiscRegNoEffect(i
, src
->readMiscRegNoEffect(i
));
162 // setMiscReg "with effect" will set the misc register mapping correctly.
163 // e.g. updateRegMap(val)
164 dest
->setMiscReg(MISCREG_CPSR
, src
->readMiscRegNoEffect(MISCREG_CPSR
));
166 // Copy over the PC State
167 dest
->pcState(src
->pcState());
169 // Invalidate the tlb misc register cache
170 dest
->getITBPtr()->invalidateMiscReg();
171 dest
->getDTBPtr()->invalidateMiscReg();
175 inSecureState(ThreadContext
*tc
)
177 SCR scr
= inAArch64(tc
) ? tc
->readMiscReg(MISCREG_SCR_EL3
) :
178 tc
->readMiscReg(MISCREG_SCR
);
179 return ArmSystem::haveSecurity(tc
) && inSecureState(
180 scr
, tc
->readMiscReg(MISCREG_CPSR
));
184 inAArch64(ThreadContext
*tc
)
186 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
187 return opModeIs64((OperatingMode
) (uint8_t) cpsr
.mode
);
191 longDescFormatInUse(ThreadContext
*tc
)
193 TTBCR ttbcr
= tc
->readMiscReg(MISCREG_TTBCR
);
194 return ArmSystem::haveLPAE(tc
) && ttbcr
.eae
;
198 getMPIDR(ArmSystem
*arm_sys
, ThreadContext
*tc
)
200 // Multiprocessor Affinity Register MPIDR from Cortex(tm)-A15 Technical
203 // bit 31 - Multi-processor extensions available
204 // bit 30 - Uni-processor system
205 // bit 24 - Multi-threaded cores
206 // bit 11-8 - Cluster ID
209 // We deliberately extend both the Cluster ID and CPU ID fields to allow
210 // for simulation of larger systems
211 assert((0 <= tc
->cpuId()) && (tc
->cpuId() < 256));
212 assert(tc
->socketId() < 65536);
213 if (arm_sys
->multiThread
) {
214 return 0x80000000 | // multiprocessor extensions available
216 } else if (arm_sys
->multiProc
) {
217 return 0x80000000 | // multiprocessor extensions available
218 tc
->cpuId() | tc
->socketId() << 8;
220 return 0x80000000 | // multiprocessor extensions available
221 0x40000000 | // in up system
222 tc
->cpuId() | tc
->socketId() << 8;
227 ELIs64(ThreadContext
*tc
, ExceptionLevel el
)
229 if (ArmSystem::highestEL(tc
) == el
)
230 // Register width is hard-wired
231 return ArmSystem::highestELIs64(tc
);
235 return opModeIs64(currOpMode(tc
));
238 // @todo: uncomment this to enable Virtualization
239 // if (ArmSystem::haveVirtualization(tc)) {
240 // HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
243 assert(ArmSystem::haveSecurity(tc
));
244 SCR scr
= tc
->readMiscReg(MISCREG_SCR_EL3
);
249 assert(ArmSystem::haveSecurity(tc
));
250 SCR scr
= tc
->readMiscReg(MISCREG_SCR_EL3
);
254 panic("Invalid exception level");
260 isBigEndian64(ThreadContext
*tc
)
262 switch (opModeToEL(currOpMode(tc
))) {
264 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL3
)).ee
;
266 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL2
)).ee
;
268 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL1
)).ee
;
270 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL1
)).e0e
;
272 panic("Invalid exception level");
278 purifyTaggedAddr(Addr addr
, ThreadContext
*tc
, ExceptionLevel el
,
284 if (bits(addr
, 55, 48) == 0xFF && tcr
.tbi1
)
285 return addr
| mask(63, 55);
286 else if (!bits(addr
, 55, 48) && tcr
.tbi0
)
287 return bits(addr
,55, 0);
289 // @todo: uncomment this to enable Virtualization
291 // assert(ArmSystem::haveVirtualization());
292 // tcr = tc->readMiscReg(MISCREG_TCR_EL2);
294 // return addr & mask(56);
297 assert(ArmSystem::haveSecurity(tc
));
299 return addr
& mask(56);
302 panic("Invalid exception level");
306 return addr
; // Nothing to do if this is not a tagged address
310 purifyTaggedAddr(Addr addr
, ThreadContext
*tc
, ExceptionLevel el
)
317 tcr
= tc
->readMiscReg(MISCREG_TCR_EL1
);
318 if (bits(addr
, 55, 48) == 0xFF && tcr
.tbi1
)
319 return addr
| mask(63, 55);
320 else if (!bits(addr
, 55, 48) && tcr
.tbi0
)
321 return bits(addr
,55, 0);
323 // @todo: uncomment this to enable Virtualization
325 // assert(ArmSystem::haveVirtualization());
326 // tcr = tc->readMiscReg(MISCREG_TCR_EL2);
328 // return addr & mask(56);
331 assert(ArmSystem::haveSecurity(tc
));
332 tcr
= tc
->readMiscReg(MISCREG_TCR_EL3
);
334 return addr
& mask(56);
337 panic("Invalid exception level");
341 return addr
; // Nothing to do if this is not a tagged address
347 return addr
& ~(PageBytes
- 1);
353 return (addr
+ PageBytes
- 1) & ~(PageBytes
- 1);
357 mcrMrc15TrapToHyp(const MiscRegIndex miscReg
, HCR hcr
, CPSR cpsr
, SCR scr
,
358 HDCR hdcr
, HSTR hstr
, HCPTR hcptr
, uint32_t iss
)
366 bool trapToHype
= false;
369 if (!inSecureState(scr
, cpsr
) && (cpsr
.mode
!= MODE_HYP
)) {
370 mcrMrcIssExtract(iss
, isRead
, crm
, rt
, crn
, opc1
, opc2
);
371 trapToHype
= ((uint32_t) hstr
) & (1 << crn
);
372 trapToHype
|= hdcr
.tpm
&& (crn
== 9) && (crm
>= 12);
373 trapToHype
|= hcr
.tidcp
&& (
374 ((crn
== 9) && ((crm
<= 2) || ((crm
>= 5) && (crm
<= 8)))) ||
375 ((crn
== 10) && ((crm
<= 1) || (crm
== 4) || (crm
== 8))) ||
376 ((crn
== 11) && ((crm
<= 8) || (crm
== 15))) );
379 switch (unflattenMiscReg(miscReg
)) {
381 trapToHype
= hcptr
.tcpac
;
387 trapToHype
= hcr
.tid1
;
393 trapToHype
= hcr
.tid2
;
395 case MISCREG_ID_PFR0
:
396 case MISCREG_ID_PFR1
:
397 case MISCREG_ID_DFR0
:
398 case MISCREG_ID_AFR0
:
399 case MISCREG_ID_MMFR0
:
400 case MISCREG_ID_MMFR1
:
401 case MISCREG_ID_MMFR2
:
402 case MISCREG_ID_MMFR3
:
403 case MISCREG_ID_ISAR0
:
404 case MISCREG_ID_ISAR1
:
405 case MISCREG_ID_ISAR2
:
406 case MISCREG_ID_ISAR3
:
407 case MISCREG_ID_ISAR4
:
408 case MISCREG_ID_ISAR5
:
409 trapToHype
= hcr
.tid3
;
414 trapToHype
= hcr
.tsw
;
416 case MISCREG_DCIMVAC
:
417 case MISCREG_DCCIMVAC
:
418 case MISCREG_DCCMVAC
:
419 trapToHype
= hcr
.tpc
;
421 case MISCREG_ICIMVAU
:
422 case MISCREG_ICIALLU
:
423 case MISCREG_ICIALLUIS
:
424 case MISCREG_DCCMVAU
:
425 trapToHype
= hcr
.tpu
;
427 case MISCREG_TLBIALLIS
:
428 case MISCREG_TLBIMVAIS
:
429 case MISCREG_TLBIASIDIS
:
430 case MISCREG_TLBIMVAAIS
:
431 case MISCREG_DTLBIALL
:
432 case MISCREG_ITLBIALL
:
433 case MISCREG_DTLBIMVA
:
434 case MISCREG_ITLBIMVA
:
435 case MISCREG_DTLBIASID
:
436 case MISCREG_ITLBIASID
:
437 case MISCREG_TLBIMVAA
:
438 case MISCREG_TLBIALL
:
439 case MISCREG_TLBIMVA
:
440 case MISCREG_TLBIASID
:
441 trapToHype
= hcr
.ttlb
;
444 trapToHype
= hcr
.tac
;
461 case MISCREG_CONTEXTIDR
:
462 trapToHype
= hcr
.tvm
& !isRead
;
465 trapToHype
= hdcr
.tpmcr
;
467 // No default action needed
478 mcrMrc14TrapToHyp(const MiscRegIndex miscReg
, HCR hcr
, CPSR cpsr
, SCR scr
,
479 HDCR hdcr
, HSTR hstr
, HCPTR hcptr
, uint32_t iss
)
487 bool trapToHype
= false;
489 if (!inSecureState(scr
, cpsr
) && (cpsr
.mode
!= MODE_HYP
)) {
490 mcrMrcIssExtract(iss
, isRead
, crm
, rt
, crn
, opc1
, opc2
);
491 inform("trap check M:%x N:%x 1:%x 2:%x hdcr %x, hcptr %x, hstr %x\n",
492 crm
, crn
, opc1
, opc2
, hdcr
, hcptr
, hstr
);
493 trapToHype
= hdcr
.tda
&& (opc1
== 0);
494 trapToHype
|= hcptr
.tta
&& (opc1
== 1);
496 switch (unflattenMiscReg(miscReg
)) {
497 case MISCREG_DBGOSLSR
:
498 case MISCREG_DBGOSLAR
:
499 case MISCREG_DBGOSDLR
:
500 case MISCREG_DBGPRCR
:
501 trapToHype
= hdcr
.tdosa
;
503 case MISCREG_DBGDRAR
:
504 case MISCREG_DBGDSAR
:
505 trapToHype
= hdcr
.tdra
;
508 trapToHype
= hcr
.tid0
;
512 trapToHype
= hstr
.tjdbx
;
516 trapToHype
= hstr
.ttee
;
518 // No default action needed
528 mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg
, CPSR cpsr
, SCR scr
, HSTR hstr
,
529 HCR hcr
, uint32_t iss
)
537 bool trapToHype
= false;
539 if (!inSecureState(scr
, cpsr
) && (cpsr
.mode
!= MODE_HYP
)) {
540 // This is technically the wrong function, but we can re-use it for
541 // the moment because we only need one field, which overlaps with the
543 mcrMrcIssExtract(iss
, isRead
, crm
, rt
, crn
, opc1
, opc2
);
544 trapToHype
= ((uint32_t) hstr
) & (1 << crm
);
547 switch (unflattenMiscReg(miscReg
)) {
563 case MISCREG_CONTEXTIDR
:
564 trapToHype
= hcr
.tvm
& !isRead
;
566 // No default action needed
576 msrMrs64TrapToSup(const MiscRegIndex miscReg
, ExceptionLevel el
,
577 CPACR cpacr
/* CPACR_EL1 */)
579 bool trapToSup
= false;
583 case MISCREG_FPEXC32_EL2
:
584 if ((el
== EL0
&& cpacr
.fpen
!= 0x3) ||
585 (el
== EL1
&& !(cpacr
.fpen
& 0x1)))
595 msrMrs64TrapToHyp(const MiscRegIndex miscReg
, bool isRead
,
596 CPTR cptr
/* CPTR_EL2 */,
597 HCR hcr
/* HCR_EL2 */,
600 bool trapToHyp
= false;
607 case MISCREG_FPEXC32_EL2
:
608 trapToHyp
= cptr
.tfp
;
612 case MISCREG_CPACR_EL1
:
613 trapToHyp
= cptr
.tcpac
;
615 // Virtual memory control regs
616 case MISCREG_SCTLR_EL1
:
617 case MISCREG_TTBR0_EL1
:
618 case MISCREG_TTBR1_EL1
:
619 case MISCREG_TCR_EL1
:
620 case MISCREG_ESR_EL1
:
621 case MISCREG_FAR_EL1
:
622 case MISCREG_AFSR0_EL1
:
623 case MISCREG_AFSR1_EL1
:
624 case MISCREG_MAIR_EL1
:
625 case MISCREG_AMAIR_EL1
:
626 case MISCREG_CONTEXTIDR_EL1
:
627 trapToHyp
= (hcr
.trvm
&& isRead
) || (hcr
.tvm
&& !isRead
);
629 // TLB maintenance instructions
630 case MISCREG_TLBI_VMALLE1
:
631 case MISCREG_TLBI_VAE1_Xt
:
632 case MISCREG_TLBI_ASIDE1_Xt
:
633 case MISCREG_TLBI_VAAE1_Xt
:
634 case MISCREG_TLBI_VALE1_Xt
:
635 case MISCREG_TLBI_VAALE1_Xt
:
636 case MISCREG_TLBI_VMALLE1IS
:
637 case MISCREG_TLBI_VAE1IS_Xt
:
638 case MISCREG_TLBI_ASIDE1IS_Xt
:
639 case MISCREG_TLBI_VAAE1IS_Xt
:
640 case MISCREG_TLBI_VALE1IS_Xt
:
641 case MISCREG_TLBI_VAALE1IS_Xt
:
642 trapToHyp
= hcr
.ttlb
;
644 // Cache maintenance instructions to the point of unification
645 case MISCREG_IC_IVAU_Xt
:
646 case MISCREG_ICIALLU
:
647 case MISCREG_ICIALLUIS
:
648 case MISCREG_DC_CVAU_Xt
:
651 // Data/Unified cache maintenance instructions to the point of coherency
652 case MISCREG_DC_IVAC_Xt
:
653 case MISCREG_DC_CIVAC_Xt
:
654 case MISCREG_DC_CVAC_Xt
:
657 // Data/Unified cache maintenance instructions by set/way
658 case MISCREG_DC_ISW_Xt
:
659 case MISCREG_DC_CSW_Xt
:
660 case MISCREG_DC_CISW_Xt
:
664 case MISCREG_ACTLR_EL1
:
665 trapToHyp
= hcr
.tacr
;
668 // @todo: Trap implementation-dependent functionality based on
672 case MISCREG_ID_PFR0_EL1
:
673 case MISCREG_ID_PFR1_EL1
:
674 case MISCREG_ID_DFR0_EL1
:
675 case MISCREG_ID_AFR0_EL1
:
676 case MISCREG_ID_MMFR0_EL1
:
677 case MISCREG_ID_MMFR1_EL1
:
678 case MISCREG_ID_MMFR2_EL1
:
679 case MISCREG_ID_MMFR3_EL1
:
680 case MISCREG_ID_ISAR0_EL1
:
681 case MISCREG_ID_ISAR1_EL1
:
682 case MISCREG_ID_ISAR2_EL1
:
683 case MISCREG_ID_ISAR3_EL1
:
684 case MISCREG_ID_ISAR4_EL1
:
685 case MISCREG_ID_ISAR5_EL1
:
686 case MISCREG_MVFR0_EL1
:
687 case MISCREG_MVFR1_EL1
:
688 case MISCREG_MVFR2_EL1
:
689 case MISCREG_ID_AA64PFR0_EL1
:
690 case MISCREG_ID_AA64PFR1_EL1
:
691 case MISCREG_ID_AA64DFR0_EL1
:
692 case MISCREG_ID_AA64DFR1_EL1
:
693 case MISCREG_ID_AA64ISAR0_EL1
:
694 case MISCREG_ID_AA64ISAR1_EL1
:
695 case MISCREG_ID_AA64MMFR0_EL1
:
696 case MISCREG_ID_AA64MMFR1_EL1
:
697 case MISCREG_ID_AA64AFR0_EL1
:
698 case MISCREG_ID_AA64AFR1_EL1
:
700 trapToHyp
= hcr
.tid3
;
703 case MISCREG_CTR_EL0
:
704 case MISCREG_CCSIDR_EL1
:
705 case MISCREG_CLIDR_EL1
:
706 case MISCREG_CSSELR_EL1
:
707 trapToHyp
= hcr
.tid2
;
710 case MISCREG_AIDR_EL1
:
711 case MISCREG_REVIDR_EL1
:
713 trapToHyp
= hcr
.tid1
;
722 msrMrs64TrapToMon(const MiscRegIndex miscReg
, CPTR cptr
/* CPTR_EL3 */,
723 ExceptionLevel el
, bool * isVfpNeon
)
725 bool trapToMon
= false;
732 case MISCREG_FPEXC32_EL2
:
733 trapToMon
= cptr
.tfp
;
737 case MISCREG_CPACR_EL1
:
739 trapToMon
= cptr
.tcpac
;
742 case MISCREG_CPTR_EL2
:
744 trapToMon
= cptr
.tcpac
;
754 decodeMrsMsrBankedReg(uint8_t sysM
, bool r
, bool &isIntReg
, int ®Idx
,
755 CPSR cpsr
, SCR scr
, NSACR nsacr
, bool checkSecurity
)
757 OperatingMode mode
= MODE_UNDEFINED
;
760 // R mostly indicates if its a int register or a misc reg, we override
761 // below if the few corner cases
763 // Loosely based on ARM ARM issue C section B9.3.10
768 regIdx
= MISCREG_SPSR_FIQ
;
772 regIdx
= MISCREG_SPSR_IRQ
;
776 regIdx
= MISCREG_SPSR_SVC
;
780 regIdx
= MISCREG_SPSR_ABT
;
784 regIdx
= MISCREG_SPSR_UND
;
785 mode
= MODE_UNDEFINED
;
788 regIdx
= MISCREG_SPSR_MON
;
792 regIdx
= MISCREG_SPSR_HYP
;
800 int sysM4To3
= bits(sysM
, 4, 3);
804 regIdx
= intRegInMode(mode
, bits(sysM
, 2, 0) + 8);
805 } else if (sysM4To3
== 1) {
807 regIdx
= intRegInMode(mode
, bits(sysM
, 2, 0) + 8);
808 } else if (sysM4To3
== 3) {
809 if (bits(sysM
, 1) == 0) {
811 regIdx
= intRegInMode(mode
, 14 - bits(sysM
, 0));
814 if (bits(sysM
, 0) == 1) {
815 regIdx
= intRegInMode(mode
, 13); // R13 in HYP
818 regIdx
= MISCREG_ELR_HYP
;
821 } else { // Other Banked registers
822 int sysM2
= bits(sysM
, 2);
823 int sysM1
= bits(sysM
, 1);
825 mode
= (OperatingMode
) ( ((sysM2
|| sysM1
) << 0) |
827 ((sysM2
&& !sysM1
) << 2) |
828 ((sysM2
&& sysM1
) << 3) |
830 regIdx
= intRegInMode(mode
, 14 - bits(sysM
, 0));
831 // Don't flatten the register here. This is going to go through
832 // setIntReg() which will do the flattening
833 ok
&= mode
!= cpsr
.mode
;
837 // Check that the requested register is accessable from the current mode
838 if (ok
&& checkSecurity
&& mode
!= cpsr
.mode
) {
845 ok
&= mode
!= MODE_HYP
;
846 ok
&= (mode
!= MODE_MON
) || !scr
.ns
;
849 ok
&= mode
!= MODE_MON
;
850 ok
&= (mode
!= MODE_FIQ
) || !nsacr
.rfr
;
857 ok
&= mode
!= MODE_HYP
;
858 ok
&= (mode
!= MODE_MON
) || !scr
.ns
;
859 ok
&= (mode
!= MODE_FIQ
) || !nsacr
.rfr
;
861 // can access everything, no further checks required
865 panic("unknown Mode 0x%x\n", cpsr
.mode
);
873 vfpNeonEnabled(uint32_t &seq
, HCPTR hcptr
, NSACR nsacr
, CPACR cpacr
, CPSR cpsr
,
874 uint32_t &iss
, bool &trap
, ThreadContext
*tc
, FPEXC fpexc
,
879 bool undefined
= false;
880 bool haveSecurity
= ArmSystem::haveSecurity(tc
);
881 bool haveVirtualization
= ArmSystem::haveVirtualization(tc
);
882 bool isSecure
= inSecureState(tc
);
884 // Non-secure view of CPACR and HCPTR determines behavior
885 // Copy register values
886 uint8_t cpacr_cp10
= cpacr
.cp10
;
887 bool cpacr_asedis
= cpacr
.asedis
;
888 bool hcptr_cp10
= false;
889 bool hcptr_tase
= false;
891 bool cp10_enabled
= cpacr
.cp10
== 0x3
892 || (cpacr
.cp10
== 0x1 && inPrivilegedMode(cpsr
));
894 bool cp11_enabled
= cpacr
.cp11
== 0x3
895 || (cpacr
.cp11
== 0x1 && inPrivilegedMode(cpsr
));
898 undefined
|= !(fpexc
.en
&& cp10_enabled
);
900 undefined
|= !(fpexc
.en
&& cp10_enabled
&& (cpacr
.cp11
== cpacr
.cp10
));
903 if (haveVirtualization
) {
904 hcptr_cp10
= hcptr
.tcp10
;
905 undefined
|= hcptr
.tcp10
!= hcptr
.tcp11
;
906 hcptr_tase
= hcptr
.tase
;
910 undefined
|= nsacr
.cp10
!= nsacr
.cp11
;
912 // Modify register values to the Non-secure view
915 if (haveVirtualization
) {
919 if (nsacr
.nsasedis
) {
921 if (haveVirtualization
) {
928 // Check Coprocessor Access Control Register for permission to use CP10/11.
929 if (!haveVirtualization
|| (cpsr
.mode
!= MODE_HYP
)) {
936 undefined
|= inUserMode(cpsr
);
940 // Check if SIMD operations are disabled
941 if (isSIMD
&& cpacr_asedis
) undefined
= true;
944 // If required, check FPEXC enabled bit.
945 undefined
|= !fpexc
.en
;
947 if (haveSecurity
&& haveVirtualization
&& !isSecure
) {
948 if (hcptr_cp10
|| (isSIMD
&& hcptr_tase
)) {
949 iss
= isSIMD
? (1 << 5) : 0xA;
958 SPAlignmentCheckEnabled(ThreadContext
* tc
)
960 switch (opModeToEL(currOpMode(tc
))) {
962 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL3
)).sa
;
964 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL2
)).sa
;
966 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL1
)).sa
;
968 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL1
)).sa0
;
970 panic("Invalid exception level");
976 decodePhysAddrRange64(uint8_t pa_enc
)
994 panic("Invalid phys. address range encoding");
999 encodePhysAddrRange64(int pa_size
)
1015 panic("Invalid phys. address range");
1019 } // namespace ArmISA