2 * Copyright (c) 2009-2014, 2016-2019 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include "arch/arm/utility.hh"
44 #include "arch/arm/faults.hh"
45 #include "arch/arm/isa_traits.hh"
46 #include "arch/arm/system.hh"
47 #include "arch/arm/tlb.hh"
48 #include "arch/arm/vtophys.hh"
49 #include "cpu/base.hh"
50 #include "cpu/checker/cpu.hh"
51 #include "cpu/thread_context.hh"
52 #include "mem/fs_translating_port_proxy.hh"
53 #include "sim/full_system.hh"
58 initCPU(ThreadContext
*tc
, int cpuId
)
60 // Reset CP15?? What does that mean -- ali
64 static Fault reset
= std::make_shared
<Reset
>();
69 getArgument(ThreadContext
*tc
, int &number
, uint16_t size
, bool fp
)
72 panic("getArgument() only implemented for full system mode.\n");
77 panic("getArgument(): Floating point arguments not implemented\n");
80 if (size
== (uint16_t)(-1))
81 size
= sizeof(uint64_t);
83 if (number
< 8 /*NumArgumentRegs64*/) {
84 return tc
->readIntReg(number
);
86 panic("getArgument(): No support reading stack args for AArch64\n");
89 if (size
== (uint16_t)(-1))
90 // todo: should this not be sizeof(uint32_t) rather?
91 size
= ArmISA::MachineBytes
;
93 if (number
< NumArgumentRegs
) {
94 // If the argument is 64 bits, it must be in an even regiser
95 // number. Increment the number here if it isn't even.
96 if (size
== sizeof(uint64_t)) {
97 if ((number
% 2) != 0)
99 // Read the two halves of the data. Number is inc here to
100 // get the second half of the 64 bit reg.
102 tmp
= tc
->readIntReg(number
++);
103 tmp
|= tc
->readIntReg(number
) << 32;
106 return tc
->readIntReg(number
);
109 Addr sp
= tc
->readIntReg(StackPointerReg
);
110 PortProxy
&vp
= tc
->getVirtProxy();
112 if (size
== sizeof(uint64_t)) {
113 // If the argument is even it must be aligned
114 if ((number
% 2) != 0)
116 arg
= vp
.read
<uint64_t>(sp
+
117 (number
-NumArgumentRegs
) * sizeof(uint32_t));
118 // since two 32 bit args == 1 64 bit arg, increment number
121 arg
= vp
.read
<uint32_t>(sp
+
122 (number
-NumArgumentRegs
) * sizeof(uint32_t));
127 panic("getArgument() should always return\n");
131 skipFunction(ThreadContext
*tc
)
133 PCState newPC
= tc
->pcState();
135 newPC
.set(tc
->readIntReg(INTREG_X30
));
137 newPC
.set(tc
->readIntReg(ReturnAddressReg
) & ~ULL(1));
140 CheckerCPU
*checker
= tc
->getCheckerCpuPtr();
142 tc
->pcStateNoRecord(newPC
);
149 copyVecRegs(ThreadContext
*src
, ThreadContext
*dest
)
151 auto src_mode
= RenameMode
<ArmISA::ISA
>::mode(src
->pcState());
153 // The way vector registers are copied (VecReg vs VecElem) is relevant
154 // in the O3 model only.
155 if (src_mode
== Enums::Full
) {
156 for (auto idx
= 0; idx
< NumVecRegs
; idx
++)
157 dest
->setVecRegFlat(idx
, src
->readVecRegFlat(idx
));
159 for (auto idx
= 0; idx
< NumVecRegs
; idx
++)
160 for (auto elem_idx
= 0; elem_idx
< NumVecElemPerVecReg
; elem_idx
++)
161 dest
->setVecElemFlat(
162 idx
, elem_idx
, src
->readVecElemFlat(idx
, elem_idx
));
167 copyRegs(ThreadContext
*src
, ThreadContext
*dest
)
169 for (int i
= 0; i
< NumIntRegs
; i
++)
170 dest
->setIntRegFlat(i
, src
->readIntRegFlat(i
));
172 for (int i
= 0; i
< NumFloatRegs
; i
++)
173 dest
->setFloatRegFlat(i
, src
->readFloatRegFlat(i
));
175 for (int i
= 0; i
< NumCCRegs
; i
++)
176 dest
->setCCReg(i
, src
->readCCReg(i
));
178 for (int i
= 0; i
< NumMiscRegs
; i
++)
179 dest
->setMiscRegNoEffect(i
, src
->readMiscRegNoEffect(i
));
181 copyVecRegs(src
, dest
);
183 // setMiscReg "with effect" will set the misc register mapping correctly.
184 // e.g. updateRegMap(val)
185 dest
->setMiscReg(MISCREG_CPSR
, src
->readMiscRegNoEffect(MISCREG_CPSR
));
187 // Copy over the PC State
188 dest
->pcState(src
->pcState());
190 // Invalidate the tlb misc register cache
191 dynamic_cast<TLB
*>(dest
->getITBPtr())->invalidateMiscReg();
192 dynamic_cast<TLB
*>(dest
->getDTBPtr())->invalidateMiscReg();
196 inSecureState(ThreadContext
*tc
)
198 SCR scr
= inAArch64(tc
) ? tc
->readMiscReg(MISCREG_SCR_EL3
) :
199 tc
->readMiscReg(MISCREG_SCR
);
200 return ArmSystem::haveSecurity(tc
) && inSecureState(
201 scr
, tc
->readMiscReg(MISCREG_CPSR
));
205 isSecureBelowEL3(ThreadContext
*tc
)
207 SCR scr
= tc
->readMiscReg(MISCREG_SCR_EL3
);
208 return ArmSystem::haveEL(tc
, EL3
) && scr
.ns
== 0;
212 inAArch64(ThreadContext
*tc
)
214 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
215 return opModeIs64((OperatingMode
) (uint8_t) cpsr
.mode
);
219 longDescFormatInUse(ThreadContext
*tc
)
221 TTBCR ttbcr
= tc
->readMiscReg(MISCREG_TTBCR
);
222 return ArmSystem::haveLPAE(tc
) && ttbcr
.eae
;
226 readMPIDR(ArmSystem
*arm_sys
, ThreadContext
*tc
)
228 const ExceptionLevel current_el
= currEL(tc
);
230 const bool is_secure
= isSecureBelowEL3(tc
);
232 switch (current_el
) {
234 // Note: in MsrMrs instruction we read the register value before
235 // checking access permissions. This means that EL0 entry must
236 // be part of the table even if MPIDR is not accessible in user
238 warn_once("Trying to read MPIDR at EL0\n");
241 if (ArmSystem::haveEL(tc
, EL2
) && !is_secure
)
242 return tc
->readMiscReg(MISCREG_VMPIDR_EL2
);
244 return getMPIDR(arm_sys
, tc
);
247 return getMPIDR(arm_sys
, tc
);
249 panic("Invalid EL for reading MPIDR register\n");
254 getMPIDR(ArmSystem
*arm_sys
, ThreadContext
*tc
)
256 // Multiprocessor Affinity Register MPIDR from Cortex(tm)-A15 Technical
259 // bit 31 - Multi-processor extensions available
260 // bit 30 - Uni-processor system
261 // bit 24 - Multi-threaded cores
262 // bit 11-8 - Cluster ID
265 // We deliberately extend both the Cluster ID and CPU ID fields to allow
266 // for simulation of larger systems
267 assert((0 <= tc
->cpuId()) && (tc
->cpuId() < 256));
268 assert(tc
->socketId() < 65536);
269 if (arm_sys
->multiThread
) {
270 return 0x80000000 | // multiprocessor extensions available
271 0x01000000 | // multi-threaded cores
273 } else if (arm_sys
->multiProc
) {
274 return 0x80000000 | // multiprocessor extensions available
275 tc
->cpuId() | tc
->socketId() << 8;
277 return 0x80000000 | // multiprocessor extensions available
278 0x40000000 | // in up system
279 tc
->cpuId() | tc
->socketId() << 8;
284 ELIs64(ThreadContext
*tc
, ExceptionLevel el
)
286 return !ELIs32(tc
, el
);
290 ELIs32(ThreadContext
*tc
, ExceptionLevel el
)
293 std::tie(known
, aarch32
) = ELUsingAArch32K(tc
, el
);
294 panic_if(!known
, "EL state is UNKNOWN");
299 ELIsInHost(ThreadContext
*tc
, ExceptionLevel el
)
301 if (!ArmSystem::haveVirtualization(tc
)) {
304 HCR hcr
= tc
->readMiscReg(MISCREG_HCR_EL2
);
305 return (!isSecureBelowEL3(tc
) && !ELIs32(tc
, EL2
) && hcr
.e2h
== 1 &&
306 (el
== EL2
|| (el
== EL0
&& hcr
.tge
== 1)));
309 std::pair
<bool, bool>
310 ELUsingAArch32K(ThreadContext
*tc
, ExceptionLevel el
)
312 // Return true if the specified EL is in aarch32 state.
313 const bool have_el3
= ArmSystem::haveSecurity(tc
);
314 const bool have_el2
= ArmSystem::haveVirtualization(tc
);
316 panic_if(el
== EL2
&& !have_el2
, "Asking for EL2 when it doesn't exist");
317 panic_if(el
== EL3
&& !have_el3
, "Asking for EL3 when it doesn't exist");
320 known
= aarch32
= false;
321 if (ArmSystem::highestELIs64(tc
) && ArmSystem::highestEL(tc
) == el
) {
322 // Target EL is the highest one in a system where
323 // the highest is using AArch64.
324 known
= true; aarch32
= false;
325 } else if (!ArmSystem::highestELIs64(tc
)) {
326 // All ELs are using AArch32:
327 known
= true; aarch32
= true;
329 SCR scr
= tc
->readMiscReg(MISCREG_SCR_EL3
);
330 bool aarch32_below_el3
= (have_el3
&& scr
.rw
== 0);
332 HCR hcr
= tc
->readMiscReg(MISCREG_HCR_EL2
);
333 bool aarch32_at_el1
= (aarch32_below_el3
335 && !isSecureBelowEL3(tc
) && hcr
.rw
== 0));
337 // Only know if EL0 using AArch32 from PSTATE
338 if (el
== EL0
&& !aarch32_at_el1
) {
339 // EL0 controlled by PSTATE
340 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
342 known
= (currEL(tc
) == EL0
);
343 aarch32
= (cpsr
.width
== 1);
346 aarch32
= (aarch32_below_el3
&& el
!= EL3
)
347 || (aarch32_at_el1
&& (el
== EL0
|| el
== EL1
) );
351 return std::make_pair(known
, aarch32
);
355 isBigEndian64(ThreadContext
*tc
)
357 switch (currEL(tc
)) {
359 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL3
)).ee
;
361 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL2
)).ee
;
363 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL1
)).ee
;
365 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL1
)).e0e
;
367 panic("Invalid exception level");
373 badMode32(ThreadContext
*tc
, OperatingMode mode
)
375 return unknownMode32(mode
) || !ArmSystem::haveEL(tc
, opModeToEL(mode
));
379 badMode(ThreadContext
*tc
, OperatingMode mode
)
381 return unknownMode(mode
) || !ArmSystem::haveEL(tc
, opModeToEL(mode
));
385 purifyTaggedAddr(Addr addr
, ThreadContext
*tc
, ExceptionLevel el
,
391 if (bits(addr
, 55, 48) == 0xFF && tcr
.tbi1
)
392 return addr
| mask(63, 55);
393 else if (!bits(addr
, 55, 48) && tcr
.tbi0
)
394 return bits(addr
,55, 0);
397 assert(ArmSystem::haveVirtualization(tc
));
398 tcr
= tc
->readMiscReg(MISCREG_TCR_EL2
);
400 return addr
& mask(56);
403 assert(ArmSystem::haveSecurity(tc
));
405 return addr
& mask(56);
408 panic("Invalid exception level");
412 return addr
; // Nothing to do if this is not a tagged address
416 purifyTaggedAddr(Addr addr
, ThreadContext
*tc
, ExceptionLevel el
)
423 tcr
= tc
->readMiscReg(MISCREG_TCR_EL1
);
424 if (bits(addr
, 55, 48) == 0xFF && tcr
.tbi1
)
425 return addr
| mask(63, 55);
426 else if (!bits(addr
, 55, 48) && tcr
.tbi0
)
427 return bits(addr
,55, 0);
430 assert(ArmSystem::haveVirtualization(tc
));
431 tcr
= tc
->readMiscReg(MISCREG_TCR_EL2
);
433 return addr
& mask(56);
436 assert(ArmSystem::haveSecurity(tc
));
437 tcr
= tc
->readMiscReg(MISCREG_TCR_EL3
);
439 return addr
& mask(56);
442 panic("Invalid exception level");
446 return addr
; // Nothing to do if this is not a tagged address
452 return addr
& ~(PageBytes
- 1);
458 return (addr
+ PageBytes
- 1) & ~(PageBytes
- 1);
462 mcrMrc15TrapToHyp(const MiscRegIndex miscReg
, ThreadContext
*tc
, uint32_t iss
)
470 bool trapToHype
= false;
472 const CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
473 const HCR hcr
= tc
->readMiscReg(MISCREG_HCR
);
474 const SCR scr
= tc
->readMiscReg(MISCREG_SCR
);
475 const HDCR hdcr
= tc
->readMiscReg(MISCREG_HDCR
);
476 const HSTR hstr
= tc
->readMiscReg(MISCREG_HSTR
);
477 const HCPTR hcptr
= tc
->readMiscReg(MISCREG_HCPTR
);
479 if (!inSecureState(scr
, cpsr
) && (cpsr
.mode
!= MODE_HYP
)) {
480 mcrMrcIssExtract(iss
, isRead
, crm
, rt
, crn
, opc1
, opc2
);
481 trapToHype
= ((uint32_t) hstr
) & (1 << crn
);
482 trapToHype
|= hdcr
.tpm
&& (crn
== 9) && (crm
>= 12);
483 trapToHype
|= hcr
.tidcp
&& (
484 ((crn
== 9) && ((crm
<= 2) || ((crm
>= 5) && (crm
<= 8)))) ||
485 ((crn
== 10) && ((crm
<= 1) || (crm
== 4) || (crm
== 8))) ||
486 ((crn
== 11) && ((crm
<= 8) || (crm
== 15))) );
489 switch (unflattenMiscReg(miscReg
)) {
491 trapToHype
= hcptr
.tcpac
;
497 trapToHype
= hcr
.tid1
;
503 trapToHype
= hcr
.tid2
;
505 case MISCREG_ID_PFR0
:
506 case MISCREG_ID_PFR1
:
507 case MISCREG_ID_DFR0
:
508 case MISCREG_ID_AFR0
:
509 case MISCREG_ID_MMFR0
:
510 case MISCREG_ID_MMFR1
:
511 case MISCREG_ID_MMFR2
:
512 case MISCREG_ID_MMFR3
:
513 case MISCREG_ID_ISAR0
:
514 case MISCREG_ID_ISAR1
:
515 case MISCREG_ID_ISAR2
:
516 case MISCREG_ID_ISAR3
:
517 case MISCREG_ID_ISAR4
:
518 case MISCREG_ID_ISAR5
:
519 trapToHype
= hcr
.tid3
;
524 trapToHype
= hcr
.tsw
;
526 case MISCREG_DCIMVAC
:
527 case MISCREG_DCCIMVAC
:
528 case MISCREG_DCCMVAC
:
529 trapToHype
= hcr
.tpc
;
531 case MISCREG_ICIMVAU
:
532 case MISCREG_ICIALLU
:
533 case MISCREG_ICIALLUIS
:
534 case MISCREG_DCCMVAU
:
535 trapToHype
= hcr
.tpu
;
537 case MISCREG_TLBIALLIS
:
538 case MISCREG_TLBIMVAIS
:
539 case MISCREG_TLBIASIDIS
:
540 case MISCREG_TLBIMVAAIS
:
541 case MISCREG_TLBIMVALIS
:
542 case MISCREG_TLBIMVAALIS
:
543 case MISCREG_DTLBIALL
:
544 case MISCREG_ITLBIALL
:
545 case MISCREG_DTLBIMVA
:
546 case MISCREG_ITLBIMVA
:
547 case MISCREG_DTLBIASID
:
548 case MISCREG_ITLBIASID
:
549 case MISCREG_TLBIMVAA
:
550 case MISCREG_TLBIALL
:
551 case MISCREG_TLBIMVA
:
552 case MISCREG_TLBIMVAL
:
553 case MISCREG_TLBIMVAAL
:
554 case MISCREG_TLBIASID
:
555 trapToHype
= hcr
.ttlb
;
558 trapToHype
= hcr
.tac
;
575 case MISCREG_CONTEXTIDR
:
576 trapToHype
= hcr
.tvm
& !isRead
;
579 trapToHype
= hdcr
.tpmcr
;
582 case MISCREG_ICC_SGI0R
:
583 if (tc
->getIsaPtr()->haveGICv3CpuIfc())
584 trapToHype
= hcr
.fmo
;
586 case MISCREG_ICC_SGI1R
:
587 case MISCREG_ICC_ASGI1R
:
588 if (tc
->getIsaPtr()->haveGICv3CpuIfc())
589 trapToHype
= hcr
.imo
;
591 // No default action needed
602 mcrMrc14TrapToHyp(const MiscRegIndex miscReg
, HCR hcr
, CPSR cpsr
, SCR scr
,
603 HDCR hdcr
, HSTR hstr
, HCPTR hcptr
, uint32_t iss
)
611 bool trapToHype
= false;
613 if (!inSecureState(scr
, cpsr
) && (cpsr
.mode
!= MODE_HYP
)) {
614 mcrMrcIssExtract(iss
, isRead
, crm
, rt
, crn
, opc1
, opc2
);
615 inform("trap check M:%x N:%x 1:%x 2:%x hdcr %x, hcptr %x, hstr %x\n",
616 crm
, crn
, opc1
, opc2
, hdcr
, hcptr
, hstr
);
617 trapToHype
= hdcr
.tda
&& (opc1
== 0);
618 trapToHype
|= hcptr
.tta
&& (opc1
== 1);
620 switch (unflattenMiscReg(miscReg
)) {
621 case MISCREG_DBGOSLSR
:
622 case MISCREG_DBGOSLAR
:
623 case MISCREG_DBGOSDLR
:
624 case MISCREG_DBGPRCR
:
625 trapToHype
= hdcr
.tdosa
;
627 case MISCREG_DBGDRAR
:
628 case MISCREG_DBGDSAR
:
629 trapToHype
= hdcr
.tdra
;
632 trapToHype
= hcr
.tid0
;
636 trapToHype
= hstr
.tjdbx
;
640 trapToHype
= hstr
.ttee
;
642 // No default action needed
652 mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg
, CPSR cpsr
, SCR scr
, HSTR hstr
,
653 HCR hcr
, uint32_t iss
)
661 bool trapToHype
= false;
663 if (!inSecureState(scr
, cpsr
) && (cpsr
.mode
!= MODE_HYP
)) {
664 // This is technically the wrong function, but we can re-use it for
665 // the moment because we only need one field, which overlaps with the
667 mcrMrcIssExtract(iss
, isRead
, crm
, rt
, crn
, opc1
, opc2
);
668 trapToHype
= ((uint32_t) hstr
) & (1 << crm
);
671 switch (unflattenMiscReg(miscReg
)) {
687 case MISCREG_CONTEXTIDR
:
688 trapToHype
= hcr
.tvm
& !isRead
;
690 // No default action needed
700 decodeMrsMsrBankedReg(uint8_t sysM
, bool r
, bool &isIntReg
, int ®Idx
,
701 CPSR cpsr
, SCR scr
, NSACR nsacr
, bool checkSecurity
)
703 OperatingMode mode
= MODE_UNDEFINED
;
706 // R mostly indicates if its a int register or a misc reg, we override
707 // below if the few corner cases
709 // Loosely based on ARM ARM issue C section B9.3.10
714 regIdx
= MISCREG_SPSR_FIQ
;
718 regIdx
= MISCREG_SPSR_IRQ
;
722 regIdx
= MISCREG_SPSR_SVC
;
726 regIdx
= MISCREG_SPSR_ABT
;
730 regIdx
= MISCREG_SPSR_UND
;
731 mode
= MODE_UNDEFINED
;
734 regIdx
= MISCREG_SPSR_MON
;
738 regIdx
= MISCREG_SPSR_HYP
;
746 int sysM4To3
= bits(sysM
, 4, 3);
750 regIdx
= intRegInMode(mode
, bits(sysM
, 2, 0) + 8);
751 } else if (sysM4To3
== 1) {
753 regIdx
= intRegInMode(mode
, bits(sysM
, 2, 0) + 8);
754 } else if (sysM4To3
== 3) {
755 if (bits(sysM
, 1) == 0) {
757 regIdx
= intRegInMode(mode
, 14 - bits(sysM
, 0));
760 if (bits(sysM
, 0) == 1) {
761 regIdx
= intRegInMode(mode
, 13); // R13 in HYP
764 regIdx
= MISCREG_ELR_HYP
;
767 } else { // Other Banked registers
768 int sysM2
= bits(sysM
, 2);
769 int sysM1
= bits(sysM
, 1);
771 mode
= (OperatingMode
) ( ((sysM2
|| sysM1
) << 0) |
773 ((sysM2
&& !sysM1
) << 2) |
774 ((sysM2
&& sysM1
) << 3) |
776 regIdx
= intRegInMode(mode
, 14 - bits(sysM
, 0));
777 // Don't flatten the register here. This is going to go through
778 // setIntReg() which will do the flattening
779 ok
&= mode
!= cpsr
.mode
;
783 // Check that the requested register is accessable from the current mode
784 if (ok
&& checkSecurity
&& mode
!= cpsr
.mode
) {
791 ok
&= mode
!= MODE_HYP
;
792 ok
&= (mode
!= MODE_MON
) || !scr
.ns
;
795 ok
&= mode
!= MODE_MON
;
796 ok
&= (mode
!= MODE_FIQ
) || !nsacr
.rfr
;
803 ok
&= mode
!= MODE_HYP
;
804 ok
&= (mode
!= MODE_MON
) || !scr
.ns
;
805 ok
&= (mode
!= MODE_FIQ
) || !nsacr
.rfr
;
807 // can access everything, no further checks required
811 panic("unknown Mode 0x%x\n", cpsr
.mode
);
819 SPAlignmentCheckEnabled(ThreadContext
* tc
)
821 switch (currEL(tc
)) {
823 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL3
)).sa
;
825 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL2
)).sa
;
827 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL1
)).sa
;
829 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL1
)).sa0
;
831 panic("Invalid exception level");
837 decodePhysAddrRange64(uint8_t pa_enc
)
855 panic("Invalid phys. address range encoding");
860 encodePhysAddrRange64(int pa_size
)
876 panic("Invalid phys. address range");
880 } // namespace ArmISA