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arch-arm: Virtualization Host Extensions checking
[gem5.git] / src / arch / arm / utility.cc
1 /*
2 * Copyright (c) 2009-2014, 2016-2019 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40 #include "arch/arm/utility.hh"
41
42 #include <memory>
43
44 #include "arch/arm/faults.hh"
45 #include "arch/arm/isa_traits.hh"
46 #include "arch/arm/system.hh"
47 #include "arch/arm/tlb.hh"
48 #include "arch/arm/vtophys.hh"
49 #include "cpu/base.hh"
50 #include "cpu/checker/cpu.hh"
51 #include "cpu/thread_context.hh"
52 #include "mem/fs_translating_port_proxy.hh"
53 #include "sim/full_system.hh"
54
55 namespace ArmISA {
56
57 void
58 initCPU(ThreadContext *tc, int cpuId)
59 {
60 // Reset CP15?? What does that mean -- ali
61
62 // FPEXC.EN = 0
63
64 static Fault reset = std::make_shared<Reset>();
65 reset->invoke(tc);
66 }
67
68 uint64_t
69 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
70 {
71 if (!FullSystem) {
72 panic("getArgument() only implemented for full system mode.\n");
73 M5_DUMMY_RETURN
74 }
75
76 if (fp)
77 panic("getArgument(): Floating point arguments not implemented\n");
78
79 if (inAArch64(tc)) {
80 if (size == (uint16_t)(-1))
81 size = sizeof(uint64_t);
82
83 if (number < 8 /*NumArgumentRegs64*/) {
84 return tc->readIntReg(number);
85 } else {
86 panic("getArgument(): No support reading stack args for AArch64\n");
87 }
88 } else {
89 if (size == (uint16_t)(-1))
90 // todo: should this not be sizeof(uint32_t) rather?
91 size = ArmISA::MachineBytes;
92
93 if (number < NumArgumentRegs) {
94 // If the argument is 64 bits, it must be in an even regiser
95 // number. Increment the number here if it isn't even.
96 if (size == sizeof(uint64_t)) {
97 if ((number % 2) != 0)
98 number++;
99 // Read the two halves of the data. Number is inc here to
100 // get the second half of the 64 bit reg.
101 uint64_t tmp;
102 tmp = tc->readIntReg(number++);
103 tmp |= tc->readIntReg(number) << 32;
104 return tmp;
105 } else {
106 return tc->readIntReg(number);
107 }
108 } else {
109 Addr sp = tc->readIntReg(StackPointerReg);
110 PortProxy &vp = tc->getVirtProxy();
111 uint64_t arg;
112 if (size == sizeof(uint64_t)) {
113 // If the argument is even it must be aligned
114 if ((number % 2) != 0)
115 number++;
116 arg = vp.read<uint64_t>(sp +
117 (number-NumArgumentRegs) * sizeof(uint32_t));
118 // since two 32 bit args == 1 64 bit arg, increment number
119 number++;
120 } else {
121 arg = vp.read<uint32_t>(sp +
122 (number-NumArgumentRegs) * sizeof(uint32_t));
123 }
124 return arg;
125 }
126 }
127 panic("getArgument() should always return\n");
128 }
129
130 void
131 skipFunction(ThreadContext *tc)
132 {
133 PCState newPC = tc->pcState();
134 if (inAArch64(tc)) {
135 newPC.set(tc->readIntReg(INTREG_X30));
136 } else {
137 newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
138 }
139
140 CheckerCPU *checker = tc->getCheckerCpuPtr();
141 if (checker) {
142 tc->pcStateNoRecord(newPC);
143 } else {
144 tc->pcState(newPC);
145 }
146 }
147
148 static void
149 copyVecRegs(ThreadContext *src, ThreadContext *dest)
150 {
151 auto src_mode = RenameMode<ArmISA::ISA>::mode(src->pcState());
152
153 // The way vector registers are copied (VecReg vs VecElem) is relevant
154 // in the O3 model only.
155 if (src_mode == Enums::Full) {
156 for (auto idx = 0; idx < NumVecRegs; idx++)
157 dest->setVecRegFlat(idx, src->readVecRegFlat(idx));
158 } else {
159 for (auto idx = 0; idx < NumVecRegs; idx++)
160 for (auto elem_idx = 0; elem_idx < NumVecElemPerVecReg; elem_idx++)
161 dest->setVecElemFlat(
162 idx, elem_idx, src->readVecElemFlat(idx, elem_idx));
163 }
164 }
165
166 void
167 copyRegs(ThreadContext *src, ThreadContext *dest)
168 {
169 for (int i = 0; i < NumIntRegs; i++)
170 dest->setIntRegFlat(i, src->readIntRegFlat(i));
171
172 for (int i = 0; i < NumFloatRegs; i++)
173 dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
174
175 for (int i = 0; i < NumCCRegs; i++)
176 dest->setCCReg(i, src->readCCReg(i));
177
178 for (int i = 0; i < NumMiscRegs; i++)
179 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
180
181 copyVecRegs(src, dest);
182
183 // setMiscReg "with effect" will set the misc register mapping correctly.
184 // e.g. updateRegMap(val)
185 dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
186
187 // Copy over the PC State
188 dest->pcState(src->pcState());
189
190 // Invalidate the tlb misc register cache
191 dynamic_cast<TLB *>(dest->getITBPtr())->invalidateMiscReg();
192 dynamic_cast<TLB *>(dest->getDTBPtr())->invalidateMiscReg();
193 }
194
195 void
196 sendEvent(ThreadContext *tc)
197 {
198 if (tc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
199 // Post Interrupt and wake cpu if needed
200 tc->getCpuPtr()->postInterrupt(tc->threadId(), INT_SEV, 0);
201 }
202 }
203
204 bool
205 inSecureState(ThreadContext *tc)
206 {
207 SCR scr = inAArch64(tc) ? tc->readMiscReg(MISCREG_SCR_EL3) :
208 tc->readMiscReg(MISCREG_SCR);
209 return ArmSystem::haveSecurity(tc) && inSecureState(
210 scr, tc->readMiscReg(MISCREG_CPSR));
211 }
212
213 inline bool
214 isSecureBelowEL3(ThreadContext *tc)
215 {
216 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
217 return ArmSystem::haveEL(tc, EL3) && scr.ns == 0;
218 }
219
220 bool
221 inAArch64(ThreadContext *tc)
222 {
223 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
224 return opModeIs64((OperatingMode) (uint8_t) cpsr.mode);
225 }
226
227 bool
228 longDescFormatInUse(ThreadContext *tc)
229 {
230 TTBCR ttbcr = tc->readMiscReg(MISCREG_TTBCR);
231 return ArmSystem::haveLPAE(tc) && ttbcr.eae;
232 }
233
234 RegVal
235 readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
236 {
237 const ExceptionLevel current_el = currEL(tc);
238
239 const bool is_secure = isSecureBelowEL3(tc);
240
241 switch (current_el) {
242 case EL0:
243 // Note: in MsrMrs instruction we read the register value before
244 // checking access permissions. This means that EL0 entry must
245 // be part of the table even if MPIDR is not accessible in user
246 // mode.
247 warn_once("Trying to read MPIDR at EL0\n");
248 M5_FALLTHROUGH;
249 case EL1:
250 if (ArmSystem::haveEL(tc, EL2) && !is_secure)
251 return tc->readMiscReg(MISCREG_VMPIDR_EL2);
252 else
253 return getMPIDR(arm_sys, tc);
254 case EL2:
255 case EL3:
256 return getMPIDR(arm_sys, tc);
257 default:
258 panic("Invalid EL for reading MPIDR register\n");
259 }
260 }
261
262 RegVal
263 getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
264 {
265 // Multiprocessor Affinity Register MPIDR from Cortex(tm)-A15 Technical
266 // Reference Manual
267 //
268 // bit 31 - Multi-processor extensions available
269 // bit 30 - Uni-processor system
270 // bit 24 - Multi-threaded cores
271 // bit 11-8 - Cluster ID
272 // bit 1-0 - CPU ID
273 //
274 // We deliberately extend both the Cluster ID and CPU ID fields to allow
275 // for simulation of larger systems
276 assert((0 <= tc->cpuId()) && (tc->cpuId() < 256));
277 assert(tc->socketId() < 65536);
278 if (arm_sys->multiThread) {
279 return 0x80000000 | // multiprocessor extensions available
280 0x01000000 | // multi-threaded cores
281 tc->contextId();
282 } else if (arm_sys->multiProc) {
283 return 0x80000000 | // multiprocessor extensions available
284 tc->cpuId() | tc->socketId() << 8;
285 } else {
286 return 0x80000000 | // multiprocessor extensions available
287 0x40000000 | // in up system
288 tc->cpuId() | tc->socketId() << 8;
289 }
290 }
291
292 bool
293 HaveVirtHostExt(ThreadContext *tc)
294 {
295 AA64MMFR1 id_aa64mmfr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
296 return id_aa64mmfr1.vh;
297 }
298
299 bool
300 HaveSecureEL2Ext(ThreadContext *tc)
301 {
302 AA64PFR0 id_aa64pfr0 = tc->readMiscReg(MISCREG_ID_AA64PFR0_EL1);
303 return id_aa64pfr0.sel2;
304 }
305
306 bool
307 IsSecureEL2Enabled(ThreadContext *tc)
308 {
309 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
310 if (ArmSystem::haveEL(tc, EL2) && HaveSecureEL2Ext(tc)) {
311 if (ArmSystem::haveEL(tc, EL3))
312 return !ELIs32(tc, EL3) && scr.eel2;
313 else
314 return inSecureState(tc);
315 }
316 return false;
317 }
318
319 bool
320 EL2Enabled(ThreadContext *tc)
321 {
322 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
323 return ArmSystem::haveEL(tc, EL2) &&
324 (!ArmSystem::haveEL(tc, EL3) || scr.ns || IsSecureEL2Enabled(tc));
325 }
326
327 bool
328 ELIs64(ThreadContext *tc, ExceptionLevel el)
329 {
330 return !ELIs32(tc, el);
331 }
332
333 bool
334 ELIs32(ThreadContext *tc, ExceptionLevel el)
335 {
336 bool known, aarch32;
337 std::tie(known, aarch32) = ELUsingAArch32K(tc, el);
338 panic_if(!known, "EL state is UNKNOWN");
339 return aarch32;
340 }
341
342 bool
343 ELIsInHost(ThreadContext *tc, ExceptionLevel el)
344 {
345 if (!ArmSystem::haveVirtualization(tc)) {
346 return false;
347 }
348 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
349 return (!isSecureBelowEL3(tc) && !ELIs32(tc, EL2) && hcr.e2h == 1 &&
350 (el == EL2 || (el == EL0 && hcr.tge == 1)));
351 }
352
353 std::pair<bool, bool>
354 ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
355 {
356 // Return true if the specified EL is in aarch32 state.
357 const bool have_el3 = ArmSystem::haveSecurity(tc);
358 const bool have_el2 = ArmSystem::haveVirtualization(tc);
359
360 panic_if(el == EL2 && !have_el2, "Asking for EL2 when it doesn't exist");
361 panic_if(el == EL3 && !have_el3, "Asking for EL3 when it doesn't exist");
362
363 bool known, aarch32;
364 known = aarch32 = false;
365 if (ArmSystem::highestELIs64(tc) && ArmSystem::highestEL(tc) == el) {
366 // Target EL is the highest one in a system where
367 // the highest is using AArch64.
368 known = true; aarch32 = false;
369 } else if (!ArmSystem::highestELIs64(tc)) {
370 // All ELs are using AArch32:
371 known = true; aarch32 = true;
372 } else {
373 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
374 bool aarch32_below_el3 = (have_el3 && scr.rw == 0);
375
376 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
377 bool aarch32_at_el1 = (aarch32_below_el3
378 || (have_el2
379 && !isSecureBelowEL3(tc) && hcr.rw == 0));
380
381 // Only know if EL0 using AArch32 from PSTATE
382 if (el == EL0 && !aarch32_at_el1) {
383 // EL0 controlled by PSTATE
384 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
385
386 known = (currEL(tc) == EL0);
387 aarch32 = (cpsr.width == 1);
388 } else {
389 known = true;
390 aarch32 = (aarch32_below_el3 && el != EL3)
391 || (aarch32_at_el1 && (el == EL0 || el == EL1) );
392 }
393 }
394
395 return std::make_pair(known, aarch32);
396 }
397
398 bool
399 isBigEndian64(ThreadContext *tc)
400 {
401 switch (currEL(tc)) {
402 case EL3:
403 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).ee;
404 case EL2:
405 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).ee;
406 case EL1:
407 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).ee;
408 case EL0:
409 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).e0e;
410 default:
411 panic("Invalid exception level");
412 break;
413 }
414 }
415
416 bool
417 badMode32(ThreadContext *tc, OperatingMode mode)
418 {
419 return unknownMode32(mode) || !ArmSystem::haveEL(tc, opModeToEL(mode));
420 }
421
422 bool
423 badMode(ThreadContext *tc, OperatingMode mode)
424 {
425 return unknownMode(mode) || !ArmSystem::haveEL(tc, opModeToEL(mode));
426 }
427
428 Addr
429 purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
430 TTBCR tcr)
431 {
432 switch (el) {
433 case EL0:
434 case EL1:
435 if (bits(addr, 55, 48) == 0xFF && tcr.tbi1)
436 return addr | mask(63, 55);
437 else if (!bits(addr, 55, 48) && tcr.tbi0)
438 return bits(addr,55, 0);
439 break;
440 case EL2:
441 assert(ArmSystem::haveVirtualization(tc));
442 tcr = tc->readMiscReg(MISCREG_TCR_EL2);
443 if (tcr.tbi)
444 return addr & mask(56);
445 break;
446 case EL3:
447 assert(ArmSystem::haveSecurity(tc));
448 if (tcr.tbi)
449 return addr & mask(56);
450 break;
451 default:
452 panic("Invalid exception level");
453 break;
454 }
455
456 return addr; // Nothing to do if this is not a tagged address
457 }
458
459 Addr
460 purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el)
461 {
462 TTBCR tcr;
463
464 switch (el) {
465 case EL0:
466 case EL1:
467 tcr = tc->readMiscReg(MISCREG_TCR_EL1);
468 if (bits(addr, 55, 48) == 0xFF && tcr.tbi1)
469 return addr | mask(63, 55);
470 else if (!bits(addr, 55, 48) && tcr.tbi0)
471 return bits(addr,55, 0);
472 break;
473 case EL2:
474 assert(ArmSystem::haveVirtualization(tc));
475 tcr = tc->readMiscReg(MISCREG_TCR_EL2);
476 if (tcr.tbi)
477 return addr & mask(56);
478 break;
479 case EL3:
480 assert(ArmSystem::haveSecurity(tc));
481 tcr = tc->readMiscReg(MISCREG_TCR_EL3);
482 if (tcr.tbi)
483 return addr & mask(56);
484 break;
485 default:
486 panic("Invalid exception level");
487 break;
488 }
489
490 return addr; // Nothing to do if this is not a tagged address
491 }
492
493 Addr
494 truncPage(Addr addr)
495 {
496 return addr & ~(PageBytes - 1);
497 }
498
499 Addr
500 roundPage(Addr addr)
501 {
502 return (addr + PageBytes - 1) & ~(PageBytes - 1);
503 }
504
505 bool
506 mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss)
507 {
508 bool isRead;
509 uint32_t crm;
510 IntRegIndex rt;
511 uint32_t crn;
512 uint32_t opc1;
513 uint32_t opc2;
514 bool trapToHype = false;
515
516 const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
517 const HCR hcr = tc->readMiscReg(MISCREG_HCR);
518 const SCR scr = tc->readMiscReg(MISCREG_SCR);
519 const HDCR hdcr = tc->readMiscReg(MISCREG_HDCR);
520 const HSTR hstr = tc->readMiscReg(MISCREG_HSTR);
521 const HCPTR hcptr = tc->readMiscReg(MISCREG_HCPTR);
522
523 if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
524 mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
525 trapToHype = ((uint32_t) hstr) & (1 << crn);
526 trapToHype |= hdcr.tpm && (crn == 9) && (crm >= 12);
527 trapToHype |= hcr.tidcp && (
528 ((crn == 9) && ((crm <= 2) || ((crm >= 5) && (crm <= 8)))) ||
529 ((crn == 10) && ((crm <= 1) || (crm == 4) || (crm == 8))) ||
530 ((crn == 11) && ((crm <= 8) || (crm == 15))) );
531
532 if (!trapToHype) {
533 switch (unflattenMiscReg(miscReg)) {
534 case MISCREG_CPACR:
535 trapToHype = hcptr.tcpac;
536 break;
537 case MISCREG_REVIDR:
538 case MISCREG_TCMTR:
539 case MISCREG_TLBTR:
540 case MISCREG_AIDR:
541 trapToHype = hcr.tid1;
542 break;
543 case MISCREG_CTR:
544 case MISCREG_CCSIDR:
545 case MISCREG_CLIDR:
546 case MISCREG_CSSELR:
547 trapToHype = hcr.tid2;
548 break;
549 case MISCREG_ID_PFR0:
550 case MISCREG_ID_PFR1:
551 case MISCREG_ID_DFR0:
552 case MISCREG_ID_AFR0:
553 case MISCREG_ID_MMFR0:
554 case MISCREG_ID_MMFR1:
555 case MISCREG_ID_MMFR2:
556 case MISCREG_ID_MMFR3:
557 case MISCREG_ID_ISAR0:
558 case MISCREG_ID_ISAR1:
559 case MISCREG_ID_ISAR2:
560 case MISCREG_ID_ISAR3:
561 case MISCREG_ID_ISAR4:
562 case MISCREG_ID_ISAR5:
563 trapToHype = hcr.tid3;
564 break;
565 case MISCREG_DCISW:
566 case MISCREG_DCCSW:
567 case MISCREG_DCCISW:
568 trapToHype = hcr.tsw;
569 break;
570 case MISCREG_DCIMVAC:
571 case MISCREG_DCCIMVAC:
572 case MISCREG_DCCMVAC:
573 trapToHype = hcr.tpc;
574 break;
575 case MISCREG_ICIMVAU:
576 case MISCREG_ICIALLU:
577 case MISCREG_ICIALLUIS:
578 case MISCREG_DCCMVAU:
579 trapToHype = hcr.tpu;
580 break;
581 case MISCREG_TLBIALLIS:
582 case MISCREG_TLBIMVAIS:
583 case MISCREG_TLBIASIDIS:
584 case MISCREG_TLBIMVAAIS:
585 case MISCREG_TLBIMVALIS:
586 case MISCREG_TLBIMVAALIS:
587 case MISCREG_DTLBIALL:
588 case MISCREG_ITLBIALL:
589 case MISCREG_DTLBIMVA:
590 case MISCREG_ITLBIMVA:
591 case MISCREG_DTLBIASID:
592 case MISCREG_ITLBIASID:
593 case MISCREG_TLBIMVAA:
594 case MISCREG_TLBIALL:
595 case MISCREG_TLBIMVA:
596 case MISCREG_TLBIMVAL:
597 case MISCREG_TLBIMVAAL:
598 case MISCREG_TLBIASID:
599 trapToHype = hcr.ttlb;
600 break;
601 case MISCREG_ACTLR:
602 trapToHype = hcr.tac;
603 break;
604 case MISCREG_SCTLR:
605 case MISCREG_TTBR0:
606 case MISCREG_TTBR1:
607 case MISCREG_TTBCR:
608 case MISCREG_DACR:
609 case MISCREG_DFSR:
610 case MISCREG_IFSR:
611 case MISCREG_DFAR:
612 case MISCREG_IFAR:
613 case MISCREG_ADFSR:
614 case MISCREG_AIFSR:
615 case MISCREG_PRRR:
616 case MISCREG_NMRR:
617 case MISCREG_MAIR0:
618 case MISCREG_MAIR1:
619 case MISCREG_CONTEXTIDR:
620 trapToHype = hcr.tvm & !isRead;
621 break;
622 case MISCREG_PMCR:
623 trapToHype = hdcr.tpmcr;
624 break;
625 // GICv3 regs
626 case MISCREG_ICC_SGI0R:
627 if (tc->getIsaPtr()->haveGICv3CpuIfc())
628 trapToHype = hcr.fmo;
629 break;
630 case MISCREG_ICC_SGI1R:
631 case MISCREG_ICC_ASGI1R:
632 if (tc->getIsaPtr()->haveGICv3CpuIfc())
633 trapToHype = hcr.imo;
634 break;
635 // No default action needed
636 default:
637 break;
638 }
639 }
640 }
641 return trapToHype;
642 }
643
644
645 bool
646 mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
647 HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
648 {
649 bool isRead;
650 uint32_t crm;
651 IntRegIndex rt;
652 uint32_t crn;
653 uint32_t opc1;
654 uint32_t opc2;
655 bool trapToHype = false;
656
657 if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
658 mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
659 inform("trap check M:%x N:%x 1:%x 2:%x hdcr %x, hcptr %x, hstr %x\n",
660 crm, crn, opc1, opc2, hdcr, hcptr, hstr);
661 trapToHype = hdcr.tda && (opc1 == 0);
662 trapToHype |= hcptr.tta && (opc1 == 1);
663 if (!trapToHype) {
664 switch (unflattenMiscReg(miscReg)) {
665 case MISCREG_DBGOSLSR:
666 case MISCREG_DBGOSLAR:
667 case MISCREG_DBGOSDLR:
668 case MISCREG_DBGPRCR:
669 trapToHype = hdcr.tdosa;
670 break;
671 case MISCREG_DBGDRAR:
672 case MISCREG_DBGDSAR:
673 trapToHype = hdcr.tdra;
674 break;
675 case MISCREG_JIDR:
676 trapToHype = hcr.tid0;
677 break;
678 case MISCREG_JOSCR:
679 case MISCREG_JMCR:
680 trapToHype = hstr.tjdbx;
681 break;
682 case MISCREG_TEECR:
683 case MISCREG_TEEHBR:
684 trapToHype = hstr.ttee;
685 break;
686 // No default action needed
687 default:
688 break;
689 }
690 }
691 }
692 return trapToHype;
693 }
694
695 bool
696 mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr,
697 HCR hcr, uint32_t iss)
698 {
699 uint32_t crm;
700 IntRegIndex rt;
701 uint32_t crn;
702 uint32_t opc1;
703 uint32_t opc2;
704 bool isRead;
705 bool trapToHype = false;
706
707 if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
708 // This is technically the wrong function, but we can re-use it for
709 // the moment because we only need one field, which overlaps with the
710 // mcrmrc layout
711 mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
712 trapToHype = ((uint32_t) hstr) & (1 << crm);
713
714 if (!trapToHype) {
715 switch (unflattenMiscReg(miscReg)) {
716 case MISCREG_SCTLR:
717 case MISCREG_TTBR0:
718 case MISCREG_TTBR1:
719 case MISCREG_TTBCR:
720 case MISCREG_DACR:
721 case MISCREG_DFSR:
722 case MISCREG_IFSR:
723 case MISCREG_DFAR:
724 case MISCREG_IFAR:
725 case MISCREG_ADFSR:
726 case MISCREG_AIFSR:
727 case MISCREG_PRRR:
728 case MISCREG_NMRR:
729 case MISCREG_MAIR0:
730 case MISCREG_MAIR1:
731 case MISCREG_CONTEXTIDR:
732 trapToHype = hcr.tvm & !isRead;
733 break;
734 // No default action needed
735 default:
736 break;
737 }
738 }
739 }
740 return trapToHype;
741 }
742
743 bool
744 decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
745 CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
746 {
747 OperatingMode mode = MODE_UNDEFINED;
748 bool ok = true;
749
750 // R mostly indicates if its a int register or a misc reg, we override
751 // below if the few corner cases
752 isIntReg = !r;
753 // Loosely based on ARM ARM issue C section B9.3.10
754 if (r) {
755 switch (sysM)
756 {
757 case 0xE:
758 regIdx = MISCREG_SPSR_FIQ;
759 mode = MODE_FIQ;
760 break;
761 case 0x10:
762 regIdx = MISCREG_SPSR_IRQ;
763 mode = MODE_IRQ;
764 break;
765 case 0x12:
766 regIdx = MISCREG_SPSR_SVC;
767 mode = MODE_SVC;
768 break;
769 case 0x14:
770 regIdx = MISCREG_SPSR_ABT;
771 mode = MODE_ABORT;
772 break;
773 case 0x16:
774 regIdx = MISCREG_SPSR_UND;
775 mode = MODE_UNDEFINED;
776 break;
777 case 0x1C:
778 regIdx = MISCREG_SPSR_MON;
779 mode = MODE_MON;
780 break;
781 case 0x1E:
782 regIdx = MISCREG_SPSR_HYP;
783 mode = MODE_HYP;
784 break;
785 default:
786 ok = false;
787 break;
788 }
789 } else {
790 int sysM4To3 = bits(sysM, 4, 3);
791
792 if (sysM4To3 == 0) {
793 mode = MODE_USER;
794 regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
795 } else if (sysM4To3 == 1) {
796 mode = MODE_FIQ;
797 regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
798 } else if (sysM4To3 == 3) {
799 if (bits(sysM, 1) == 0) {
800 mode = MODE_MON;
801 regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
802 } else {
803 mode = MODE_HYP;
804 if (bits(sysM, 0) == 1) {
805 regIdx = intRegInMode(mode, 13); // R13 in HYP
806 } else {
807 isIntReg = false;
808 regIdx = MISCREG_ELR_HYP;
809 }
810 }
811 } else { // Other Banked registers
812 int sysM2 = bits(sysM, 2);
813 int sysM1 = bits(sysM, 1);
814
815 mode = (OperatingMode) ( ((sysM2 || sysM1) << 0) |
816 (1 << 1) |
817 ((sysM2 && !sysM1) << 2) |
818 ((sysM2 && sysM1) << 3) |
819 (1 << 4) );
820 regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
821 // Don't flatten the register here. This is going to go through
822 // setIntReg() which will do the flattening
823 ok &= mode != cpsr.mode;
824 }
825 }
826
827 // Check that the requested register is accessable from the current mode
828 if (ok && checkSecurity && mode != cpsr.mode) {
829 switch (cpsr.mode)
830 {
831 case MODE_USER:
832 ok = false;
833 break;
834 case MODE_FIQ:
835 ok &= mode != MODE_HYP;
836 ok &= (mode != MODE_MON) || !scr.ns;
837 break;
838 case MODE_HYP:
839 ok &= mode != MODE_MON;
840 ok &= (mode != MODE_FIQ) || !nsacr.rfr;
841 break;
842 case MODE_IRQ:
843 case MODE_SVC:
844 case MODE_ABORT:
845 case MODE_UNDEFINED:
846 case MODE_SYSTEM:
847 ok &= mode != MODE_HYP;
848 ok &= (mode != MODE_MON) || !scr.ns;
849 ok &= (mode != MODE_FIQ) || !nsacr.rfr;
850 break;
851 // can access everything, no further checks required
852 case MODE_MON:
853 break;
854 default:
855 panic("unknown Mode 0x%x\n", cpsr.mode);
856 break;
857 }
858 }
859 return (ok);
860 }
861
862 bool
863 SPAlignmentCheckEnabled(ThreadContext* tc)
864 {
865 switch (currEL(tc)) {
866 case EL3:
867 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).sa;
868 case EL2:
869 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).sa;
870 case EL1:
871 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa;
872 case EL0:
873 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa0;
874 default:
875 panic("Invalid exception level");
876 break;
877 }
878 }
879
880 int
881 decodePhysAddrRange64(uint8_t pa_enc)
882 {
883 switch (pa_enc) {
884 case 0x0:
885 return 32;
886 case 0x1:
887 return 36;
888 case 0x2:
889 return 40;
890 case 0x3:
891 return 42;
892 case 0x4:
893 return 44;
894 case 0x5:
895 case 0x6:
896 case 0x7:
897 return 48;
898 default:
899 panic("Invalid phys. address range encoding");
900 }
901 }
902
903 uint8_t
904 encodePhysAddrRange64(int pa_size)
905 {
906 switch (pa_size) {
907 case 32:
908 return 0x0;
909 case 36:
910 return 0x1;
911 case 40:
912 return 0x2;
913 case 42:
914 return 0x3;
915 case 44:
916 return 0x4;
917 case 48:
918 return 0x5;
919 default:
920 panic("Invalid phys. address range");
921 }
922 }
923
924 } // namespace ArmISA