2 * Copyright (c) 2009-2014, 2016-2018 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include "arch/arm/utility.hh"
44 #include "arch/arm/faults.hh"
45 #include "arch/arm/isa_traits.hh"
46 #include "arch/arm/system.hh"
47 #include "arch/arm/tlb.hh"
48 #include "arch/arm/vtophys.hh"
49 #include "cpu/base.hh"
50 #include "cpu/checker/cpu.hh"
51 #include "cpu/thread_context.hh"
52 #include "mem/fs_translating_port_proxy.hh"
53 #include "sim/full_system.hh"
58 initCPU(ThreadContext
*tc
, int cpuId
)
60 // Reset CP15?? What does that mean -- ali
64 static Fault reset
= std::make_shared
<Reset
>();
69 getArgument(ThreadContext
*tc
, int &number
, uint16_t size
, bool fp
)
72 panic("getArgument() only implemented for full system mode.\n");
77 panic("getArgument(): Floating point arguments not implemented\n");
80 if (size
== (uint16_t)(-1))
81 size
= sizeof(uint64_t);
83 if (number
< 8 /*NumArgumentRegs64*/) {
84 return tc
->readIntReg(number
);
86 panic("getArgument(): No support reading stack args for AArch64\n");
89 if (size
== (uint16_t)(-1))
90 // todo: should this not be sizeof(uint32_t) rather?
91 size
= ArmISA::MachineBytes
;
93 if (number
< NumArgumentRegs
) {
94 // If the argument is 64 bits, it must be in an even regiser
95 // number. Increment the number here if it isn't even.
96 if (size
== sizeof(uint64_t)) {
97 if ((number
% 2) != 0)
99 // Read the two halves of the data. Number is inc here to
100 // get the second half of the 64 bit reg.
102 tmp
= tc
->readIntReg(number
++);
103 tmp
|= tc
->readIntReg(number
) << 32;
106 return tc
->readIntReg(number
);
109 Addr sp
= tc
->readIntReg(StackPointerReg
);
110 FSTranslatingPortProxy
&vp
= tc
->getVirtProxy();
112 if (size
== sizeof(uint64_t)) {
113 // If the argument is even it must be aligned
114 if ((number
% 2) != 0)
116 arg
= vp
.read
<uint64_t>(sp
+
117 (number
-NumArgumentRegs
) * sizeof(uint32_t));
118 // since two 32 bit args == 1 64 bit arg, increment number
121 arg
= vp
.read
<uint32_t>(sp
+
122 (number
-NumArgumentRegs
) * sizeof(uint32_t));
127 panic("getArgument() should always return\n");
131 skipFunction(ThreadContext
*tc
)
133 PCState newPC
= tc
->pcState();
135 newPC
.set(tc
->readIntReg(INTREG_X30
));
137 newPC
.set(tc
->readIntReg(ReturnAddressReg
) & ~ULL(1));
140 CheckerCPU
*checker
= tc
->getCheckerCpuPtr();
142 tc
->pcStateNoRecord(newPC
);
149 copyRegs(ThreadContext
*src
, ThreadContext
*dest
)
151 for (int i
= 0; i
< NumIntRegs
; i
++)
152 dest
->setIntRegFlat(i
, src
->readIntRegFlat(i
));
154 for (int i
= 0; i
< NumFloatRegs
; i
++)
155 dest
->setFloatRegBitsFlat(i
, src
->readFloatRegBitsFlat(i
));
157 for (int i
= 0; i
< NumVecRegs
; i
++)
158 dest
->setVecRegFlat(i
, src
->readVecRegFlat(i
));
160 for (int i
= 0; i
< NumCCRegs
; i
++)
161 dest
->setCCReg(i
, src
->readCCReg(i
));
163 for (int i
= 0; i
< NumMiscRegs
; i
++)
164 dest
->setMiscRegNoEffect(i
, src
->readMiscRegNoEffect(i
));
166 // setMiscReg "with effect" will set the misc register mapping correctly.
167 // e.g. updateRegMap(val)
168 dest
->setMiscReg(MISCREG_CPSR
, src
->readMiscRegNoEffect(MISCREG_CPSR
));
170 // Copy over the PC State
171 dest
->pcState(src
->pcState());
173 // Invalidate the tlb misc register cache
174 dynamic_cast<TLB
*>(dest
->getITBPtr())->invalidateMiscReg();
175 dynamic_cast<TLB
*>(dest
->getDTBPtr())->invalidateMiscReg();
179 inSecureState(ThreadContext
*tc
)
181 SCR scr
= inAArch64(tc
) ? tc
->readMiscReg(MISCREG_SCR_EL3
) :
182 tc
->readMiscReg(MISCREG_SCR
);
183 return ArmSystem::haveSecurity(tc
) && inSecureState(
184 scr
, tc
->readMiscReg(MISCREG_CPSR
));
188 isSecureBelowEL3(ThreadContext
*tc
)
190 SCR scr
= tc
->readMiscReg(MISCREG_SCR_EL3
);
191 return ArmSystem::haveEL(tc
, EL3
) && scr
.ns
== 0;
195 inAArch64(ThreadContext
*tc
)
197 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
198 return opModeIs64((OperatingMode
) (uint8_t) cpsr
.mode
);
202 longDescFormatInUse(ThreadContext
*tc
)
204 TTBCR ttbcr
= tc
->readMiscReg(MISCREG_TTBCR
);
205 return ArmSystem::haveLPAE(tc
) && ttbcr
.eae
;
209 readMPIDR(ArmSystem
*arm_sys
, ThreadContext
*tc
)
211 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
212 const ExceptionLevel current_el
=
213 opModeToEL((OperatingMode
) (uint8_t) cpsr
.mode
);
215 const bool is_secure
= isSecureBelowEL3(tc
);
217 switch (current_el
) {
219 // Note: in MsrMrs instruction we read the register value before
220 // checking access permissions. This means that EL0 entry must
221 // be part of the table even if MPIDR is not accessible in user
223 warn_once("Trying to read MPIDR at EL0\n");
226 if (ArmSystem::haveEL(tc
, EL2
) && !is_secure
)
227 return tc
->readMiscReg(MISCREG_VMPIDR_EL2
);
229 return getMPIDR(arm_sys
, tc
);
232 return getMPIDR(arm_sys
, tc
);
234 panic("Invalid EL for reading MPIDR register\n");
239 getMPIDR(ArmSystem
*arm_sys
, ThreadContext
*tc
)
241 // Multiprocessor Affinity Register MPIDR from Cortex(tm)-A15 Technical
244 // bit 31 - Multi-processor extensions available
245 // bit 30 - Uni-processor system
246 // bit 24 - Multi-threaded cores
247 // bit 11-8 - Cluster ID
250 // We deliberately extend both the Cluster ID and CPU ID fields to allow
251 // for simulation of larger systems
252 assert((0 <= tc
->cpuId()) && (tc
->cpuId() < 256));
253 assert(tc
->socketId() < 65536);
254 if (arm_sys
->multiThread
) {
255 return 0x80000000 | // multiprocessor extensions available
256 0x01000000 | // multi-threaded cores
258 } else if (arm_sys
->multiProc
) {
259 return 0x80000000 | // multiprocessor extensions available
260 tc
->cpuId() | tc
->socketId() << 8;
262 return 0x80000000 | // multiprocessor extensions available
263 0x40000000 | // in up system
264 tc
->cpuId() | tc
->socketId() << 8;
269 ELIs64(ThreadContext
*tc
, ExceptionLevel el
)
271 return !ELIs32(tc
, el
);
275 ELIs32(ThreadContext
*tc
, ExceptionLevel el
)
278 std::tie(known
, aarch32
) = ELUsingAArch32K(tc
, el
);
279 panic_if(!known
, "EL state is UNKNOWN");
283 std::pair
<bool, bool>
284 ELUsingAArch32K(ThreadContext
*tc
, ExceptionLevel el
)
286 // Return true if the specified EL is in aarch32 state.
287 const bool have_el3
= ArmSystem::haveSecurity(tc
);
288 const bool have_el2
= ArmSystem::haveVirtualization(tc
);
290 panic_if(el
== EL2
&& !have_el2
, "Asking for EL2 when it doesn't exist");
291 panic_if(el
== EL3
&& !have_el3
, "Asking for EL3 when it doesn't exist");
294 known
= aarch32
= false;
295 if (ArmSystem::highestELIs64(tc
) && ArmSystem::highestEL(tc
) == el
) {
296 // Target EL is the highest one in a system where
297 // the highest is using AArch64.
298 known
= true; aarch32
= false;
299 } else if (!ArmSystem::highestELIs64(tc
)) {
300 // All ELs are using AArch32:
301 known
= true; aarch32
= true;
303 SCR scr
= tc
->readMiscReg(MISCREG_SCR_EL3
);
304 bool aarch32_below_el3
= (have_el3
&& scr
.rw
== 0);
306 HCR hcr
= tc
->readMiscReg(MISCREG_HCR_EL2
);
307 bool aarch32_at_el1
= (aarch32_below_el3
309 && !isSecureBelowEL3(tc
) && hcr
.rw
== 0));
311 // Only know if EL0 using AArch32 from PSTATE
312 if (el
== EL0
&& !aarch32_at_el1
) {
313 // EL0 controlled by PSTATE
314 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
316 known
= (cpsr
.el
== EL0
);
317 aarch32
= (cpsr
.width
== 1);
320 aarch32
= (aarch32_below_el3
&& el
!= EL3
)
321 || (aarch32_at_el1
&& (el
== EL0
|| el
== EL1
) );
325 return std::make_pair(known
, aarch32
);
329 isBigEndian64(ThreadContext
*tc
)
331 switch (opModeToEL(currOpMode(tc
))) {
333 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL3
)).ee
;
335 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL2
)).ee
;
337 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL1
)).ee
;
339 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL1
)).e0e
;
341 panic("Invalid exception level");
347 badMode32(ThreadContext
*tc
, OperatingMode mode
)
349 return unknownMode32(mode
) || !ArmSystem::haveEL(tc
, opModeToEL(mode
));
353 badMode(ThreadContext
*tc
, OperatingMode mode
)
355 return unknownMode(mode
) || !ArmSystem::haveEL(tc
, opModeToEL(mode
));
359 purifyTaggedAddr(Addr addr
, ThreadContext
*tc
, ExceptionLevel el
,
365 if (bits(addr
, 55, 48) == 0xFF && tcr
.tbi1
)
366 return addr
| mask(63, 55);
367 else if (!bits(addr
, 55, 48) && tcr
.tbi0
)
368 return bits(addr
,55, 0);
371 assert(ArmSystem::haveVirtualization(tc
));
372 tcr
= tc
->readMiscReg(MISCREG_TCR_EL2
);
374 return addr
& mask(56);
377 assert(ArmSystem::haveSecurity(tc
));
379 return addr
& mask(56);
382 panic("Invalid exception level");
386 return addr
; // Nothing to do if this is not a tagged address
390 purifyTaggedAddr(Addr addr
, ThreadContext
*tc
, ExceptionLevel el
)
397 tcr
= tc
->readMiscReg(MISCREG_TCR_EL1
);
398 if (bits(addr
, 55, 48) == 0xFF && tcr
.tbi1
)
399 return addr
| mask(63, 55);
400 else if (!bits(addr
, 55, 48) && tcr
.tbi0
)
401 return bits(addr
,55, 0);
404 assert(ArmSystem::haveVirtualization(tc
));
405 tcr
= tc
->readMiscReg(MISCREG_TCR_EL2
);
407 return addr
& mask(56);
410 assert(ArmSystem::haveSecurity(tc
));
411 tcr
= tc
->readMiscReg(MISCREG_TCR_EL3
);
413 return addr
& mask(56);
416 panic("Invalid exception level");
420 return addr
; // Nothing to do if this is not a tagged address
426 return addr
& ~(PageBytes
- 1);
432 return (addr
+ PageBytes
- 1) & ~(PageBytes
- 1);
436 mcrMrc15TrapToHyp(const MiscRegIndex miscReg
, HCR hcr
, CPSR cpsr
, SCR scr
,
437 HDCR hdcr
, HSTR hstr
, HCPTR hcptr
, uint32_t iss
)
445 bool trapToHype
= false;
448 if (!inSecureState(scr
, cpsr
) && (cpsr
.mode
!= MODE_HYP
)) {
449 mcrMrcIssExtract(iss
, isRead
, crm
, rt
, crn
, opc1
, opc2
);
450 trapToHype
= ((uint32_t) hstr
) & (1 << crn
);
451 trapToHype
|= hdcr
.tpm
&& (crn
== 9) && (crm
>= 12);
452 trapToHype
|= hcr
.tidcp
&& (
453 ((crn
== 9) && ((crm
<= 2) || ((crm
>= 5) && (crm
<= 8)))) ||
454 ((crn
== 10) && ((crm
<= 1) || (crm
== 4) || (crm
== 8))) ||
455 ((crn
== 11) && ((crm
<= 8) || (crm
== 15))) );
458 switch (unflattenMiscReg(miscReg
)) {
460 trapToHype
= hcptr
.tcpac
;
466 trapToHype
= hcr
.tid1
;
472 trapToHype
= hcr
.tid2
;
474 case MISCREG_ID_PFR0
:
475 case MISCREG_ID_PFR1
:
476 case MISCREG_ID_DFR0
:
477 case MISCREG_ID_AFR0
:
478 case MISCREG_ID_MMFR0
:
479 case MISCREG_ID_MMFR1
:
480 case MISCREG_ID_MMFR2
:
481 case MISCREG_ID_MMFR3
:
482 case MISCREG_ID_ISAR0
:
483 case MISCREG_ID_ISAR1
:
484 case MISCREG_ID_ISAR2
:
485 case MISCREG_ID_ISAR3
:
486 case MISCREG_ID_ISAR4
:
487 case MISCREG_ID_ISAR5
:
488 trapToHype
= hcr
.tid3
;
493 trapToHype
= hcr
.tsw
;
495 case MISCREG_DCIMVAC
:
496 case MISCREG_DCCIMVAC
:
497 case MISCREG_DCCMVAC
:
498 trapToHype
= hcr
.tpc
;
500 case MISCREG_ICIMVAU
:
501 case MISCREG_ICIALLU
:
502 case MISCREG_ICIALLUIS
:
503 case MISCREG_DCCMVAU
:
504 trapToHype
= hcr
.tpu
;
506 case MISCREG_TLBIALLIS
:
507 case MISCREG_TLBIMVAIS
:
508 case MISCREG_TLBIASIDIS
:
509 case MISCREG_TLBIMVAAIS
:
510 case MISCREG_TLBIMVALIS
:
511 case MISCREG_TLBIMVAALIS
:
512 case MISCREG_DTLBIALL
:
513 case MISCREG_ITLBIALL
:
514 case MISCREG_DTLBIMVA
:
515 case MISCREG_ITLBIMVA
:
516 case MISCREG_DTLBIASID
:
517 case MISCREG_ITLBIASID
:
518 case MISCREG_TLBIMVAA
:
519 case MISCREG_TLBIALL
:
520 case MISCREG_TLBIMVA
:
521 case MISCREG_TLBIMVAL
:
522 case MISCREG_TLBIMVAAL
:
523 case MISCREG_TLBIASID
:
524 trapToHype
= hcr
.ttlb
;
527 trapToHype
= hcr
.tac
;
544 case MISCREG_CONTEXTIDR
:
545 trapToHype
= hcr
.tvm
& !isRead
;
548 trapToHype
= hdcr
.tpmcr
;
550 // No default action needed
561 mcrMrc14TrapToHyp(const MiscRegIndex miscReg
, HCR hcr
, CPSR cpsr
, SCR scr
,
562 HDCR hdcr
, HSTR hstr
, HCPTR hcptr
, uint32_t iss
)
570 bool trapToHype
= false;
572 if (!inSecureState(scr
, cpsr
) && (cpsr
.mode
!= MODE_HYP
)) {
573 mcrMrcIssExtract(iss
, isRead
, crm
, rt
, crn
, opc1
, opc2
);
574 inform("trap check M:%x N:%x 1:%x 2:%x hdcr %x, hcptr %x, hstr %x\n",
575 crm
, crn
, opc1
, opc2
, hdcr
, hcptr
, hstr
);
576 trapToHype
= hdcr
.tda
&& (opc1
== 0);
577 trapToHype
|= hcptr
.tta
&& (opc1
== 1);
579 switch (unflattenMiscReg(miscReg
)) {
580 case MISCREG_DBGOSLSR
:
581 case MISCREG_DBGOSLAR
:
582 case MISCREG_DBGOSDLR
:
583 case MISCREG_DBGPRCR
:
584 trapToHype
= hdcr
.tdosa
;
586 case MISCREG_DBGDRAR
:
587 case MISCREG_DBGDSAR
:
588 trapToHype
= hdcr
.tdra
;
591 trapToHype
= hcr
.tid0
;
595 trapToHype
= hstr
.tjdbx
;
599 trapToHype
= hstr
.ttee
;
601 // No default action needed
611 mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg
, CPSR cpsr
, SCR scr
, HSTR hstr
,
612 HCR hcr
, uint32_t iss
)
620 bool trapToHype
= false;
622 if (!inSecureState(scr
, cpsr
) && (cpsr
.mode
!= MODE_HYP
)) {
623 // This is technically the wrong function, but we can re-use it for
624 // the moment because we only need one field, which overlaps with the
626 mcrMrcIssExtract(iss
, isRead
, crm
, rt
, crn
, opc1
, opc2
);
627 trapToHype
= ((uint32_t) hstr
) & (1 << crm
);
630 switch (unflattenMiscReg(miscReg
)) {
646 case MISCREG_CONTEXTIDR
:
647 trapToHype
= hcr
.tvm
& !isRead
;
649 // No default action needed
659 decodeMrsMsrBankedReg(uint8_t sysM
, bool r
, bool &isIntReg
, int ®Idx
,
660 CPSR cpsr
, SCR scr
, NSACR nsacr
, bool checkSecurity
)
662 OperatingMode mode
= MODE_UNDEFINED
;
665 // R mostly indicates if its a int register or a misc reg, we override
666 // below if the few corner cases
668 // Loosely based on ARM ARM issue C section B9.3.10
673 regIdx
= MISCREG_SPSR_FIQ
;
677 regIdx
= MISCREG_SPSR_IRQ
;
681 regIdx
= MISCREG_SPSR_SVC
;
685 regIdx
= MISCREG_SPSR_ABT
;
689 regIdx
= MISCREG_SPSR_UND
;
690 mode
= MODE_UNDEFINED
;
693 regIdx
= MISCREG_SPSR_MON
;
697 regIdx
= MISCREG_SPSR_HYP
;
705 int sysM4To3
= bits(sysM
, 4, 3);
709 regIdx
= intRegInMode(mode
, bits(sysM
, 2, 0) + 8);
710 } else if (sysM4To3
== 1) {
712 regIdx
= intRegInMode(mode
, bits(sysM
, 2, 0) + 8);
713 } else if (sysM4To3
== 3) {
714 if (bits(sysM
, 1) == 0) {
716 regIdx
= intRegInMode(mode
, 14 - bits(sysM
, 0));
719 if (bits(sysM
, 0) == 1) {
720 regIdx
= intRegInMode(mode
, 13); // R13 in HYP
723 regIdx
= MISCREG_ELR_HYP
;
726 } else { // Other Banked registers
727 int sysM2
= bits(sysM
, 2);
728 int sysM1
= bits(sysM
, 1);
730 mode
= (OperatingMode
) ( ((sysM2
|| sysM1
) << 0) |
732 ((sysM2
&& !sysM1
) << 2) |
733 ((sysM2
&& sysM1
) << 3) |
735 regIdx
= intRegInMode(mode
, 14 - bits(sysM
, 0));
736 // Don't flatten the register here. This is going to go through
737 // setIntReg() which will do the flattening
738 ok
&= mode
!= cpsr
.mode
;
742 // Check that the requested register is accessable from the current mode
743 if (ok
&& checkSecurity
&& mode
!= cpsr
.mode
) {
750 ok
&= mode
!= MODE_HYP
;
751 ok
&= (mode
!= MODE_MON
) || !scr
.ns
;
754 ok
&= mode
!= MODE_MON
;
755 ok
&= (mode
!= MODE_FIQ
) || !nsacr
.rfr
;
762 ok
&= mode
!= MODE_HYP
;
763 ok
&= (mode
!= MODE_MON
) || !scr
.ns
;
764 ok
&= (mode
!= MODE_FIQ
) || !nsacr
.rfr
;
766 // can access everything, no further checks required
770 panic("unknown Mode 0x%x\n", cpsr
.mode
);
778 SPAlignmentCheckEnabled(ThreadContext
* tc
)
780 switch (opModeToEL(currOpMode(tc
))) {
782 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL3
)).sa
;
784 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL2
)).sa
;
786 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL1
)).sa
;
788 return ((SCTLR
) tc
->readMiscReg(MISCREG_SCTLR_EL1
)).sa0
;
790 panic("Invalid exception level");
796 decodePhysAddrRange64(uint8_t pa_enc
)
814 panic("Invalid phys. address range encoding");
819 encodePhysAddrRange64(int pa_size
)
835 panic("Invalid phys. address range");
839 } // namespace ArmISA