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arch-arm: ELIsInHost, check VHE and SecEL2
[gem5.git] / src / arch / arm / utility.cc
1 /*
2 * Copyright (c) 2009-2014, 2016-2019 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40 #include "arch/arm/utility.hh"
41
42 #include <memory>
43
44 #include "arch/arm/faults.hh"
45 #include "arch/arm/isa_traits.hh"
46 #include "arch/arm/system.hh"
47 #include "arch/arm/tlb.hh"
48 #include "arch/arm/vtophys.hh"
49 #include "cpu/base.hh"
50 #include "cpu/checker/cpu.hh"
51 #include "cpu/thread_context.hh"
52 #include "mem/fs_translating_port_proxy.hh"
53 #include "sim/full_system.hh"
54
55 namespace ArmISA {
56
57 void
58 initCPU(ThreadContext *tc, int cpuId)
59 {
60 // Reset CP15?? What does that mean -- ali
61
62 // FPEXC.EN = 0
63
64 static Fault reset = std::make_shared<Reset>();
65 reset->invoke(tc);
66 }
67
68 uint64_t
69 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
70 {
71 if (!FullSystem) {
72 panic("getArgument() only implemented for full system mode.\n");
73 M5_DUMMY_RETURN
74 }
75
76 if (fp)
77 panic("getArgument(): Floating point arguments not implemented\n");
78
79 if (inAArch64(tc)) {
80 if (size == (uint16_t)(-1))
81 size = sizeof(uint64_t);
82
83 if (number < 8 /*NumArgumentRegs64*/) {
84 return tc->readIntReg(number);
85 } else {
86 panic("getArgument(): No support reading stack args for AArch64\n");
87 }
88 } else {
89 if (size == (uint16_t)(-1))
90 // todo: should this not be sizeof(uint32_t) rather?
91 size = ArmISA::MachineBytes;
92
93 if (number < NumArgumentRegs) {
94 // If the argument is 64 bits, it must be in an even regiser
95 // number. Increment the number here if it isn't even.
96 if (size == sizeof(uint64_t)) {
97 if ((number % 2) != 0)
98 number++;
99 // Read the two halves of the data. Number is inc here to
100 // get the second half of the 64 bit reg.
101 uint64_t tmp;
102 tmp = tc->readIntReg(number++);
103 tmp |= tc->readIntReg(number) << 32;
104 return tmp;
105 } else {
106 return tc->readIntReg(number);
107 }
108 } else {
109 Addr sp = tc->readIntReg(StackPointerReg);
110 PortProxy &vp = tc->getVirtProxy();
111 uint64_t arg;
112 if (size == sizeof(uint64_t)) {
113 // If the argument is even it must be aligned
114 if ((number % 2) != 0)
115 number++;
116 arg = vp.read<uint64_t>(sp +
117 (number-NumArgumentRegs) * sizeof(uint32_t));
118 // since two 32 bit args == 1 64 bit arg, increment number
119 number++;
120 } else {
121 arg = vp.read<uint32_t>(sp +
122 (number-NumArgumentRegs) * sizeof(uint32_t));
123 }
124 return arg;
125 }
126 }
127 panic("getArgument() should always return\n");
128 }
129
130 void
131 skipFunction(ThreadContext *tc)
132 {
133 PCState newPC = tc->pcState();
134 if (inAArch64(tc)) {
135 newPC.set(tc->readIntReg(INTREG_X30));
136 } else {
137 newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
138 }
139
140 CheckerCPU *checker = tc->getCheckerCpuPtr();
141 if (checker) {
142 tc->pcStateNoRecord(newPC);
143 } else {
144 tc->pcState(newPC);
145 }
146 }
147
148 static void
149 copyVecRegs(ThreadContext *src, ThreadContext *dest)
150 {
151 auto src_mode = RenameMode<ArmISA::ISA>::mode(src->pcState());
152
153 // The way vector registers are copied (VecReg vs VecElem) is relevant
154 // in the O3 model only.
155 if (src_mode == Enums::Full) {
156 for (auto idx = 0; idx < NumVecRegs; idx++)
157 dest->setVecRegFlat(idx, src->readVecRegFlat(idx));
158 } else {
159 for (auto idx = 0; idx < NumVecRegs; idx++)
160 for (auto elem_idx = 0; elem_idx < NumVecElemPerVecReg; elem_idx++)
161 dest->setVecElemFlat(
162 idx, elem_idx, src->readVecElemFlat(idx, elem_idx));
163 }
164 }
165
166 void
167 copyRegs(ThreadContext *src, ThreadContext *dest)
168 {
169 for (int i = 0; i < NumIntRegs; i++)
170 dest->setIntRegFlat(i, src->readIntRegFlat(i));
171
172 for (int i = 0; i < NumFloatRegs; i++)
173 dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
174
175 for (int i = 0; i < NumCCRegs; i++)
176 dest->setCCReg(i, src->readCCReg(i));
177
178 for (int i = 0; i < NumMiscRegs; i++)
179 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
180
181 copyVecRegs(src, dest);
182
183 // setMiscReg "with effect" will set the misc register mapping correctly.
184 // e.g. updateRegMap(val)
185 dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
186
187 // Copy over the PC State
188 dest->pcState(src->pcState());
189
190 // Invalidate the tlb misc register cache
191 dynamic_cast<TLB *>(dest->getITBPtr())->invalidateMiscReg();
192 dynamic_cast<TLB *>(dest->getDTBPtr())->invalidateMiscReg();
193 }
194
195 void
196 sendEvent(ThreadContext *tc)
197 {
198 if (tc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
199 // Post Interrupt and wake cpu if needed
200 tc->getCpuPtr()->postInterrupt(tc->threadId(), INT_SEV, 0);
201 }
202 }
203
204 bool
205 inSecureState(ThreadContext *tc)
206 {
207 SCR scr = inAArch64(tc) ? tc->readMiscReg(MISCREG_SCR_EL3) :
208 tc->readMiscReg(MISCREG_SCR);
209 return ArmSystem::haveSecurity(tc) && inSecureState(
210 scr, tc->readMiscReg(MISCREG_CPSR));
211 }
212
213 inline bool
214 isSecureBelowEL3(ThreadContext *tc)
215 {
216 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
217 return ArmSystem::haveEL(tc, EL3) && scr.ns == 0;
218 }
219
220 bool
221 inAArch64(ThreadContext *tc)
222 {
223 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
224 return opModeIs64((OperatingMode) (uint8_t) cpsr.mode);
225 }
226
227 bool
228 longDescFormatInUse(ThreadContext *tc)
229 {
230 TTBCR ttbcr = tc->readMiscReg(MISCREG_TTBCR);
231 return ArmSystem::haveLPAE(tc) && ttbcr.eae;
232 }
233
234 RegVal
235 readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
236 {
237 const ExceptionLevel current_el = currEL(tc);
238
239 const bool is_secure = isSecureBelowEL3(tc);
240
241 switch (current_el) {
242 case EL0:
243 // Note: in MsrMrs instruction we read the register value before
244 // checking access permissions. This means that EL0 entry must
245 // be part of the table even if MPIDR is not accessible in user
246 // mode.
247 warn_once("Trying to read MPIDR at EL0\n");
248 M5_FALLTHROUGH;
249 case EL1:
250 if (ArmSystem::haveEL(tc, EL2) && !is_secure)
251 return tc->readMiscReg(MISCREG_VMPIDR_EL2);
252 else
253 return getMPIDR(arm_sys, tc);
254 case EL2:
255 case EL3:
256 return getMPIDR(arm_sys, tc);
257 default:
258 panic("Invalid EL for reading MPIDR register\n");
259 }
260 }
261
262 RegVal
263 getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
264 {
265 // Multiprocessor Affinity Register MPIDR from Cortex(tm)-A15 Technical
266 // Reference Manual
267 //
268 // bit 31 - Multi-processor extensions available
269 // bit 30 - Uni-processor system
270 // bit 24 - Multi-threaded cores
271 // bit 11-8 - Cluster ID
272 // bit 1-0 - CPU ID
273 //
274 // We deliberately extend both the Cluster ID and CPU ID fields to allow
275 // for simulation of larger systems
276 assert((0 <= tc->cpuId()) && (tc->cpuId() < 256));
277 assert(tc->socketId() < 65536);
278 if (arm_sys->multiThread) {
279 return 0x80000000 | // multiprocessor extensions available
280 0x01000000 | // multi-threaded cores
281 tc->contextId();
282 } else if (arm_sys->multiProc) {
283 return 0x80000000 | // multiprocessor extensions available
284 tc->cpuId() | tc->socketId() << 8;
285 } else {
286 return 0x80000000 | // multiprocessor extensions available
287 0x40000000 | // in up system
288 tc->cpuId() | tc->socketId() << 8;
289 }
290 }
291
292 bool
293 HaveVirtHostExt(ThreadContext *tc)
294 {
295 AA64MMFR1 id_aa64mmfr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
296 return id_aa64mmfr1.vh;
297 }
298
299 bool
300 HaveSecureEL2Ext(ThreadContext *tc)
301 {
302 AA64PFR0 id_aa64pfr0 = tc->readMiscReg(MISCREG_ID_AA64PFR0_EL1);
303 return id_aa64pfr0.sel2;
304 }
305
306 bool
307 IsSecureEL2Enabled(ThreadContext *tc)
308 {
309 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
310 if (ArmSystem::haveEL(tc, EL2) && HaveSecureEL2Ext(tc)) {
311 if (ArmSystem::haveEL(tc, EL3))
312 return !ELIs32(tc, EL3) && scr.eel2;
313 else
314 return inSecureState(tc);
315 }
316 return false;
317 }
318
319 bool
320 EL2Enabled(ThreadContext *tc)
321 {
322 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
323 return ArmSystem::haveEL(tc, EL2) &&
324 (!ArmSystem::haveEL(tc, EL3) || scr.ns || IsSecureEL2Enabled(tc));
325 }
326
327 bool
328 ELIs64(ThreadContext *tc, ExceptionLevel el)
329 {
330 return !ELIs32(tc, el);
331 }
332
333 bool
334 ELIs32(ThreadContext *tc, ExceptionLevel el)
335 {
336 bool known, aarch32;
337 std::tie(known, aarch32) = ELUsingAArch32K(tc, el);
338 panic_if(!known, "EL state is UNKNOWN");
339 return aarch32;
340 }
341
342 bool
343 ELIsInHost(ThreadContext *tc, ExceptionLevel el)
344 {
345 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
346 return ((IsSecureEL2Enabled(tc) || !isSecureBelowEL3(tc)) &&
347 HaveVirtHostExt(tc) && !ELIs32(tc, EL2) && hcr.e2h == 1 &&
348 (el == EL2 || (el == EL0 && hcr.tge == 1)));
349 }
350
351 std::pair<bool, bool>
352 ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
353 {
354 // Return true if the specified EL is in aarch32 state.
355 const bool have_el3 = ArmSystem::haveSecurity(tc);
356 const bool have_el2 = ArmSystem::haveVirtualization(tc);
357
358 panic_if(el == EL2 && !have_el2, "Asking for EL2 when it doesn't exist");
359 panic_if(el == EL3 && !have_el3, "Asking for EL3 when it doesn't exist");
360
361 bool known, aarch32;
362 known = aarch32 = false;
363 if (ArmSystem::highestELIs64(tc) && ArmSystem::highestEL(tc) == el) {
364 // Target EL is the highest one in a system where
365 // the highest is using AArch64.
366 known = true; aarch32 = false;
367 } else if (!ArmSystem::highestELIs64(tc)) {
368 // All ELs are using AArch32:
369 known = true; aarch32 = true;
370 } else {
371 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
372 bool aarch32_below_el3 = (have_el3 && scr.rw == 0);
373
374 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
375 bool aarch32_at_el1 = (aarch32_below_el3
376 || (have_el2
377 && !isSecureBelowEL3(tc) && hcr.rw == 0));
378
379 // Only know if EL0 using AArch32 from PSTATE
380 if (el == EL0 && !aarch32_at_el1) {
381 // EL0 controlled by PSTATE
382 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
383
384 known = (currEL(tc) == EL0);
385 aarch32 = (cpsr.width == 1);
386 } else {
387 known = true;
388 aarch32 = (aarch32_below_el3 && el != EL3)
389 || (aarch32_at_el1 && (el == EL0 || el == EL1) );
390 }
391 }
392
393 return std::make_pair(known, aarch32);
394 }
395
396 bool
397 isBigEndian64(ThreadContext *tc)
398 {
399 switch (currEL(tc)) {
400 case EL3:
401 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).ee;
402 case EL2:
403 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).ee;
404 case EL1:
405 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).ee;
406 case EL0:
407 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).e0e;
408 default:
409 panic("Invalid exception level");
410 break;
411 }
412 }
413
414 bool
415 badMode32(ThreadContext *tc, OperatingMode mode)
416 {
417 return unknownMode32(mode) || !ArmSystem::haveEL(tc, opModeToEL(mode));
418 }
419
420 bool
421 badMode(ThreadContext *tc, OperatingMode mode)
422 {
423 return unknownMode(mode) || !ArmSystem::haveEL(tc, opModeToEL(mode));
424 }
425
426 Addr
427 purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
428 TTBCR tcr)
429 {
430 switch (el) {
431 case EL0:
432 case EL1:
433 if (bits(addr, 55, 48) == 0xFF && tcr.tbi1)
434 return addr | mask(63, 55);
435 else if (!bits(addr, 55, 48) && tcr.tbi0)
436 return bits(addr,55, 0);
437 break;
438 case EL2:
439 assert(ArmSystem::haveVirtualization(tc));
440 tcr = tc->readMiscReg(MISCREG_TCR_EL2);
441 if (tcr.tbi)
442 return addr & mask(56);
443 break;
444 case EL3:
445 assert(ArmSystem::haveSecurity(tc));
446 if (tcr.tbi)
447 return addr & mask(56);
448 break;
449 default:
450 panic("Invalid exception level");
451 break;
452 }
453
454 return addr; // Nothing to do if this is not a tagged address
455 }
456
457 Addr
458 purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el)
459 {
460 TTBCR tcr;
461
462 switch (el) {
463 case EL0:
464 case EL1:
465 tcr = tc->readMiscReg(MISCREG_TCR_EL1);
466 if (bits(addr, 55, 48) == 0xFF && tcr.tbi1)
467 return addr | mask(63, 55);
468 else if (!bits(addr, 55, 48) && tcr.tbi0)
469 return bits(addr,55, 0);
470 break;
471 case EL2:
472 assert(ArmSystem::haveVirtualization(tc));
473 tcr = tc->readMiscReg(MISCREG_TCR_EL2);
474 if (tcr.tbi)
475 return addr & mask(56);
476 break;
477 case EL3:
478 assert(ArmSystem::haveSecurity(tc));
479 tcr = tc->readMiscReg(MISCREG_TCR_EL3);
480 if (tcr.tbi)
481 return addr & mask(56);
482 break;
483 default:
484 panic("Invalid exception level");
485 break;
486 }
487
488 return addr; // Nothing to do if this is not a tagged address
489 }
490
491 Addr
492 truncPage(Addr addr)
493 {
494 return addr & ~(PageBytes - 1);
495 }
496
497 Addr
498 roundPage(Addr addr)
499 {
500 return (addr + PageBytes - 1) & ~(PageBytes - 1);
501 }
502
503 bool
504 mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss)
505 {
506 bool isRead;
507 uint32_t crm;
508 IntRegIndex rt;
509 uint32_t crn;
510 uint32_t opc1;
511 uint32_t opc2;
512 bool trapToHype = false;
513
514 const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
515 const HCR hcr = tc->readMiscReg(MISCREG_HCR);
516 const SCR scr = tc->readMiscReg(MISCREG_SCR);
517 const HDCR hdcr = tc->readMiscReg(MISCREG_HDCR);
518 const HSTR hstr = tc->readMiscReg(MISCREG_HSTR);
519 const HCPTR hcptr = tc->readMiscReg(MISCREG_HCPTR);
520
521 if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
522 mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
523 trapToHype = ((uint32_t) hstr) & (1 << crn);
524 trapToHype |= hdcr.tpm && (crn == 9) && (crm >= 12);
525 trapToHype |= hcr.tidcp && (
526 ((crn == 9) && ((crm <= 2) || ((crm >= 5) && (crm <= 8)))) ||
527 ((crn == 10) && ((crm <= 1) || (crm == 4) || (crm == 8))) ||
528 ((crn == 11) && ((crm <= 8) || (crm == 15))) );
529
530 if (!trapToHype) {
531 switch (unflattenMiscReg(miscReg)) {
532 case MISCREG_CPACR:
533 trapToHype = hcptr.tcpac;
534 break;
535 case MISCREG_REVIDR:
536 case MISCREG_TCMTR:
537 case MISCREG_TLBTR:
538 case MISCREG_AIDR:
539 trapToHype = hcr.tid1;
540 break;
541 case MISCREG_CTR:
542 case MISCREG_CCSIDR:
543 case MISCREG_CLIDR:
544 case MISCREG_CSSELR:
545 trapToHype = hcr.tid2;
546 break;
547 case MISCREG_ID_PFR0:
548 case MISCREG_ID_PFR1:
549 case MISCREG_ID_DFR0:
550 case MISCREG_ID_AFR0:
551 case MISCREG_ID_MMFR0:
552 case MISCREG_ID_MMFR1:
553 case MISCREG_ID_MMFR2:
554 case MISCREG_ID_MMFR3:
555 case MISCREG_ID_ISAR0:
556 case MISCREG_ID_ISAR1:
557 case MISCREG_ID_ISAR2:
558 case MISCREG_ID_ISAR3:
559 case MISCREG_ID_ISAR4:
560 case MISCREG_ID_ISAR5:
561 trapToHype = hcr.tid3;
562 break;
563 case MISCREG_DCISW:
564 case MISCREG_DCCSW:
565 case MISCREG_DCCISW:
566 trapToHype = hcr.tsw;
567 break;
568 case MISCREG_DCIMVAC:
569 case MISCREG_DCCIMVAC:
570 case MISCREG_DCCMVAC:
571 trapToHype = hcr.tpc;
572 break;
573 case MISCREG_ICIMVAU:
574 case MISCREG_ICIALLU:
575 case MISCREG_ICIALLUIS:
576 case MISCREG_DCCMVAU:
577 trapToHype = hcr.tpu;
578 break;
579 case MISCREG_TLBIALLIS:
580 case MISCREG_TLBIMVAIS:
581 case MISCREG_TLBIASIDIS:
582 case MISCREG_TLBIMVAAIS:
583 case MISCREG_TLBIMVALIS:
584 case MISCREG_TLBIMVAALIS:
585 case MISCREG_DTLBIALL:
586 case MISCREG_ITLBIALL:
587 case MISCREG_DTLBIMVA:
588 case MISCREG_ITLBIMVA:
589 case MISCREG_DTLBIASID:
590 case MISCREG_ITLBIASID:
591 case MISCREG_TLBIMVAA:
592 case MISCREG_TLBIALL:
593 case MISCREG_TLBIMVA:
594 case MISCREG_TLBIMVAL:
595 case MISCREG_TLBIMVAAL:
596 case MISCREG_TLBIASID:
597 trapToHype = hcr.ttlb;
598 break;
599 case MISCREG_ACTLR:
600 trapToHype = hcr.tac;
601 break;
602 case MISCREG_SCTLR:
603 case MISCREG_TTBR0:
604 case MISCREG_TTBR1:
605 case MISCREG_TTBCR:
606 case MISCREG_DACR:
607 case MISCREG_DFSR:
608 case MISCREG_IFSR:
609 case MISCREG_DFAR:
610 case MISCREG_IFAR:
611 case MISCREG_ADFSR:
612 case MISCREG_AIFSR:
613 case MISCREG_PRRR:
614 case MISCREG_NMRR:
615 case MISCREG_MAIR0:
616 case MISCREG_MAIR1:
617 case MISCREG_CONTEXTIDR:
618 trapToHype = hcr.tvm & !isRead;
619 break;
620 case MISCREG_PMCR:
621 trapToHype = hdcr.tpmcr;
622 break;
623 // GICv3 regs
624 case MISCREG_ICC_SGI0R:
625 if (tc->getIsaPtr()->haveGICv3CpuIfc())
626 trapToHype = hcr.fmo;
627 break;
628 case MISCREG_ICC_SGI1R:
629 case MISCREG_ICC_ASGI1R:
630 if (tc->getIsaPtr()->haveGICv3CpuIfc())
631 trapToHype = hcr.imo;
632 break;
633 // No default action needed
634 default:
635 break;
636 }
637 }
638 }
639 return trapToHype;
640 }
641
642
643 bool
644 mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
645 HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
646 {
647 bool isRead;
648 uint32_t crm;
649 IntRegIndex rt;
650 uint32_t crn;
651 uint32_t opc1;
652 uint32_t opc2;
653 bool trapToHype = false;
654
655 if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
656 mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
657 inform("trap check M:%x N:%x 1:%x 2:%x hdcr %x, hcptr %x, hstr %x\n",
658 crm, crn, opc1, opc2, hdcr, hcptr, hstr);
659 trapToHype = hdcr.tda && (opc1 == 0);
660 trapToHype |= hcptr.tta && (opc1 == 1);
661 if (!trapToHype) {
662 switch (unflattenMiscReg(miscReg)) {
663 case MISCREG_DBGOSLSR:
664 case MISCREG_DBGOSLAR:
665 case MISCREG_DBGOSDLR:
666 case MISCREG_DBGPRCR:
667 trapToHype = hdcr.tdosa;
668 break;
669 case MISCREG_DBGDRAR:
670 case MISCREG_DBGDSAR:
671 trapToHype = hdcr.tdra;
672 break;
673 case MISCREG_JIDR:
674 trapToHype = hcr.tid0;
675 break;
676 case MISCREG_JOSCR:
677 case MISCREG_JMCR:
678 trapToHype = hstr.tjdbx;
679 break;
680 case MISCREG_TEECR:
681 case MISCREG_TEEHBR:
682 trapToHype = hstr.ttee;
683 break;
684 // No default action needed
685 default:
686 break;
687 }
688 }
689 }
690 return trapToHype;
691 }
692
693 bool
694 mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr,
695 HCR hcr, uint32_t iss)
696 {
697 uint32_t crm;
698 IntRegIndex rt;
699 uint32_t crn;
700 uint32_t opc1;
701 uint32_t opc2;
702 bool isRead;
703 bool trapToHype = false;
704
705 if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
706 // This is technically the wrong function, but we can re-use it for
707 // the moment because we only need one field, which overlaps with the
708 // mcrmrc layout
709 mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
710 trapToHype = ((uint32_t) hstr) & (1 << crm);
711
712 if (!trapToHype) {
713 switch (unflattenMiscReg(miscReg)) {
714 case MISCREG_SCTLR:
715 case MISCREG_TTBR0:
716 case MISCREG_TTBR1:
717 case MISCREG_TTBCR:
718 case MISCREG_DACR:
719 case MISCREG_DFSR:
720 case MISCREG_IFSR:
721 case MISCREG_DFAR:
722 case MISCREG_IFAR:
723 case MISCREG_ADFSR:
724 case MISCREG_AIFSR:
725 case MISCREG_PRRR:
726 case MISCREG_NMRR:
727 case MISCREG_MAIR0:
728 case MISCREG_MAIR1:
729 case MISCREG_CONTEXTIDR:
730 trapToHype = hcr.tvm & !isRead;
731 break;
732 // No default action needed
733 default:
734 break;
735 }
736 }
737 }
738 return trapToHype;
739 }
740
741 bool
742 decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
743 CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
744 {
745 OperatingMode mode = MODE_UNDEFINED;
746 bool ok = true;
747
748 // R mostly indicates if its a int register or a misc reg, we override
749 // below if the few corner cases
750 isIntReg = !r;
751 // Loosely based on ARM ARM issue C section B9.3.10
752 if (r) {
753 switch (sysM)
754 {
755 case 0xE:
756 regIdx = MISCREG_SPSR_FIQ;
757 mode = MODE_FIQ;
758 break;
759 case 0x10:
760 regIdx = MISCREG_SPSR_IRQ;
761 mode = MODE_IRQ;
762 break;
763 case 0x12:
764 regIdx = MISCREG_SPSR_SVC;
765 mode = MODE_SVC;
766 break;
767 case 0x14:
768 regIdx = MISCREG_SPSR_ABT;
769 mode = MODE_ABORT;
770 break;
771 case 0x16:
772 regIdx = MISCREG_SPSR_UND;
773 mode = MODE_UNDEFINED;
774 break;
775 case 0x1C:
776 regIdx = MISCREG_SPSR_MON;
777 mode = MODE_MON;
778 break;
779 case 0x1E:
780 regIdx = MISCREG_SPSR_HYP;
781 mode = MODE_HYP;
782 break;
783 default:
784 ok = false;
785 break;
786 }
787 } else {
788 int sysM4To3 = bits(sysM, 4, 3);
789
790 if (sysM4To3 == 0) {
791 mode = MODE_USER;
792 regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
793 } else if (sysM4To3 == 1) {
794 mode = MODE_FIQ;
795 regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
796 } else if (sysM4To3 == 3) {
797 if (bits(sysM, 1) == 0) {
798 mode = MODE_MON;
799 regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
800 } else {
801 mode = MODE_HYP;
802 if (bits(sysM, 0) == 1) {
803 regIdx = intRegInMode(mode, 13); // R13 in HYP
804 } else {
805 isIntReg = false;
806 regIdx = MISCREG_ELR_HYP;
807 }
808 }
809 } else { // Other Banked registers
810 int sysM2 = bits(sysM, 2);
811 int sysM1 = bits(sysM, 1);
812
813 mode = (OperatingMode) ( ((sysM2 || sysM1) << 0) |
814 (1 << 1) |
815 ((sysM2 && !sysM1) << 2) |
816 ((sysM2 && sysM1) << 3) |
817 (1 << 4) );
818 regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
819 // Don't flatten the register here. This is going to go through
820 // setIntReg() which will do the flattening
821 ok &= mode != cpsr.mode;
822 }
823 }
824
825 // Check that the requested register is accessable from the current mode
826 if (ok && checkSecurity && mode != cpsr.mode) {
827 switch (cpsr.mode)
828 {
829 case MODE_USER:
830 ok = false;
831 break;
832 case MODE_FIQ:
833 ok &= mode != MODE_HYP;
834 ok &= (mode != MODE_MON) || !scr.ns;
835 break;
836 case MODE_HYP:
837 ok &= mode != MODE_MON;
838 ok &= (mode != MODE_FIQ) || !nsacr.rfr;
839 break;
840 case MODE_IRQ:
841 case MODE_SVC:
842 case MODE_ABORT:
843 case MODE_UNDEFINED:
844 case MODE_SYSTEM:
845 ok &= mode != MODE_HYP;
846 ok &= (mode != MODE_MON) || !scr.ns;
847 ok &= (mode != MODE_FIQ) || !nsacr.rfr;
848 break;
849 // can access everything, no further checks required
850 case MODE_MON:
851 break;
852 default:
853 panic("unknown Mode 0x%x\n", cpsr.mode);
854 break;
855 }
856 }
857 return (ok);
858 }
859
860 bool
861 SPAlignmentCheckEnabled(ThreadContext* tc)
862 {
863 switch (currEL(tc)) {
864 case EL3:
865 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).sa;
866 case EL2:
867 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).sa;
868 case EL1:
869 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa;
870 case EL0:
871 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa0;
872 default:
873 panic("Invalid exception level");
874 break;
875 }
876 }
877
878 int
879 decodePhysAddrRange64(uint8_t pa_enc)
880 {
881 switch (pa_enc) {
882 case 0x0:
883 return 32;
884 case 0x1:
885 return 36;
886 case 0x2:
887 return 40;
888 case 0x3:
889 return 42;
890 case 0x4:
891 return 44;
892 case 0x5:
893 case 0x6:
894 case 0x7:
895 return 48;
896 default:
897 panic("Invalid phys. address range encoding");
898 }
899 }
900
901 uint8_t
902 encodePhysAddrRange64(int pa_size)
903 {
904 switch (pa_size) {
905 case 32:
906 return 0x0;
907 case 36:
908 return 0x1;
909 case 40:
910 return 0x2;
911 case 42:
912 return 0x3;
913 case 44:
914 return 0x4;
915 case 48:
916 return 0x5;
917 default:
918 panic("Invalid phys. address range");
919 }
920 }
921
922 } // namespace ArmISA