src/arch/arm/utility.cc

   1 /*
   2  * Copyright (c) 2009-2014, 2016-2019 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Ali Saidi
  38  */
  39
  40 #include "arch/arm/utility.hh"
  41
  42 #include <memory>
  43
  44 #include "arch/arm/faults.hh"
  45 #include "arch/arm/isa_traits.hh"
  46 #include "arch/arm/system.hh"
  47 #include "arch/arm/tlb.hh"
  48 #include "arch/arm/vtophys.hh"
  49 #include "cpu/base.hh"
  50 #include "cpu/checker/cpu.hh"
  51 #include "cpu/thread_context.hh"
  52 #include "mem/fs_translating_port_proxy.hh"
  53 #include "sim/full_system.hh"
  54
  55 namespace ArmISA {
  56
  57 void
  58 initCPU(ThreadContext *tc, int cpuId)
  59 {
  60     // Reset CP15?? What does that mean -- ali
  61
  62     // FPEXC.EN = 0
  63
  64     static Fault reset = std::make_shared<Reset>();
  65     reset->invoke(tc);
  66 }
  67
  68 uint64_t
  69 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
  70 {
  71     if (!FullSystem) {
  72         panic("getArgument() only implemented for full system mode.\n");
  73         M5_DUMMY_RETURN
  74     }
  75
  76     if (fp)
  77         panic("getArgument(): Floating point arguments not implemented\n");
  78
  79     if (inAArch64(tc)) {
  80         if (size == (uint16_t)(-1))
  81             size = sizeof(uint64_t);
  82
  83         if (number < 8 /*NumArgumentRegs64*/) {
  84                return tc->readIntReg(number);
  85         } else {
  86             panic("getArgument(): No support reading stack args for AArch64\n");
  87         }
  88     } else {
  89         if (size == (uint16_t)(-1))
  90             // todo: should this not be sizeof(uint32_t) rather?
  91             size = ArmISA::MachineBytes;
  92
  93         if (number < NumArgumentRegs) {
  94             // If the argument is 64 bits, it must be in an even regiser
  95             // number. Increment the number here if it isn't even.
  96             if (size == sizeof(uint64_t)) {
  97                 if ((number % 2) != 0)
  98                     number++;
  99                 // Read the two halves of the data. Number is inc here to
 100                 // get the second half of the 64 bit reg.
 101                 uint64_t tmp;
 102                 tmp = tc->readIntReg(number++);
 103                 tmp |= tc->readIntReg(number) << 32;
 104                 return tmp;
 105             } else {
 106                return tc->readIntReg(number);
 107             }
 108         } else {
 109             Addr sp = tc->readIntReg(StackPointerReg);
 110             PortProxy &vp = tc->getVirtProxy();
 111             uint64_t arg;
 112             if (size == sizeof(uint64_t)) {
 113                 // If the argument is even it must be aligned
 114                 if ((number % 2) != 0)
 115                     number++;
 116                 arg = vp.read<uint64_t>(sp +
 117                         (number-NumArgumentRegs) * sizeof(uint32_t));
 118                 // since two 32 bit args == 1 64 bit arg, increment number
 119                 number++;
 120             } else {
 121                 arg = vp.read<uint32_t>(sp +
 122                                (number-NumArgumentRegs) * sizeof(uint32_t));
 123             }
 124             return arg;
 125         }
 126     }
 127     panic("getArgument() should always return\n");
 128 }
 129
 130 void
 131 skipFunction(ThreadContext *tc)
 132 {
 133     PCState newPC = tc->pcState();
 134     if (inAArch64(tc)) {
 135         newPC.set(tc->readIntReg(INTREG_X30));
 136     } else {
 137         newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
 138     }
 139
 140     CheckerCPU *checker = tc->getCheckerCpuPtr();
 141     if (checker) {
 142         tc->pcStateNoRecord(newPC);
 143     } else {
 144         tc->pcState(newPC);
 145     }
 146 }
 147
 148 static void
 149 copyVecRegs(ThreadContext *src, ThreadContext *dest)
 150 {
 151     auto src_mode = RenameMode<ArmISA::ISA>::mode(src->pcState());
 152
 153     // The way vector registers are copied (VecReg vs VecElem) is relevant
 154     // in the O3 model only.
 155     if (src_mode == Enums::Full) {
 156         for (auto idx = 0; idx < NumVecRegs; idx++)
 157             dest->setVecRegFlat(idx, src->readVecRegFlat(idx));
 158     } else {
 159         for (auto idx = 0; idx < NumVecRegs; idx++)
 160             for (auto elem_idx = 0; elem_idx < NumVecElemPerVecReg; elem_idx++)
 161                 dest->setVecElemFlat(
 162                     idx, elem_idx, src->readVecElemFlat(idx, elem_idx));
 163     }
 164 }
 165
 166 void
 167 copyRegs(ThreadContext *src, ThreadContext *dest)
 168 {
 169     for (int i = 0; i < NumIntRegs; i++)
 170         dest->setIntRegFlat(i, src->readIntRegFlat(i));
 171
 172     for (int i = 0; i < NumFloatRegs; i++)
 173         dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
 174
 175     for (int i = 0; i < NumCCRegs; i++)
 176         dest->setCCReg(i, src->readCCReg(i));
 177
 178     for (int i = 0; i < NumMiscRegs; i++)
 179         dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
 180
 181     copyVecRegs(src, dest);
 182
 183     // setMiscReg "with effect" will set the misc register mapping correctly.
 184     // e.g. updateRegMap(val)
 185     dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
 186
 187     // Copy over the PC State
 188     dest->pcState(src->pcState());
 189
 190     // Invalidate the tlb misc register cache
 191     dynamic_cast<TLB *>(dest->getITBPtr())->invalidateMiscReg();
 192     dynamic_cast<TLB *>(dest->getDTBPtr())->invalidateMiscReg();
 193 }
 194
 195 void
 196 sendEvent(ThreadContext *tc)
 197 {
 198     if (tc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
 199         // Post Interrupt and wake cpu if needed
 200         tc->getCpuPtr()->postInterrupt(tc->threadId(), INT_SEV, 0);
 201     }
 202 }
 203
 204 bool
 205 inSecureState(ThreadContext *tc)
 206 {
 207     SCR scr = inAArch64(tc) ? tc->readMiscReg(MISCREG_SCR_EL3) :
 208         tc->readMiscReg(MISCREG_SCR);
 209     return ArmSystem::haveSecurity(tc) && inSecureState(
 210         scr, tc->readMiscReg(MISCREG_CPSR));
 211 }
 212
 213 inline bool
 214 isSecureBelowEL3(ThreadContext *tc)
 215 {
 216     SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
 217     return ArmSystem::haveEL(tc, EL3) && scr.ns == 0;
 218 }
 219
 220 bool
 221 inAArch64(ThreadContext *tc)
 222 {
 223     CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 224     return opModeIs64((OperatingMode) (uint8_t) cpsr.mode);
 225 }
 226
 227 bool
 228 longDescFormatInUse(ThreadContext *tc)
 229 {
 230     TTBCR ttbcr = tc->readMiscReg(MISCREG_TTBCR);
 231     return ArmSystem::haveLPAE(tc) && ttbcr.eae;
 232 }
 233
 234 RegVal
 235 readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
 236 {
 237     const ExceptionLevel current_el = currEL(tc);
 238
 239     const bool is_secure = isSecureBelowEL3(tc);
 240
 241     switch (current_el) {
 242       case EL0:
 243         // Note: in MsrMrs instruction we read the register value before
 244         // checking access permissions. This means that EL0 entry must
 245         // be part of the table even if MPIDR is not accessible in user
 246         // mode.
 247         warn_once("Trying to read MPIDR at EL0\n");
 248         M5_FALLTHROUGH;
 249       case EL1:
 250         if (ArmSystem::haveEL(tc, EL2) && !is_secure)
 251             return tc->readMiscReg(MISCREG_VMPIDR_EL2);
 252         else
 253             return getMPIDR(arm_sys, tc);
 254       case EL2:
 255       case EL3:
 256         return getMPIDR(arm_sys, tc);
 257       default:
 258         panic("Invalid EL for reading MPIDR register\n");
 259     }
 260 }
 261
 262 RegVal
 263 getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
 264 {
 265     // Multiprocessor Affinity Register MPIDR from Cortex(tm)-A15 Technical
 266     // Reference Manual
 267     //
 268     // bit   31 - Multi-processor extensions available
 269     // bit   30 - Uni-processor system
 270     // bit   24 - Multi-threaded cores
 271     // bit 11-8 - Cluster ID
 272     // bit  1-0 - CPU ID
 273     //
 274     // We deliberately extend both the Cluster ID and CPU ID fields to allow
 275     // for simulation of larger systems
 276     assert((0 <= tc->cpuId()) && (tc->cpuId() < 256));
 277     assert(tc->socketId() < 65536);
 278     if (arm_sys->multiThread) {
 279        return 0x80000000 | // multiprocessor extensions available
 280               0x01000000 | // multi-threaded cores
 281               tc->contextId();
 282     } else if (arm_sys->multiProc) {
 283        return 0x80000000 | // multiprocessor extensions available
 284               tc->cpuId() | tc->socketId() << 8;
 285     } else {
 286        return 0x80000000 |  // multiprocessor extensions available
 287               0x40000000 |  // in up system
 288               tc->cpuId() | tc->socketId() << 8;
 289     }
 290 }
 291
 292 bool
 293 ELIs64(ThreadContext *tc, ExceptionLevel el)
 294 {
 295     return !ELIs32(tc, el);
 296 }
 297
 298 bool
 299 ELIs32(ThreadContext *tc, ExceptionLevel el)
 300 {
 301     bool known, aarch32;
 302     std::tie(known, aarch32) = ELUsingAArch32K(tc, el);
 303     panic_if(!known, "EL state is UNKNOWN");
 304     return aarch32;
 305 }
 306
 307 bool
 308 ELIsInHost(ThreadContext *tc, ExceptionLevel el)
 309 {
 310     if (!ArmSystem::haveVirtualization(tc)) {
 311         return false;
 312     }
 313     HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
 314     return (!isSecureBelowEL3(tc) && !ELIs32(tc, EL2) && hcr.e2h == 1 &&
 315             (el == EL2 || (el == EL0 && hcr.tge == 1)));
 316 }
 317
 318 std::pair<bool, bool>
 319 ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
 320 {
 321     // Return true if the specified EL is in aarch32 state.
 322     const bool have_el3 = ArmSystem::haveSecurity(tc);
 323     const bool have_el2 = ArmSystem::haveVirtualization(tc);
 324
 325     panic_if(el == EL2 && !have_el2, "Asking for EL2 when it doesn't exist");
 326     panic_if(el == EL3 && !have_el3, "Asking for EL3 when it doesn't exist");
 327
 328     bool known, aarch32;
 329     known = aarch32 = false;
 330     if (ArmSystem::highestELIs64(tc) && ArmSystem::highestEL(tc) == el) {
 331         // Target EL is the highest one in a system where
 332         // the highest is using AArch64.
 333         known = true; aarch32 = false;
 334     } else if (!ArmSystem::highestELIs64(tc)) {
 335         // All ELs are using AArch32:
 336         known = true; aarch32 = true;
 337     } else {
 338         SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
 339         bool aarch32_below_el3 = (have_el3 && scr.rw == 0);
 340
 341         HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
 342         bool aarch32_at_el1 = (aarch32_below_el3
 343                                || (have_el2
 344                                && !isSecureBelowEL3(tc) && hcr.rw == 0));
 345
 346         // Only know if EL0 using AArch32 from PSTATE
 347         if (el == EL0 && !aarch32_at_el1) {
 348             // EL0 controlled by PSTATE
 349             CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 350
 351             known = (currEL(tc) == EL0);
 352             aarch32 = (cpsr.width == 1);
 353         } else {
 354             known = true;
 355             aarch32 = (aarch32_below_el3 && el != EL3)
 356                       || (aarch32_at_el1 && (el == EL0 || el == EL1) );
 357         }
 358     }
 359
 360     return std::make_pair(known, aarch32);
 361 }
 362
 363 bool
 364 isBigEndian64(ThreadContext *tc)
 365 {
 366     switch (currEL(tc)) {
 367       case EL3:
 368         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).ee;
 369       case EL2:
 370         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).ee;
 371       case EL1:
 372         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).ee;
 373       case EL0:
 374         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).e0e;
 375       default:
 376         panic("Invalid exception level");
 377         break;
 378     }
 379 }
 380
 381 bool
 382 badMode32(ThreadContext *tc, OperatingMode mode)
 383 {
 384     return unknownMode32(mode) || !ArmSystem::haveEL(tc, opModeToEL(mode));
 385 }
 386
 387 bool
 388 badMode(ThreadContext *tc, OperatingMode mode)
 389 {
 390     return unknownMode(mode) || !ArmSystem::haveEL(tc, opModeToEL(mode));
 391 }
 392
 393 Addr
 394 purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
 395                  TTBCR tcr)
 396 {
 397     switch (el) {
 398       case EL0:
 399       case EL1:
 400         if (bits(addr, 55, 48) == 0xFF && tcr.tbi1)
 401             return addr | mask(63, 55);
 402         else if (!bits(addr, 55, 48) && tcr.tbi0)
 403             return bits(addr,55, 0);
 404         break;
 405       case EL2:
 406         assert(ArmSystem::haveVirtualization(tc));
 407         tcr = tc->readMiscReg(MISCREG_TCR_EL2);
 408         if (tcr.tbi)
 409             return addr & mask(56);
 410         break;
 411       case EL3:
 412         assert(ArmSystem::haveSecurity(tc));
 413         if (tcr.tbi)
 414             return addr & mask(56);
 415         break;
 416       default:
 417         panic("Invalid exception level");
 418         break;
 419     }
 420
 421     return addr;  // Nothing to do if this is not a tagged address
 422 }
 423
 424 Addr
 425 purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el)
 426 {
 427     TTBCR tcr;
 428
 429     switch (el) {
 430       case EL0:
 431       case EL1:
 432         tcr = tc->readMiscReg(MISCREG_TCR_EL1);
 433         if (bits(addr, 55, 48) == 0xFF && tcr.tbi1)
 434             return addr | mask(63, 55);
 435         else if (!bits(addr, 55, 48) && tcr.tbi0)
 436             return bits(addr,55, 0);
 437         break;
 438       case EL2:
 439         assert(ArmSystem::haveVirtualization(tc));
 440         tcr = tc->readMiscReg(MISCREG_TCR_EL2);
 441         if (tcr.tbi)
 442             return addr & mask(56);
 443         break;
 444       case EL3:
 445         assert(ArmSystem::haveSecurity(tc));
 446         tcr = tc->readMiscReg(MISCREG_TCR_EL3);
 447         if (tcr.tbi)
 448             return addr & mask(56);
 449         break;
 450       default:
 451         panic("Invalid exception level");
 452         break;
 453     }
 454
 455     return addr;  // Nothing to do if this is not a tagged address
 456 }
 457
 458 Addr
 459 truncPage(Addr addr)
 460 {
 461     return addr & ~(PageBytes - 1);
 462 }
 463
 464 Addr
 465 roundPage(Addr addr)
 466 {
 467     return (addr + PageBytes - 1) & ~(PageBytes - 1);
 468 }
 469
 470 bool
 471 mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss)
 472 {
 473     bool        isRead;
 474     uint32_t    crm;
 475     IntRegIndex rt;
 476     uint32_t    crn;
 477     uint32_t    opc1;
 478     uint32_t    opc2;
 479     bool        trapToHype = false;
 480
 481     const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 482     const HCR hcr = tc->readMiscReg(MISCREG_HCR);
 483     const SCR scr = tc->readMiscReg(MISCREG_SCR);
 484     const HDCR hdcr = tc->readMiscReg(MISCREG_HDCR);
 485     const HSTR hstr = tc->readMiscReg(MISCREG_HSTR);
 486     const HCPTR hcptr = tc->readMiscReg(MISCREG_HCPTR);
 487
 488     if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
 489         mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
 490         trapToHype  = ((uint32_t) hstr) & (1 << crn);
 491         trapToHype |= hdcr.tpm  && (crn == 9) && (crm >= 12);
 492         trapToHype |= hcr.tidcp && (
 493             ((crn ==  9) && ((crm <= 2) || ((crm >= 5) && (crm <= 8)))) ||
 494             ((crn == 10) && ((crm <= 1) ||  (crm == 4) || (crm == 8)))  ||
 495             ((crn == 11) && ((crm <= 8) ||  (crm == 15)))               );
 496
 497         if (!trapToHype) {
 498             switch (unflattenMiscReg(miscReg)) {
 499               case MISCREG_CPACR:
 500                 trapToHype = hcptr.tcpac;
 501                 break;
 502               case MISCREG_REVIDR:
 503               case MISCREG_TCMTR:
 504               case MISCREG_TLBTR:
 505               case MISCREG_AIDR:
 506                 trapToHype = hcr.tid1;
 507                 break;
 508               case MISCREG_CTR:
 509               case MISCREG_CCSIDR:
 510               case MISCREG_CLIDR:
 511               case MISCREG_CSSELR:
 512                 trapToHype = hcr.tid2;
 513                 break;
 514               case MISCREG_ID_PFR0:
 515               case MISCREG_ID_PFR1:
 516               case MISCREG_ID_DFR0:
 517               case MISCREG_ID_AFR0:
 518               case MISCREG_ID_MMFR0:
 519               case MISCREG_ID_MMFR1:
 520               case MISCREG_ID_MMFR2:
 521               case MISCREG_ID_MMFR3:
 522               case MISCREG_ID_ISAR0:
 523               case MISCREG_ID_ISAR1:
 524               case MISCREG_ID_ISAR2:
 525               case MISCREG_ID_ISAR3:
 526               case MISCREG_ID_ISAR4:
 527               case MISCREG_ID_ISAR5:
 528                 trapToHype = hcr.tid3;
 529                 break;
 530               case MISCREG_DCISW:
 531               case MISCREG_DCCSW:
 532               case MISCREG_DCCISW:
 533                 trapToHype = hcr.tsw;
 534                 break;
 535               case MISCREG_DCIMVAC:
 536               case MISCREG_DCCIMVAC:
 537               case MISCREG_DCCMVAC:
 538                 trapToHype = hcr.tpc;
 539                 break;
 540               case MISCREG_ICIMVAU:
 541               case MISCREG_ICIALLU:
 542               case MISCREG_ICIALLUIS:
 543               case MISCREG_DCCMVAU:
 544                 trapToHype = hcr.tpu;
 545                 break;
 546               case MISCREG_TLBIALLIS:
 547               case MISCREG_TLBIMVAIS:
 548               case MISCREG_TLBIASIDIS:
 549               case MISCREG_TLBIMVAAIS:
 550               case MISCREG_TLBIMVALIS:
 551               case MISCREG_TLBIMVAALIS:
 552               case MISCREG_DTLBIALL:
 553               case MISCREG_ITLBIALL:
 554               case MISCREG_DTLBIMVA:
 555               case MISCREG_ITLBIMVA:
 556               case MISCREG_DTLBIASID:
 557               case MISCREG_ITLBIASID:
 558               case MISCREG_TLBIMVAA:
 559               case MISCREG_TLBIALL:
 560               case MISCREG_TLBIMVA:
 561               case MISCREG_TLBIMVAL:
 562               case MISCREG_TLBIMVAAL:
 563               case MISCREG_TLBIASID:
 564                 trapToHype = hcr.ttlb;
 565                 break;
 566               case MISCREG_ACTLR:
 567                 trapToHype = hcr.tac;
 568                 break;
 569               case MISCREG_SCTLR:
 570               case MISCREG_TTBR0:
 571               case MISCREG_TTBR1:
 572               case MISCREG_TTBCR:
 573               case MISCREG_DACR:
 574               case MISCREG_DFSR:
 575               case MISCREG_IFSR:
 576               case MISCREG_DFAR:
 577               case MISCREG_IFAR:
 578               case MISCREG_ADFSR:
 579               case MISCREG_AIFSR:
 580               case MISCREG_PRRR:
 581               case MISCREG_NMRR:
 582               case MISCREG_MAIR0:
 583               case MISCREG_MAIR1:
 584               case MISCREG_CONTEXTIDR:
 585                 trapToHype = hcr.tvm & !isRead;
 586                 break;
 587               case MISCREG_PMCR:
 588                 trapToHype = hdcr.tpmcr;
 589                 break;
 590               // GICv3 regs
 591               case MISCREG_ICC_SGI0R:
 592                 if (tc->getIsaPtr()->haveGICv3CpuIfc())
 593                     trapToHype = hcr.fmo;
 594                 break;
 595               case MISCREG_ICC_SGI1R:
 596               case MISCREG_ICC_ASGI1R:
 597                 if (tc->getIsaPtr()->haveGICv3CpuIfc())
 598                     trapToHype = hcr.imo;
 599                 break;
 600               // No default action needed
 601               default:
 602                 break;
 603             }
 604         }
 605     }
 606     return trapToHype;
 607 }
 608
 609
 610 bool
 611 mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
 612                   HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
 613 {
 614     bool        isRead;
 615     uint32_t    crm;
 616     IntRegIndex rt;
 617     uint32_t    crn;
 618     uint32_t    opc1;
 619     uint32_t    opc2;
 620     bool        trapToHype = false;
 621
 622     if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
 623         mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
 624         inform("trap check M:%x N:%x 1:%x 2:%x hdcr %x, hcptr %x, hstr %x\n",
 625                 crm, crn, opc1, opc2, hdcr, hcptr, hstr);
 626         trapToHype  = hdcr.tda  && (opc1 == 0);
 627         trapToHype |= hcptr.tta && (opc1 == 1);
 628         if (!trapToHype) {
 629             switch (unflattenMiscReg(miscReg)) {
 630               case MISCREG_DBGOSLSR:
 631               case MISCREG_DBGOSLAR:
 632               case MISCREG_DBGOSDLR:
 633               case MISCREG_DBGPRCR:
 634                 trapToHype = hdcr.tdosa;
 635                 break;
 636               case MISCREG_DBGDRAR:
 637               case MISCREG_DBGDSAR:
 638                 trapToHype = hdcr.tdra;
 639                 break;
 640               case MISCREG_JIDR:
 641                 trapToHype = hcr.tid0;
 642                 break;
 643               case MISCREG_JOSCR:
 644               case MISCREG_JMCR:
 645                 trapToHype = hstr.tjdbx;
 646                 break;
 647               case MISCREG_TEECR:
 648               case MISCREG_TEEHBR:
 649                 trapToHype = hstr.ttee;
 650                 break;
 651               // No default action needed
 652               default:
 653                 break;
 654             }
 655         }
 656     }
 657     return trapToHype;
 658 }
 659
 660 bool
 661 mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr,
 662                     HCR hcr, uint32_t iss)
 663 {
 664     uint32_t    crm;
 665     IntRegIndex rt;
 666     uint32_t    crn;
 667     uint32_t    opc1;
 668     uint32_t    opc2;
 669     bool        isRead;
 670     bool        trapToHype = false;
 671
 672     if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
 673         // This is technically the wrong function, but we can re-use it for
 674         // the moment because we only need one field, which overlaps with the
 675         // mcrmrc layout
 676         mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
 677         trapToHype = ((uint32_t) hstr) & (1 << crm);
 678
 679         if (!trapToHype) {
 680             switch (unflattenMiscReg(miscReg)) {
 681               case MISCREG_SCTLR:
 682               case MISCREG_TTBR0:
 683               case MISCREG_TTBR1:
 684               case MISCREG_TTBCR:
 685               case MISCREG_DACR:
 686               case MISCREG_DFSR:
 687               case MISCREG_IFSR:
 688               case MISCREG_DFAR:
 689               case MISCREG_IFAR:
 690               case MISCREG_ADFSR:
 691               case MISCREG_AIFSR:
 692               case MISCREG_PRRR:
 693               case MISCREG_NMRR:
 694               case MISCREG_MAIR0:
 695               case MISCREG_MAIR1:
 696               case MISCREG_CONTEXTIDR:
 697                 trapToHype = hcr.tvm & !isRead;
 698                 break;
 699               // No default action needed
 700               default:
 701                 break;
 702             }
 703         }
 704     }
 705     return trapToHype;
 706 }
 707
 708 bool
 709 decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
 710                       CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
 711 {
 712     OperatingMode mode = MODE_UNDEFINED;
 713     bool          ok = true;
 714
 715     // R mostly indicates if its a int register or a misc reg, we override
 716     // below if the few corner cases
 717     isIntReg = !r;
 718     // Loosely based on ARM ARM issue C section B9.3.10
 719     if (r) {
 720         switch (sysM)
 721         {
 722           case 0xE:
 723             regIdx = MISCREG_SPSR_FIQ;
 724             mode   = MODE_FIQ;
 725             break;
 726           case 0x10:
 727             regIdx = MISCREG_SPSR_IRQ;
 728             mode   = MODE_IRQ;
 729             break;
 730           case 0x12:
 731             regIdx = MISCREG_SPSR_SVC;
 732             mode   = MODE_SVC;
 733             break;
 734           case 0x14:
 735             regIdx = MISCREG_SPSR_ABT;
 736             mode   = MODE_ABORT;
 737             break;
 738           case 0x16:
 739             regIdx = MISCREG_SPSR_UND;
 740             mode   = MODE_UNDEFINED;
 741             break;
 742           case 0x1C:
 743             regIdx = MISCREG_SPSR_MON;
 744             mode   = MODE_MON;
 745             break;
 746           case 0x1E:
 747             regIdx = MISCREG_SPSR_HYP;
 748             mode   = MODE_HYP;
 749             break;
 750           default:
 751             ok = false;
 752             break;
 753         }
 754     } else {
 755         int sysM4To3 = bits(sysM, 4, 3);
 756
 757         if (sysM4To3 == 0) {
 758             mode = MODE_USER;
 759             regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
 760         } else if (sysM4To3 == 1) {
 761             mode = MODE_FIQ;
 762             regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
 763         } else if (sysM4To3 == 3) {
 764             if (bits(sysM, 1) == 0) {
 765                 mode = MODE_MON;
 766                 regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
 767             } else {
 768                 mode = MODE_HYP;
 769                 if (bits(sysM, 0) == 1) {
 770                     regIdx = intRegInMode(mode, 13); // R13 in HYP
 771                 } else {
 772                     isIntReg = false;
 773                     regIdx   = MISCREG_ELR_HYP;
 774                 }
 775             }
 776         } else { // Other Banked registers
 777             int sysM2 = bits(sysM, 2);
 778             int sysM1 = bits(sysM, 1);
 779
 780             mode  = (OperatingMode) ( ((sysM2 ||  sysM1) << 0) |
 781                                       (1                 << 1) |
 782                                       ((sysM2 && !sysM1) << 2) |
 783                                       ((sysM2 &&  sysM1) << 3) |
 784                                       (1                 << 4) );
 785             regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
 786             // Don't flatten the register here. This is going to go through
 787             // setIntReg() which will do the flattening
 788             ok &= mode != cpsr.mode;
 789         }
 790     }
 791
 792     // Check that the requested register is accessable from the current mode
 793     if (ok && checkSecurity && mode != cpsr.mode) {
 794         switch (cpsr.mode)
 795         {
 796           case MODE_USER:
 797             ok = false;
 798             break;
 799           case MODE_FIQ:
 800             ok &=  mode != MODE_HYP;
 801             ok &= (mode != MODE_MON) || !scr.ns;
 802             break;
 803           case MODE_HYP:
 804             ok &=  mode != MODE_MON;
 805             ok &= (mode != MODE_FIQ) || !nsacr.rfr;
 806             break;
 807           case MODE_IRQ:
 808           case MODE_SVC:
 809           case MODE_ABORT:
 810           case MODE_UNDEFINED:
 811           case MODE_SYSTEM:
 812             ok &=  mode != MODE_HYP;
 813             ok &= (mode != MODE_MON) || !scr.ns;
 814             ok &= (mode != MODE_FIQ) || !nsacr.rfr;
 815             break;
 816           // can access everything, no further checks required
 817           case MODE_MON:
 818             break;
 819           default:
 820             panic("unknown Mode 0x%x\n", cpsr.mode);
 821             break;
 822         }
 823     }
 824     return (ok);
 825 }
 826
 827 bool
 828 SPAlignmentCheckEnabled(ThreadContext* tc)
 829 {
 830     switch (currEL(tc)) {
 831       case EL3:
 832         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).sa;
 833       case EL2:
 834         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).sa;
 835       case EL1:
 836         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa;
 837       case EL0:
 838         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa0;
 839       default:
 840         panic("Invalid exception level");
 841         break;
 842     }
 843 }
 844
 845 int
 846 decodePhysAddrRange64(uint8_t pa_enc)
 847 {
 848     switch (pa_enc) {
 849       case 0x0:
 850         return 32;
 851       case 0x1:
 852         return 36;
 853       case 0x2:
 854         return 40;
 855       case 0x3:
 856         return 42;
 857       case 0x4:
 858         return 44;
 859       case 0x5:
 860       case 0x6:
 861       case 0x7:
 862         return 48;
 863       default:
 864         panic("Invalid phys. address range encoding");
 865     }
 866 }
 867
 868 uint8_t
 869 encodePhysAddrRange64(int pa_size)
 870 {
 871     switch (pa_size) {
 872       case 32:
 873         return 0x0;
 874       case 36:
 875         return 0x1;
 876       case 40:
 877         return 0x2;
 878       case 42:
 879         return 0x3;
 880       case 44:
 881         return 0x4;
 882       case 48:
 883         return 0x5;
 884       default:
 885         panic("Invalid phys. address range");
 886     }
 887 }
 888
 889 } // namespace ArmISA