src/arch/arm/utility.cc

   1 /*
   2  * Copyright (c) 2009-2014, 2016-2018 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Ali Saidi
  38  */
  39
  40 #include "arch/arm/utility.hh"
  41
  42 #include <memory>
  43
  44 #include "arch/arm/faults.hh"
  45 #include "arch/arm/isa_traits.hh"
  46 #include "arch/arm/system.hh"
  47 #include "arch/arm/tlb.hh"
  48 #include "arch/arm/vtophys.hh"
  49 #include "cpu/base.hh"
  50 #include "cpu/checker/cpu.hh"
  51 #include "cpu/thread_context.hh"
  52 #include "mem/fs_translating_port_proxy.hh"
  53 #include "sim/full_system.hh"
  54
  55 namespace ArmISA {
  56
  57 void
  58 initCPU(ThreadContext *tc, int cpuId)
  59 {
  60     // Reset CP15?? What does that mean -- ali
  61
  62     // FPEXC.EN = 0
  63
  64     static Fault reset = std::make_shared<Reset>();
  65     reset->invoke(tc);
  66 }
  67
  68 uint64_t
  69 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
  70 {
  71     if (!FullSystem) {
  72         panic("getArgument() only implemented for full system mode.\n");
  73         M5_DUMMY_RETURN
  74     }
  75
  76     if (fp)
  77         panic("getArgument(): Floating point arguments not implemented\n");
  78
  79     if (inAArch64(tc)) {
  80         if (size == (uint16_t)(-1))
  81             size = sizeof(uint64_t);
  82
  83         if (number < 8 /*NumArgumentRegs64*/) {
  84                return tc->readIntReg(number);
  85         } else {
  86             panic("getArgument(): No support reading stack args for AArch64\n");
  87         }
  88     } else {
  89         if (size == (uint16_t)(-1))
  90             // todo: should this not be sizeof(uint32_t) rather?
  91             size = ArmISA::MachineBytes;
  92
  93         if (number < NumArgumentRegs) {
  94             // If the argument is 64 bits, it must be in an even regiser
  95             // number. Increment the number here if it isn't even.
  96             if (size == sizeof(uint64_t)) {
  97                 if ((number % 2) != 0)
  98                     number++;
  99                 // Read the two halves of the data. Number is inc here to
 100                 // get the second half of the 64 bit reg.
 101                 uint64_t tmp;
 102                 tmp = tc->readIntReg(number++);
 103                 tmp |= tc->readIntReg(number) << 32;
 104                 return tmp;
 105             } else {
 106                return tc->readIntReg(number);
 107             }
 108         } else {
 109             Addr sp = tc->readIntReg(StackPointerReg);
 110             FSTranslatingPortProxy &vp = tc->getVirtProxy();
 111             uint64_t arg;
 112             if (size == sizeof(uint64_t)) {
 113                 // If the argument is even it must be aligned
 114                 if ((number % 2) != 0)
 115                     number++;
 116                 arg = vp.read<uint64_t>(sp +
 117                         (number-NumArgumentRegs) * sizeof(uint32_t));
 118                 // since two 32 bit args == 1 64 bit arg, increment number
 119                 number++;
 120             } else {
 121                 arg = vp.read<uint32_t>(sp +
 122                                (number-NumArgumentRegs) * sizeof(uint32_t));
 123             }
 124             return arg;
 125         }
 126     }
 127     panic("getArgument() should always return\n");
 128 }
 129
 130 void
 131 skipFunction(ThreadContext *tc)
 132 {
 133     PCState newPC = tc->pcState();
 134     if (inAArch64(tc)) {
 135         newPC.set(tc->readIntReg(INTREG_X30));
 136     } else {
 137         newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
 138     }
 139
 140     CheckerCPU *checker = tc->getCheckerCpuPtr();
 141     if (checker) {
 142         tc->pcStateNoRecord(newPC);
 143     } else {
 144         tc->pcState(newPC);
 145     }
 146 }
 147
 148 void
 149 copyRegs(ThreadContext *src, ThreadContext *dest)
 150 {
 151     for (int i = 0; i < NumIntRegs; i++)
 152         dest->setIntRegFlat(i, src->readIntRegFlat(i));
 153
 154     for (int i = 0; i < NumFloatRegs; i++)
 155         dest->setFloatRegBitsFlat(i, src->readFloatRegBitsFlat(i));
 156
 157     for (int i = 0; i < NumVecRegs; i++)
 158         dest->setVecRegFlat(i, src->readVecRegFlat(i));
 159
 160     for (int i = 0; i < NumCCRegs; i++)
 161         dest->setCCReg(i, src->readCCReg(i));
 162
 163     for (int i = 0; i < NumMiscRegs; i++)
 164         dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
 165
 166     // setMiscReg "with effect" will set the misc register mapping correctly.
 167     // e.g. updateRegMap(val)
 168     dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
 169
 170     // Copy over the PC State
 171     dest->pcState(src->pcState());
 172
 173     // Invalidate the tlb misc register cache
 174     dynamic_cast<TLB *>(dest->getITBPtr())->invalidateMiscReg();
 175     dynamic_cast<TLB *>(dest->getDTBPtr())->invalidateMiscReg();
 176 }
 177
 178 bool
 179 inSecureState(ThreadContext *tc)
 180 {
 181     SCR scr = inAArch64(tc) ? tc->readMiscReg(MISCREG_SCR_EL3) :
 182         tc->readMiscReg(MISCREG_SCR);
 183     return ArmSystem::haveSecurity(tc) && inSecureState(
 184         scr, tc->readMiscReg(MISCREG_CPSR));
 185 }
 186
 187 inline bool
 188 isSecureBelowEL3(ThreadContext *tc)
 189 {
 190     SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
 191     return ArmSystem::haveEL(tc, EL3) && scr.ns == 0;
 192 }
 193
 194 bool
 195 inAArch64(ThreadContext *tc)
 196 {
 197     CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 198     return opModeIs64((OperatingMode) (uint8_t) cpsr.mode);
 199 }
 200
 201 bool
 202 longDescFormatInUse(ThreadContext *tc)
 203 {
 204     TTBCR ttbcr = tc->readMiscReg(MISCREG_TTBCR);
 205     return ArmSystem::haveLPAE(tc) && ttbcr.eae;
 206 }
 207
 208 MiscReg
 209 readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
 210 {
 211     CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 212     const ExceptionLevel current_el =
 213         opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
 214
 215     const bool is_secure = isSecureBelowEL3(tc);
 216
 217     switch (current_el) {
 218       case EL0:
 219         // Note: in MsrMrs instruction we read the register value before
 220         // checking access permissions. This means that EL0 entry must
 221         // be part of the table even if MPIDR is not accessible in user
 222         // mode.
 223         warn_once("Trying to read MPIDR at EL0\n");
 224         M5_FALLTHROUGH;
 225       case EL1:
 226         if (ArmSystem::haveEL(tc, EL2) && !is_secure)
 227             return tc->readMiscReg(MISCREG_VMPIDR_EL2);
 228         else
 229             return getMPIDR(arm_sys, tc);
 230       case EL2:
 231       case EL3:
 232         return getMPIDR(arm_sys, tc);
 233       default:
 234         panic("Invalid EL for reading MPIDR register\n");
 235     }
 236 }
 237
 238 MiscReg
 239 getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
 240 {
 241     // Multiprocessor Affinity Register MPIDR from Cortex(tm)-A15 Technical
 242     // Reference Manual
 243     //
 244     // bit   31 - Multi-processor extensions available
 245     // bit   30 - Uni-processor system
 246     // bit   24 - Multi-threaded cores
 247     // bit 11-8 - Cluster ID
 248     // bit  1-0 - CPU ID
 249     //
 250     // We deliberately extend both the Cluster ID and CPU ID fields to allow
 251     // for simulation of larger systems
 252     assert((0 <= tc->cpuId()) && (tc->cpuId() < 256));
 253     assert(tc->socketId() < 65536);
 254     if (arm_sys->multiThread) {
 255        return 0x80000000 | // multiprocessor extensions available
 256               0x01000000 | // multi-threaded cores
 257               tc->contextId();
 258     } else if (arm_sys->multiProc) {
 259        return 0x80000000 | // multiprocessor extensions available
 260               tc->cpuId() | tc->socketId() << 8;
 261     } else {
 262        return 0x80000000 |  // multiprocessor extensions available
 263               0x40000000 |  // in up system
 264               tc->cpuId() | tc->socketId() << 8;
 265     }
 266 }
 267
 268 bool
 269 ELIs64(ThreadContext *tc, ExceptionLevel el)
 270 {
 271     return !ELIs32(tc, el);
 272 }
 273
 274 bool
 275 ELIs32(ThreadContext *tc, ExceptionLevel el)
 276 {
 277     bool known, aarch32;
 278     std::tie(known, aarch32) = ELUsingAArch32K(tc, el);
 279     panic_if(!known, "EL state is UNKNOWN");
 280     return aarch32;
 281 }
 282
 283 std::pair<bool, bool>
 284 ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
 285 {
 286     // Return true if the specified EL is in aarch32 state.
 287     const bool have_el3 = ArmSystem::haveSecurity(tc);
 288     const bool have_el2 = ArmSystem::haveVirtualization(tc);
 289
 290     panic_if(el == EL2 && !have_el2, "Asking for EL2 when it doesn't exist");
 291     panic_if(el == EL3 && !have_el3, "Asking for EL3 when it doesn't exist");
 292
 293     bool known, aarch32;
 294     known = aarch32 = false;
 295     if (ArmSystem::highestELIs64(tc) && ArmSystem::highestEL(tc) == el) {
 296         // Target EL is the highest one in a system where
 297         // the highest is using AArch64.
 298         known = true; aarch32 = false;
 299     } else if (!ArmSystem::highestELIs64(tc)) {
 300         // All ELs are using AArch32:
 301         known = true; aarch32 = true;
 302     } else {
 303         SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
 304         bool aarch32_below_el3 = (have_el3 && scr.rw == 0);
 305
 306         HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
 307         bool aarch32_at_el1 = (aarch32_below_el3
 308                                || (have_el2
 309                                && !isSecureBelowEL3(tc) && hcr.rw == 0));
 310
 311         // Only know if EL0 using AArch32 from PSTATE
 312         if (el == EL0 && !aarch32_at_el1) {
 313             // EL0 controlled by PSTATE
 314             CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 315
 316             known = (cpsr.el == EL0);
 317             aarch32 = (cpsr.width == 1);
 318         } else {
 319             known = true;
 320             aarch32 = (aarch32_below_el3 && el != EL3)
 321                       || (aarch32_at_el1 && (el == EL0 || el == EL1) );
 322         }
 323     }
 324
 325     return std::make_pair(known, aarch32);
 326 }
 327
 328 bool
 329 isBigEndian64(ThreadContext *tc)
 330 {
 331     switch (opModeToEL(currOpMode(tc))) {
 332       case EL3:
 333         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).ee;
 334       case EL2:
 335         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).ee;
 336       case EL1:
 337         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).ee;
 338       case EL0:
 339         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).e0e;
 340       default:
 341         panic("Invalid exception level");
 342         break;
 343     }
 344 }
 345
 346 bool
 347 badMode32(ThreadContext *tc, OperatingMode mode)
 348 {
 349     return unknownMode32(mode) || !ArmSystem::haveEL(tc, opModeToEL(mode));
 350 }
 351
 352 bool
 353 badMode(ThreadContext *tc, OperatingMode mode)
 354 {
 355     return unknownMode(mode) || !ArmSystem::haveEL(tc, opModeToEL(mode));
 356 }
 357
 358 Addr
 359 purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
 360                  TTBCR tcr)
 361 {
 362     switch (el) {
 363       case EL0:
 364       case EL1:
 365         if (bits(addr, 55, 48) == 0xFF && tcr.tbi1)
 366             return addr | mask(63, 55);
 367         else if (!bits(addr, 55, 48) && tcr.tbi0)
 368             return bits(addr,55, 0);
 369         break;
 370       case EL2:
 371         assert(ArmSystem::haveVirtualization(tc));
 372         tcr = tc->readMiscReg(MISCREG_TCR_EL2);
 373         if (tcr.tbi)
 374             return addr & mask(56);
 375         break;
 376       case EL3:
 377         assert(ArmSystem::haveSecurity(tc));
 378         if (tcr.tbi)
 379             return addr & mask(56);
 380         break;
 381       default:
 382         panic("Invalid exception level");
 383         break;
 384     }
 385
 386     return addr;  // Nothing to do if this is not a tagged address
 387 }
 388
 389 Addr
 390 purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el)
 391 {
 392     TTBCR tcr;
 393
 394     switch (el) {
 395       case EL0:
 396       case EL1:
 397         tcr = tc->readMiscReg(MISCREG_TCR_EL1);
 398         if (bits(addr, 55, 48) == 0xFF && tcr.tbi1)
 399             return addr | mask(63, 55);
 400         else if (!bits(addr, 55, 48) && tcr.tbi0)
 401             return bits(addr,55, 0);
 402         break;
 403       case EL2:
 404         assert(ArmSystem::haveVirtualization(tc));
 405         tcr = tc->readMiscReg(MISCREG_TCR_EL2);
 406         if (tcr.tbi)
 407             return addr & mask(56);
 408         break;
 409       case EL3:
 410         assert(ArmSystem::haveSecurity(tc));
 411         tcr = tc->readMiscReg(MISCREG_TCR_EL3);
 412         if (tcr.tbi)
 413             return addr & mask(56);
 414         break;
 415       default:
 416         panic("Invalid exception level");
 417         break;
 418     }
 419
 420     return addr;  // Nothing to do if this is not a tagged address
 421 }
 422
 423 Addr
 424 truncPage(Addr addr)
 425 {
 426     return addr & ~(PageBytes - 1);
 427 }
 428
 429 Addr
 430 roundPage(Addr addr)
 431 {
 432     return (addr + PageBytes - 1) & ~(PageBytes - 1);
 433 }
 434
 435 bool
 436 mcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
 437                   HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
 438 {
 439     bool        isRead;
 440     uint32_t    crm;
 441     IntRegIndex rt;
 442     uint32_t    crn;
 443     uint32_t    opc1;
 444     uint32_t    opc2;
 445     bool        trapToHype = false;
 446
 447
 448     if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
 449         mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
 450         trapToHype  = ((uint32_t) hstr) & (1 << crn);
 451         trapToHype |= hdcr.tpm  && (crn == 9) && (crm >= 12);
 452         trapToHype |= hcr.tidcp && (
 453             ((crn ==  9) && ((crm <= 2) || ((crm >= 5) && (crm <= 8)))) ||
 454             ((crn == 10) && ((crm <= 1) ||  (crm == 4) || (crm == 8)))  ||
 455             ((crn == 11) && ((crm <= 8) ||  (crm == 15)))               );
 456
 457         if (!trapToHype) {
 458             switch (unflattenMiscReg(miscReg)) {
 459               case MISCREG_CPACR:
 460                 trapToHype = hcptr.tcpac;
 461                 break;
 462               case MISCREG_REVIDR:
 463               case MISCREG_TCMTR:
 464               case MISCREG_TLBTR:
 465               case MISCREG_AIDR:
 466                 trapToHype = hcr.tid1;
 467                 break;
 468               case MISCREG_CTR:
 469               case MISCREG_CCSIDR:
 470               case MISCREG_CLIDR:
 471               case MISCREG_CSSELR:
 472                 trapToHype = hcr.tid2;
 473                 break;
 474               case MISCREG_ID_PFR0:
 475               case MISCREG_ID_PFR1:
 476               case MISCREG_ID_DFR0:
 477               case MISCREG_ID_AFR0:
 478               case MISCREG_ID_MMFR0:
 479               case MISCREG_ID_MMFR1:
 480               case MISCREG_ID_MMFR2:
 481               case MISCREG_ID_MMFR3:
 482               case MISCREG_ID_ISAR0:
 483               case MISCREG_ID_ISAR1:
 484               case MISCREG_ID_ISAR2:
 485               case MISCREG_ID_ISAR3:
 486               case MISCREG_ID_ISAR4:
 487               case MISCREG_ID_ISAR5:
 488                 trapToHype = hcr.tid3;
 489                 break;
 490               case MISCREG_DCISW:
 491               case MISCREG_DCCSW:
 492               case MISCREG_DCCISW:
 493                 trapToHype = hcr.tsw;
 494                 break;
 495               case MISCREG_DCIMVAC:
 496               case MISCREG_DCCIMVAC:
 497               case MISCREG_DCCMVAC:
 498                 trapToHype = hcr.tpc;
 499                 break;
 500               case MISCREG_ICIMVAU:
 501               case MISCREG_ICIALLU:
 502               case MISCREG_ICIALLUIS:
 503               case MISCREG_DCCMVAU:
 504                 trapToHype = hcr.tpu;
 505                 break;
 506               case MISCREG_TLBIALLIS:
 507               case MISCREG_TLBIMVAIS:
 508               case MISCREG_TLBIASIDIS:
 509               case MISCREG_TLBIMVAAIS:
 510               case MISCREG_TLBIMVALIS:
 511               case MISCREG_TLBIMVAALIS:
 512               case MISCREG_DTLBIALL:
 513               case MISCREG_ITLBIALL:
 514               case MISCREG_DTLBIMVA:
 515               case MISCREG_ITLBIMVA:
 516               case MISCREG_DTLBIASID:
 517               case MISCREG_ITLBIASID:
 518               case MISCREG_TLBIMVAA:
 519               case MISCREG_TLBIALL:
 520               case MISCREG_TLBIMVA:
 521               case MISCREG_TLBIMVAL:
 522               case MISCREG_TLBIMVAAL:
 523               case MISCREG_TLBIASID:
 524                 trapToHype = hcr.ttlb;
 525                 break;
 526               case MISCREG_ACTLR:
 527                 trapToHype = hcr.tac;
 528                 break;
 529               case MISCREG_SCTLR:
 530               case MISCREG_TTBR0:
 531               case MISCREG_TTBR1:
 532               case MISCREG_TTBCR:
 533               case MISCREG_DACR:
 534               case MISCREG_DFSR:
 535               case MISCREG_IFSR:
 536               case MISCREG_DFAR:
 537               case MISCREG_IFAR:
 538               case MISCREG_ADFSR:
 539               case MISCREG_AIFSR:
 540               case MISCREG_PRRR:
 541               case MISCREG_NMRR:
 542               case MISCREG_MAIR0:
 543               case MISCREG_MAIR1:
 544               case MISCREG_CONTEXTIDR:
 545                 trapToHype = hcr.tvm & !isRead;
 546                 break;
 547               case MISCREG_PMCR:
 548                 trapToHype = hdcr.tpmcr;
 549                 break;
 550               // No default action needed
 551               default:
 552                 break;
 553             }
 554         }
 555     }
 556     return trapToHype;
 557 }
 558
 559
 560 bool
 561 mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
 562                   HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
 563 {
 564     bool        isRead;
 565     uint32_t    crm;
 566     IntRegIndex rt;
 567     uint32_t    crn;
 568     uint32_t    opc1;
 569     uint32_t    opc2;
 570     bool        trapToHype = false;
 571
 572     if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
 573         mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
 574         inform("trap check M:%x N:%x 1:%x 2:%x hdcr %x, hcptr %x, hstr %x\n",
 575                 crm, crn, opc1, opc2, hdcr, hcptr, hstr);
 576         trapToHype  = hdcr.tda  && (opc1 == 0);
 577         trapToHype |= hcptr.tta && (opc1 == 1);
 578         if (!trapToHype) {
 579             switch (unflattenMiscReg(miscReg)) {
 580               case MISCREG_DBGOSLSR:
 581               case MISCREG_DBGOSLAR:
 582               case MISCREG_DBGOSDLR:
 583               case MISCREG_DBGPRCR:
 584                 trapToHype = hdcr.tdosa;
 585                 break;
 586               case MISCREG_DBGDRAR:
 587               case MISCREG_DBGDSAR:
 588                 trapToHype = hdcr.tdra;
 589                 break;
 590               case MISCREG_JIDR:
 591                 trapToHype = hcr.tid0;
 592                 break;
 593               case MISCREG_JOSCR:
 594               case MISCREG_JMCR:
 595                 trapToHype = hstr.tjdbx;
 596                 break;
 597               case MISCREG_TEECR:
 598               case MISCREG_TEEHBR:
 599                 trapToHype = hstr.ttee;
 600                 break;
 601               // No default action needed
 602               default:
 603                 break;
 604             }
 605         }
 606     }
 607     return trapToHype;
 608 }
 609
 610 bool
 611 mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr,
 612                     HCR hcr, uint32_t iss)
 613 {
 614     uint32_t    crm;
 615     IntRegIndex rt;
 616     uint32_t    crn;
 617     uint32_t    opc1;
 618     uint32_t    opc2;
 619     bool        isRead;
 620     bool        trapToHype = false;
 621
 622     if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
 623         // This is technically the wrong function, but we can re-use it for
 624         // the moment because we only need one field, which overlaps with the
 625         // mcrmrc layout
 626         mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
 627         trapToHype = ((uint32_t) hstr) & (1 << crm);
 628
 629         if (!trapToHype) {
 630             switch (unflattenMiscReg(miscReg)) {
 631               case MISCREG_SCTLR:
 632               case MISCREG_TTBR0:
 633               case MISCREG_TTBR1:
 634               case MISCREG_TTBCR:
 635               case MISCREG_DACR:
 636               case MISCREG_DFSR:
 637               case MISCREG_IFSR:
 638               case MISCREG_DFAR:
 639               case MISCREG_IFAR:
 640               case MISCREG_ADFSR:
 641               case MISCREG_AIFSR:
 642               case MISCREG_PRRR:
 643               case MISCREG_NMRR:
 644               case MISCREG_MAIR0:
 645               case MISCREG_MAIR1:
 646               case MISCREG_CONTEXTIDR:
 647                 trapToHype = hcr.tvm & !isRead;
 648                 break;
 649               // No default action needed
 650               default:
 651                 break;
 652             }
 653         }
 654     }
 655     return trapToHype;
 656 }
 657
 658 bool
 659 decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
 660                       CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
 661 {
 662     OperatingMode mode = MODE_UNDEFINED;
 663     bool          ok = true;
 664
 665     // R mostly indicates if its a int register or a misc reg, we override
 666     // below if the few corner cases
 667     isIntReg = !r;
 668     // Loosely based on ARM ARM issue C section B9.3.10
 669     if (r) {
 670         switch (sysM)
 671         {
 672           case 0xE:
 673             regIdx = MISCREG_SPSR_FIQ;
 674             mode   = MODE_FIQ;
 675             break;
 676           case 0x10:
 677             regIdx = MISCREG_SPSR_IRQ;
 678             mode   = MODE_IRQ;
 679             break;
 680           case 0x12:
 681             regIdx = MISCREG_SPSR_SVC;
 682             mode   = MODE_SVC;
 683             break;
 684           case 0x14:
 685             regIdx = MISCREG_SPSR_ABT;
 686             mode   = MODE_ABORT;
 687             break;
 688           case 0x16:
 689             regIdx = MISCREG_SPSR_UND;
 690             mode   = MODE_UNDEFINED;
 691             break;
 692           case 0x1C:
 693             regIdx = MISCREG_SPSR_MON;
 694             mode   = MODE_MON;
 695             break;
 696           case 0x1E:
 697             regIdx = MISCREG_SPSR_HYP;
 698             mode   = MODE_HYP;
 699             break;
 700           default:
 701             ok = false;
 702             break;
 703         }
 704     } else {
 705         int sysM4To3 = bits(sysM, 4, 3);
 706
 707         if (sysM4To3 == 0) {
 708             mode = MODE_USER;
 709             regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
 710         } else if (sysM4To3 == 1) {
 711             mode = MODE_FIQ;
 712             regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
 713         } else if (sysM4To3 == 3) {
 714             if (bits(sysM, 1) == 0) {
 715                 mode = MODE_MON;
 716                 regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
 717             } else {
 718                 mode = MODE_HYP;
 719                 if (bits(sysM, 0) == 1) {
 720                     regIdx = intRegInMode(mode, 13); // R13 in HYP
 721                 } else {
 722                     isIntReg = false;
 723                     regIdx   = MISCREG_ELR_HYP;
 724                 }
 725             }
 726         } else { // Other Banked registers
 727             int sysM2 = bits(sysM, 2);
 728             int sysM1 = bits(sysM, 1);
 729
 730             mode  = (OperatingMode) ( ((sysM2 ||  sysM1) << 0) |
 731                                       (1                 << 1) |
 732                                       ((sysM2 && !sysM1) << 2) |
 733                                       ((sysM2 &&  sysM1) << 3) |
 734                                       (1                 << 4) );
 735             regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
 736             // Don't flatten the register here. This is going to go through
 737             // setIntReg() which will do the flattening
 738             ok &= mode != cpsr.mode;
 739         }
 740     }
 741
 742     // Check that the requested register is accessable from the current mode
 743     if (ok && checkSecurity && mode != cpsr.mode) {
 744         switch (cpsr.mode)
 745         {
 746           case MODE_USER:
 747             ok = false;
 748             break;
 749           case MODE_FIQ:
 750             ok &=  mode != MODE_HYP;
 751             ok &= (mode != MODE_MON) || !scr.ns;
 752             break;
 753           case MODE_HYP:
 754             ok &=  mode != MODE_MON;
 755             ok &= (mode != MODE_FIQ) || !nsacr.rfr;
 756             break;
 757           case MODE_IRQ:
 758           case MODE_SVC:
 759           case MODE_ABORT:
 760           case MODE_UNDEFINED:
 761           case MODE_SYSTEM:
 762             ok &=  mode != MODE_HYP;
 763             ok &= (mode != MODE_MON) || !scr.ns;
 764             ok &= (mode != MODE_FIQ) || !nsacr.rfr;
 765             break;
 766           // can access everything, no further checks required
 767           case MODE_MON:
 768             break;
 769           default:
 770             panic("unknown Mode 0x%x\n", cpsr.mode);
 771             break;
 772         }
 773     }
 774     return (ok);
 775 }
 776
 777 bool
 778 SPAlignmentCheckEnabled(ThreadContext* tc)
 779 {
 780     switch (opModeToEL(currOpMode(tc))) {
 781       case EL3:
 782         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).sa;
 783       case EL2:
 784         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).sa;
 785       case EL1:
 786         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa;
 787       case EL0:
 788         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa0;
 789       default:
 790         panic("Invalid exception level");
 791         break;
 792     }
 793 }
 794
 795 int
 796 decodePhysAddrRange64(uint8_t pa_enc)
 797 {
 798     switch (pa_enc) {
 799       case 0x0:
 800         return 32;
 801       case 0x1:
 802         return 36;
 803       case 0x2:
 804         return 40;
 805       case 0x3:
 806         return 42;
 807       case 0x4:
 808         return 44;
 809       case 0x5:
 810       case 0x6:
 811       case 0x7:
 812         return 48;
 813       default:
 814         panic("Invalid phys. address range encoding");
 815     }
 816 }
 817
 818 uint8_t
 819 encodePhysAddrRange64(int pa_size)
 820 {
 821     switch (pa_size) {
 822       case 32:
 823         return 0x0;
 824       case 36:
 825         return 0x1;
 826       case 40:
 827         return 0x2;
 828       case 42:
 829         return 0x3;
 830       case 44:
 831         return 0x4;
 832       case 48:
 833         return 0x5;
 834       default:
 835         panic("Invalid phys. address range");
 836     }
 837 }
 838
 839 } // namespace ArmISA