src/arch/arm/utility.cc

   1 /*
   2  * Copyright (c) 2009-2014, 2016-2019 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Ali Saidi
  38  */
  39
  40 #include "arch/arm/utility.hh"
  41
  42 #include <memory>
  43
  44 #include "arch/arm/faults.hh"
  45 #include "arch/arm/isa_traits.hh"
  46 #include "arch/arm/system.hh"
  47 #include "arch/arm/tlb.hh"
  48 #include "arch/arm/vtophys.hh"
  49 #include "cpu/base.hh"
  50 #include "cpu/checker/cpu.hh"
  51 #include "cpu/thread_context.hh"
  52 #include "mem/fs_translating_port_proxy.hh"
  53 #include "sim/full_system.hh"
  54
  55 namespace ArmISA {
  56
  57 void
  58 initCPU(ThreadContext *tc, int cpuId)
  59 {
  60     // Reset CP15?? What does that mean -- ali
  61
  62     // FPEXC.EN = 0
  63
  64     static Fault reset = std::make_shared<Reset>();
  65     reset->invoke(tc);
  66 }
  67
  68 uint64_t
  69 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
  70 {
  71     if (!FullSystem) {
  72         panic("getArgument() only implemented for full system mode.\n");
  73         M5_DUMMY_RETURN
  74     }
  75
  76     if (fp)
  77         panic("getArgument(): Floating point arguments not implemented\n");
  78
  79     if (inAArch64(tc)) {
  80         if (size == (uint16_t)(-1))
  81             size = sizeof(uint64_t);
  82
  83         if (number < 8 /*NumArgumentRegs64*/) {
  84                return tc->readIntReg(number);
  85         } else {
  86             panic("getArgument(): No support reading stack args for AArch64\n");
  87         }
  88     } else {
  89         if (size == (uint16_t)(-1))
  90             // todo: should this not be sizeof(uint32_t) rather?
  91             size = ArmISA::MachineBytes;
  92
  93         if (number < NumArgumentRegs) {
  94             // If the argument is 64 bits, it must be in an even regiser
  95             // number. Increment the number here if it isn't even.
  96             if (size == sizeof(uint64_t)) {
  97                 if ((number % 2) != 0)
  98                     number++;
  99                 // Read the two halves of the data. Number is inc here to
 100                 // get the second half of the 64 bit reg.
 101                 uint64_t tmp;
 102                 tmp = tc->readIntReg(number++);
 103                 tmp |= tc->readIntReg(number) << 32;
 104                 return tmp;
 105             } else {
 106                return tc->readIntReg(number);
 107             }
 108         } else {
 109             Addr sp = tc->readIntReg(StackPointerReg);
 110             PortProxy &vp = tc->getVirtProxy();
 111             uint64_t arg;
 112             if (size == sizeof(uint64_t)) {
 113                 // If the argument is even it must be aligned
 114                 if ((number % 2) != 0)
 115                     number++;
 116                 arg = vp.read<uint64_t>(sp +
 117                         (number-NumArgumentRegs) * sizeof(uint32_t));
 118                 // since two 32 bit args == 1 64 bit arg, increment number
 119                 number++;
 120             } else {
 121                 arg = vp.read<uint32_t>(sp +
 122                                (number-NumArgumentRegs) * sizeof(uint32_t));
 123             }
 124             return arg;
 125         }
 126     }
 127     panic("getArgument() should always return\n");
 128 }
 129
 130 void
 131 skipFunction(ThreadContext *tc)
 132 {
 133     PCState newPC = tc->pcState();
 134     if (inAArch64(tc)) {
 135         newPC.set(tc->readIntReg(INTREG_X30));
 136     } else {
 137         newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
 138     }
 139
 140     CheckerCPU *checker = tc->getCheckerCpuPtr();
 141     if (checker) {
 142         tc->pcStateNoRecord(newPC);
 143     } else {
 144         tc->pcState(newPC);
 145     }
 146 }
 147
 148 static void
 149 copyVecRegs(ThreadContext *src, ThreadContext *dest)
 150 {
 151     auto src_mode = RenameMode<ArmISA::ISA>::mode(src->pcState());
 152
 153     // The way vector registers are copied (VecReg vs VecElem) is relevant
 154     // in the O3 model only.
 155     if (src_mode == Enums::Full) {
 156         for (auto idx = 0; idx < NumVecRegs; idx++)
 157             dest->setVecRegFlat(idx, src->readVecRegFlat(idx));
 158     } else {
 159         for (auto idx = 0; idx < NumVecRegs; idx++)
 160             for (auto elem_idx = 0; elem_idx < NumVecElemPerVecReg; elem_idx++)
 161                 dest->setVecElemFlat(
 162                     idx, elem_idx, src->readVecElemFlat(idx, elem_idx));
 163     }
 164 }
 165
 166 void
 167 copyRegs(ThreadContext *src, ThreadContext *dest)
 168 {
 169     for (int i = 0; i < NumIntRegs; i++)
 170         dest->setIntRegFlat(i, src->readIntRegFlat(i));
 171
 172     for (int i = 0; i < NumFloatRegs; i++)
 173         dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
 174
 175     for (int i = 0; i < NumCCRegs; i++)
 176         dest->setCCReg(i, src->readCCReg(i));
 177
 178     for (int i = 0; i < NumMiscRegs; i++)
 179         dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
 180
 181     copyVecRegs(src, dest);
 182
 183     // setMiscReg "with effect" will set the misc register mapping correctly.
 184     // e.g. updateRegMap(val)
 185     dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
 186
 187     // Copy over the PC State
 188     dest->pcState(src->pcState());
 189
 190     // Invalidate the tlb misc register cache
 191     dynamic_cast<TLB *>(dest->getITBPtr())->invalidateMiscReg();
 192     dynamic_cast<TLB *>(dest->getDTBPtr())->invalidateMiscReg();
 193 }
 194
 195 void
 196 sendEvent(ThreadContext *tc)
 197 {
 198     if (tc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
 199         // Post Interrupt and wake cpu if needed
 200         tc->getCpuPtr()->postInterrupt(tc->threadId(), INT_SEV, 0);
 201     }
 202 }
 203
 204 bool
 205 inSecureState(ThreadContext *tc)
 206 {
 207     SCR scr = inAArch64(tc) ? tc->readMiscReg(MISCREG_SCR_EL3) :
 208         tc->readMiscReg(MISCREG_SCR);
 209     return ArmSystem::haveSecurity(tc) && inSecureState(
 210         scr, tc->readMiscReg(MISCREG_CPSR));
 211 }
 212
 213 inline bool
 214 isSecureBelowEL3(ThreadContext *tc)
 215 {
 216     SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
 217     return ArmSystem::haveEL(tc, EL3) && scr.ns == 0;
 218 }
 219
 220 bool
 221 inAArch64(ThreadContext *tc)
 222 {
 223     CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 224     return opModeIs64((OperatingMode) (uint8_t) cpsr.mode);
 225 }
 226
 227 bool
 228 longDescFormatInUse(ThreadContext *tc)
 229 {
 230     TTBCR ttbcr = tc->readMiscReg(MISCREG_TTBCR);
 231     return ArmSystem::haveLPAE(tc) && ttbcr.eae;
 232 }
 233
 234 RegVal
 235 readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
 236 {
 237     const ExceptionLevel current_el = currEL(tc);
 238
 239     const bool is_secure = isSecureBelowEL3(tc);
 240
 241     switch (current_el) {
 242       case EL0:
 243         // Note: in MsrMrs instruction we read the register value before
 244         // checking access permissions. This means that EL0 entry must
 245         // be part of the table even if MPIDR is not accessible in user
 246         // mode.
 247         warn_once("Trying to read MPIDR at EL0\n");
 248         M5_FALLTHROUGH;
 249       case EL1:
 250         if (ArmSystem::haveEL(tc, EL2) && !is_secure)
 251             return tc->readMiscReg(MISCREG_VMPIDR_EL2);
 252         else
 253             return getMPIDR(arm_sys, tc);
 254       case EL2:
 255       case EL3:
 256         return getMPIDR(arm_sys, tc);
 257       default:
 258         panic("Invalid EL for reading MPIDR register\n");
 259     }
 260 }
 261
 262 RegVal
 263 getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
 264 {
 265     // Multiprocessor Affinity Register MPIDR from Cortex(tm)-A15 Technical
 266     // Reference Manual
 267     //
 268     // bit   31 - Multi-processor extensions available
 269     // bit   30 - Uni-processor system
 270     // bit   24 - Multi-threaded cores
 271     // bit 11-8 - Cluster ID
 272     // bit  1-0 - CPU ID
 273     //
 274     // We deliberately extend both the Cluster ID and CPU ID fields to allow
 275     // for simulation of larger systems
 276     assert((0 <= tc->cpuId()) && (tc->cpuId() < 256));
 277     assert(tc->socketId() < 65536);
 278     if (arm_sys->multiThread) {
 279        return 0x80000000 | // multiprocessor extensions available
 280               0x01000000 | // multi-threaded cores
 281               tc->contextId();
 282     } else if (arm_sys->multiProc) {
 283        return 0x80000000 | // multiprocessor extensions available
 284               tc->cpuId() | tc->socketId() << 8;
 285     } else {
 286        return 0x80000000 |  // multiprocessor extensions available
 287               0x40000000 |  // in up system
 288               tc->cpuId() | tc->socketId() << 8;
 289     }
 290 }
 291
 292 bool
 293 HaveSecureEL2Ext(ThreadContext *tc)
 294 {
 295     AA64PFR0 id_aa64pfr0 = tc->readMiscReg(MISCREG_ID_AA64PFR0_EL1);
 296     return id_aa64pfr0.sel2;
 297 }
 298
 299 bool
 300 IsSecureEL2Enabled(ThreadContext *tc)
 301 {
 302     SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
 303     if (ArmSystem::haveEL(tc, EL2) && HaveSecureEL2Ext(tc)) {
 304         if (ArmSystem::haveEL(tc, EL3))
 305             return !ELIs32(tc, EL3) && scr.eel2;
 306         else
 307             return inSecureState(tc);
 308     }
 309     return false;
 310 }
 311
 312 bool
 313 EL2Enabled(ThreadContext *tc)
 314 {
 315     SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
 316     return ArmSystem::haveEL(tc, EL2) &&
 317            (!ArmSystem::haveEL(tc, EL3) || scr.ns || IsSecureEL2Enabled(tc));
 318 }
 319
 320 bool
 321 ELIs64(ThreadContext *tc, ExceptionLevel el)
 322 {
 323     return !ELIs32(tc, el);
 324 }
 325
 326 bool
 327 ELIs32(ThreadContext *tc, ExceptionLevel el)
 328 {
 329     bool known, aarch32;
 330     std::tie(known, aarch32) = ELUsingAArch32K(tc, el);
 331     panic_if(!known, "EL state is UNKNOWN");
 332     return aarch32;
 333 }
 334
 335 bool
 336 ELIsInHost(ThreadContext *tc, ExceptionLevel el)
 337 {
 338     if (!ArmSystem::haveVirtualization(tc)) {
 339         return false;
 340     }
 341     HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
 342     return (!isSecureBelowEL3(tc) && !ELIs32(tc, EL2) && hcr.e2h == 1 &&
 343             (el == EL2 || (el == EL0 && hcr.tge == 1)));
 344 }
 345
 346 std::pair<bool, bool>
 347 ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
 348 {
 349     // Return true if the specified EL is in aarch32 state.
 350     const bool have_el3 = ArmSystem::haveSecurity(tc);
 351     const bool have_el2 = ArmSystem::haveVirtualization(tc);
 352
 353     panic_if(el == EL2 && !have_el2, "Asking for EL2 when it doesn't exist");
 354     panic_if(el == EL3 && !have_el3, "Asking for EL3 when it doesn't exist");
 355
 356     bool known, aarch32;
 357     known = aarch32 = false;
 358     if (ArmSystem::highestELIs64(tc) && ArmSystem::highestEL(tc) == el) {
 359         // Target EL is the highest one in a system where
 360         // the highest is using AArch64.
 361         known = true; aarch32 = false;
 362     } else if (!ArmSystem::highestELIs64(tc)) {
 363         // All ELs are using AArch32:
 364         known = true; aarch32 = true;
 365     } else {
 366         SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
 367         bool aarch32_below_el3 = (have_el3 && scr.rw == 0);
 368
 369         HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
 370         bool aarch32_at_el1 = (aarch32_below_el3
 371                                || (have_el2
 372                                && !isSecureBelowEL3(tc) && hcr.rw == 0));
 373
 374         // Only know if EL0 using AArch32 from PSTATE
 375         if (el == EL0 && !aarch32_at_el1) {
 376             // EL0 controlled by PSTATE
 377             CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 378
 379             known = (currEL(tc) == EL0);
 380             aarch32 = (cpsr.width == 1);
 381         } else {
 382             known = true;
 383             aarch32 = (aarch32_below_el3 && el != EL3)
 384                       || (aarch32_at_el1 && (el == EL0 || el == EL1) );
 385         }
 386     }
 387
 388     return std::make_pair(known, aarch32);
 389 }
 390
 391 bool
 392 isBigEndian64(ThreadContext *tc)
 393 {
 394     switch (currEL(tc)) {
 395       case EL3:
 396         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).ee;
 397       case EL2:
 398         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).ee;
 399       case EL1:
 400         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).ee;
 401       case EL0:
 402         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).e0e;
 403       default:
 404         panic("Invalid exception level");
 405         break;
 406     }
 407 }
 408
 409 bool
 410 badMode32(ThreadContext *tc, OperatingMode mode)
 411 {
 412     return unknownMode32(mode) || !ArmSystem::haveEL(tc, opModeToEL(mode));
 413 }
 414
 415 bool
 416 badMode(ThreadContext *tc, OperatingMode mode)
 417 {
 418     return unknownMode(mode) || !ArmSystem::haveEL(tc, opModeToEL(mode));
 419 }
 420
 421 Addr
 422 purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
 423                  TTBCR tcr)
 424 {
 425     switch (el) {
 426       case EL0:
 427       case EL1:
 428         if (bits(addr, 55, 48) == 0xFF && tcr.tbi1)
 429             return addr | mask(63, 55);
 430         else if (!bits(addr, 55, 48) && tcr.tbi0)
 431             return bits(addr,55, 0);
 432         break;
 433       case EL2:
 434         assert(ArmSystem::haveVirtualization(tc));
 435         tcr = tc->readMiscReg(MISCREG_TCR_EL2);
 436         if (tcr.tbi)
 437             return addr & mask(56);
 438         break;
 439       case EL3:
 440         assert(ArmSystem::haveSecurity(tc));
 441         if (tcr.tbi)
 442             return addr & mask(56);
 443         break;
 444       default:
 445         panic("Invalid exception level");
 446         break;
 447     }
 448
 449     return addr;  // Nothing to do if this is not a tagged address
 450 }
 451
 452 Addr
 453 purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el)
 454 {
 455     TTBCR tcr;
 456
 457     switch (el) {
 458       case EL0:
 459       case EL1:
 460         tcr = tc->readMiscReg(MISCREG_TCR_EL1);
 461         if (bits(addr, 55, 48) == 0xFF && tcr.tbi1)
 462             return addr | mask(63, 55);
 463         else if (!bits(addr, 55, 48) && tcr.tbi0)
 464             return bits(addr,55, 0);
 465         break;
 466       case EL2:
 467         assert(ArmSystem::haveVirtualization(tc));
 468         tcr = tc->readMiscReg(MISCREG_TCR_EL2);
 469         if (tcr.tbi)
 470             return addr & mask(56);
 471         break;
 472       case EL3:
 473         assert(ArmSystem::haveSecurity(tc));
 474         tcr = tc->readMiscReg(MISCREG_TCR_EL3);
 475         if (tcr.tbi)
 476             return addr & mask(56);
 477         break;
 478       default:
 479         panic("Invalid exception level");
 480         break;
 481     }
 482
 483     return addr;  // Nothing to do if this is not a tagged address
 484 }
 485
 486 Addr
 487 truncPage(Addr addr)
 488 {
 489     return addr & ~(PageBytes - 1);
 490 }
 491
 492 Addr
 493 roundPage(Addr addr)
 494 {
 495     return (addr + PageBytes - 1) & ~(PageBytes - 1);
 496 }
 497
 498 bool
 499 mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss)
 500 {
 501     bool        isRead;
 502     uint32_t    crm;
 503     IntRegIndex rt;
 504     uint32_t    crn;
 505     uint32_t    opc1;
 506     uint32_t    opc2;
 507     bool        trapToHype = false;
 508
 509     const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 510     const HCR hcr = tc->readMiscReg(MISCREG_HCR);
 511     const SCR scr = tc->readMiscReg(MISCREG_SCR);
 512     const HDCR hdcr = tc->readMiscReg(MISCREG_HDCR);
 513     const HSTR hstr = tc->readMiscReg(MISCREG_HSTR);
 514     const HCPTR hcptr = tc->readMiscReg(MISCREG_HCPTR);
 515
 516     if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
 517         mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
 518         trapToHype  = ((uint32_t) hstr) & (1 << crn);
 519         trapToHype |= hdcr.tpm  && (crn == 9) && (crm >= 12);
 520         trapToHype |= hcr.tidcp && (
 521             ((crn ==  9) && ((crm <= 2) || ((crm >= 5) && (crm <= 8)))) ||
 522             ((crn == 10) && ((crm <= 1) ||  (crm == 4) || (crm == 8)))  ||
 523             ((crn == 11) && ((crm <= 8) ||  (crm == 15)))               );
 524
 525         if (!trapToHype) {
 526             switch (unflattenMiscReg(miscReg)) {
 527               case MISCREG_CPACR:
 528                 trapToHype = hcptr.tcpac;
 529                 break;
 530               case MISCREG_REVIDR:
 531               case MISCREG_TCMTR:
 532               case MISCREG_TLBTR:
 533               case MISCREG_AIDR:
 534                 trapToHype = hcr.tid1;
 535                 break;
 536               case MISCREG_CTR:
 537               case MISCREG_CCSIDR:
 538               case MISCREG_CLIDR:
 539               case MISCREG_CSSELR:
 540                 trapToHype = hcr.tid2;
 541                 break;
 542               case MISCREG_ID_PFR0:
 543               case MISCREG_ID_PFR1:
 544               case MISCREG_ID_DFR0:
 545               case MISCREG_ID_AFR0:
 546               case MISCREG_ID_MMFR0:
 547               case MISCREG_ID_MMFR1:
 548               case MISCREG_ID_MMFR2:
 549               case MISCREG_ID_MMFR3:
 550               case MISCREG_ID_ISAR0:
 551               case MISCREG_ID_ISAR1:
 552               case MISCREG_ID_ISAR2:
 553               case MISCREG_ID_ISAR3:
 554               case MISCREG_ID_ISAR4:
 555               case MISCREG_ID_ISAR5:
 556                 trapToHype = hcr.tid3;
 557                 break;
 558               case MISCREG_DCISW:
 559               case MISCREG_DCCSW:
 560               case MISCREG_DCCISW:
 561                 trapToHype = hcr.tsw;
 562                 break;
 563               case MISCREG_DCIMVAC:
 564               case MISCREG_DCCIMVAC:
 565               case MISCREG_DCCMVAC:
 566                 trapToHype = hcr.tpc;
 567                 break;
 568               case MISCREG_ICIMVAU:
 569               case MISCREG_ICIALLU:
 570               case MISCREG_ICIALLUIS:
 571               case MISCREG_DCCMVAU:
 572                 trapToHype = hcr.tpu;
 573                 break;
 574               case MISCREG_TLBIALLIS:
 575               case MISCREG_TLBIMVAIS:
 576               case MISCREG_TLBIASIDIS:
 577               case MISCREG_TLBIMVAAIS:
 578               case MISCREG_TLBIMVALIS:
 579               case MISCREG_TLBIMVAALIS:
 580               case MISCREG_DTLBIALL:
 581               case MISCREG_ITLBIALL:
 582               case MISCREG_DTLBIMVA:
 583               case MISCREG_ITLBIMVA:
 584               case MISCREG_DTLBIASID:
 585               case MISCREG_ITLBIASID:
 586               case MISCREG_TLBIMVAA:
 587               case MISCREG_TLBIALL:
 588               case MISCREG_TLBIMVA:
 589               case MISCREG_TLBIMVAL:
 590               case MISCREG_TLBIMVAAL:
 591               case MISCREG_TLBIASID:
 592                 trapToHype = hcr.ttlb;
 593                 break;
 594               case MISCREG_ACTLR:
 595                 trapToHype = hcr.tac;
 596                 break;
 597               case MISCREG_SCTLR:
 598               case MISCREG_TTBR0:
 599               case MISCREG_TTBR1:
 600               case MISCREG_TTBCR:
 601               case MISCREG_DACR:
 602               case MISCREG_DFSR:
 603               case MISCREG_IFSR:
 604               case MISCREG_DFAR:
 605               case MISCREG_IFAR:
 606               case MISCREG_ADFSR:
 607               case MISCREG_AIFSR:
 608               case MISCREG_PRRR:
 609               case MISCREG_NMRR:
 610               case MISCREG_MAIR0:
 611               case MISCREG_MAIR1:
 612               case MISCREG_CONTEXTIDR:
 613                 trapToHype = hcr.tvm & !isRead;
 614                 break;
 615               case MISCREG_PMCR:
 616                 trapToHype = hdcr.tpmcr;
 617                 break;
 618               // GICv3 regs
 619               case MISCREG_ICC_SGI0R:
 620                 if (tc->getIsaPtr()->haveGICv3CpuIfc())
 621                     trapToHype = hcr.fmo;
 622                 break;
 623               case MISCREG_ICC_SGI1R:
 624               case MISCREG_ICC_ASGI1R:
 625                 if (tc->getIsaPtr()->haveGICv3CpuIfc())
 626                     trapToHype = hcr.imo;
 627                 break;
 628               // No default action needed
 629               default:
 630                 break;
 631             }
 632         }
 633     }
 634     return trapToHype;
 635 }
 636
 637
 638 bool
 639 mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
 640                   HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
 641 {
 642     bool        isRead;
 643     uint32_t    crm;
 644     IntRegIndex rt;
 645     uint32_t    crn;
 646     uint32_t    opc1;
 647     uint32_t    opc2;
 648     bool        trapToHype = false;
 649
 650     if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
 651         mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
 652         inform("trap check M:%x N:%x 1:%x 2:%x hdcr %x, hcptr %x, hstr %x\n",
 653                 crm, crn, opc1, opc2, hdcr, hcptr, hstr);
 654         trapToHype  = hdcr.tda  && (opc1 == 0);
 655         trapToHype |= hcptr.tta && (opc1 == 1);
 656         if (!trapToHype) {
 657             switch (unflattenMiscReg(miscReg)) {
 658               case MISCREG_DBGOSLSR:
 659               case MISCREG_DBGOSLAR:
 660               case MISCREG_DBGOSDLR:
 661               case MISCREG_DBGPRCR:
 662                 trapToHype = hdcr.tdosa;
 663                 break;
 664               case MISCREG_DBGDRAR:
 665               case MISCREG_DBGDSAR:
 666                 trapToHype = hdcr.tdra;
 667                 break;
 668               case MISCREG_JIDR:
 669                 trapToHype = hcr.tid0;
 670                 break;
 671               case MISCREG_JOSCR:
 672               case MISCREG_JMCR:
 673                 trapToHype = hstr.tjdbx;
 674                 break;
 675               case MISCREG_TEECR:
 676               case MISCREG_TEEHBR:
 677                 trapToHype = hstr.ttee;
 678                 break;
 679               // No default action needed
 680               default:
 681                 break;
 682             }
 683         }
 684     }
 685     return trapToHype;
 686 }
 687
 688 bool
 689 mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr,
 690                     HCR hcr, uint32_t iss)
 691 {
 692     uint32_t    crm;
 693     IntRegIndex rt;
 694     uint32_t    crn;
 695     uint32_t    opc1;
 696     uint32_t    opc2;
 697     bool        isRead;
 698     bool        trapToHype = false;
 699
 700     if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
 701         // This is technically the wrong function, but we can re-use it for
 702         // the moment because we only need one field, which overlaps with the
 703         // mcrmrc layout
 704         mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
 705         trapToHype = ((uint32_t) hstr) & (1 << crm);
 706
 707         if (!trapToHype) {
 708             switch (unflattenMiscReg(miscReg)) {
 709               case MISCREG_SCTLR:
 710               case MISCREG_TTBR0:
 711               case MISCREG_TTBR1:
 712               case MISCREG_TTBCR:
 713               case MISCREG_DACR:
 714               case MISCREG_DFSR:
 715               case MISCREG_IFSR:
 716               case MISCREG_DFAR:
 717               case MISCREG_IFAR:
 718               case MISCREG_ADFSR:
 719               case MISCREG_AIFSR:
 720               case MISCREG_PRRR:
 721               case MISCREG_NMRR:
 722               case MISCREG_MAIR0:
 723               case MISCREG_MAIR1:
 724               case MISCREG_CONTEXTIDR:
 725                 trapToHype = hcr.tvm & !isRead;
 726                 break;
 727               // No default action needed
 728               default:
 729                 break;
 730             }
 731         }
 732     }
 733     return trapToHype;
 734 }
 735
 736 bool
 737 decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
 738                       CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
 739 {
 740     OperatingMode mode = MODE_UNDEFINED;
 741     bool          ok = true;
 742
 743     // R mostly indicates if its a int register or a misc reg, we override
 744     // below if the few corner cases
 745     isIntReg = !r;
 746     // Loosely based on ARM ARM issue C section B9.3.10
 747     if (r) {
 748         switch (sysM)
 749         {
 750           case 0xE:
 751             regIdx = MISCREG_SPSR_FIQ;
 752             mode   = MODE_FIQ;
 753             break;
 754           case 0x10:
 755             regIdx = MISCREG_SPSR_IRQ;
 756             mode   = MODE_IRQ;
 757             break;
 758           case 0x12:
 759             regIdx = MISCREG_SPSR_SVC;
 760             mode   = MODE_SVC;
 761             break;
 762           case 0x14:
 763             regIdx = MISCREG_SPSR_ABT;
 764             mode   = MODE_ABORT;
 765             break;
 766           case 0x16:
 767             regIdx = MISCREG_SPSR_UND;
 768             mode   = MODE_UNDEFINED;
 769             break;
 770           case 0x1C:
 771             regIdx = MISCREG_SPSR_MON;
 772             mode   = MODE_MON;
 773             break;
 774           case 0x1E:
 775             regIdx = MISCREG_SPSR_HYP;
 776             mode   = MODE_HYP;
 777             break;
 778           default:
 779             ok = false;
 780             break;
 781         }
 782     } else {
 783         int sysM4To3 = bits(sysM, 4, 3);
 784
 785         if (sysM4To3 == 0) {
 786             mode = MODE_USER;
 787             regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
 788         } else if (sysM4To3 == 1) {
 789             mode = MODE_FIQ;
 790             regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
 791         } else if (sysM4To3 == 3) {
 792             if (bits(sysM, 1) == 0) {
 793                 mode = MODE_MON;
 794                 regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
 795             } else {
 796                 mode = MODE_HYP;
 797                 if (bits(sysM, 0) == 1) {
 798                     regIdx = intRegInMode(mode, 13); // R13 in HYP
 799                 } else {
 800                     isIntReg = false;
 801                     regIdx   = MISCREG_ELR_HYP;
 802                 }
 803             }
 804         } else { // Other Banked registers
 805             int sysM2 = bits(sysM, 2);
 806             int sysM1 = bits(sysM, 1);
 807
 808             mode  = (OperatingMode) ( ((sysM2 ||  sysM1) << 0) |
 809                                       (1                 << 1) |
 810                                       ((sysM2 && !sysM1) << 2) |
 811                                       ((sysM2 &&  sysM1) << 3) |
 812                                       (1                 << 4) );
 813             regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
 814             // Don't flatten the register here. This is going to go through
 815             // setIntReg() which will do the flattening
 816             ok &= mode != cpsr.mode;
 817         }
 818     }
 819
 820     // Check that the requested register is accessable from the current mode
 821     if (ok && checkSecurity && mode != cpsr.mode) {
 822         switch (cpsr.mode)
 823         {
 824           case MODE_USER:
 825             ok = false;
 826             break;
 827           case MODE_FIQ:
 828             ok &=  mode != MODE_HYP;
 829             ok &= (mode != MODE_MON) || !scr.ns;
 830             break;
 831           case MODE_HYP:
 832             ok &=  mode != MODE_MON;
 833             ok &= (mode != MODE_FIQ) || !nsacr.rfr;
 834             break;
 835           case MODE_IRQ:
 836           case MODE_SVC:
 837           case MODE_ABORT:
 838           case MODE_UNDEFINED:
 839           case MODE_SYSTEM:
 840             ok &=  mode != MODE_HYP;
 841             ok &= (mode != MODE_MON) || !scr.ns;
 842             ok &= (mode != MODE_FIQ) || !nsacr.rfr;
 843             break;
 844           // can access everything, no further checks required
 845           case MODE_MON:
 846             break;
 847           default:
 848             panic("unknown Mode 0x%x\n", cpsr.mode);
 849             break;
 850         }
 851     }
 852     return (ok);
 853 }
 854
 855 bool
 856 SPAlignmentCheckEnabled(ThreadContext* tc)
 857 {
 858     switch (currEL(tc)) {
 859       case EL3:
 860         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).sa;
 861       case EL2:
 862         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).sa;
 863       case EL1:
 864         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa;
 865       case EL0:
 866         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa0;
 867       default:
 868         panic("Invalid exception level");
 869         break;
 870     }
 871 }
 872
 873 int
 874 decodePhysAddrRange64(uint8_t pa_enc)
 875 {
 876     switch (pa_enc) {
 877       case 0x0:
 878         return 32;
 879       case 0x1:
 880         return 36;
 881       case 0x2:
 882         return 40;
 883       case 0x3:
 884         return 42;
 885       case 0x4:
 886         return 44;
 887       case 0x5:
 888       case 0x6:
 889       case 0x7:
 890         return 48;
 891       default:
 892         panic("Invalid phys. address range encoding");
 893     }
 894 }
 895
 896 uint8_t
 897 encodePhysAddrRange64(int pa_size)
 898 {
 899     switch (pa_size) {
 900       case 32:
 901         return 0x0;
 902       case 36:
 903         return 0x1;
 904       case 40:
 905         return 0x2;
 906       case 42:
 907         return 0x3;
 908       case 44:
 909         return 0x4;
 910       case 48:
 911         return 0x5;
 912       default:
 913         panic("Invalid phys. address range");
 914     }
 915 }
 916
 917 } // namespace ArmISA