src/arch/arm/utility.hh

   1 /*
   2  * Copyright (c) 2010, 2012-2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2007-2008 The Florida State University
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Korey Sewell
  42  *          Stephen Hines
  43  */
  44
  45 #ifndef __ARCH_ARM_UTILITY_HH__
  46 #define __ARCH_ARM_UTILITY_HH__
  47
  48 #include "arch/arm/isa_traits.hh"
  49 #include "arch/arm/miscregs.hh"
  50 #include "arch/arm/types.hh"
  51 #include "base/misc.hh"
  52 #include "base/trace.hh"
  53 #include "base/types.hh"
  54 #include "cpu/static_inst.hh"
  55 #include "cpu/thread_context.hh"
  56
  57 class ArmSystem;
  58
  59 namespace ArmISA {
  60
  61 inline PCState
  62 buildRetPC(const PCState &curPC, const PCState &callPC)
  63 {
  64     PCState retPC = callPC;
  65     retPC.uEnd();
  66     return retPC;
  67 }
  68
  69 inline bool
  70 testPredicate(uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
  71 {
  72     bool n = (nz & 0x2);
  73     bool z = (nz & 0x1);
  74
  75     switch (code)
  76     {
  77         case COND_EQ: return  z;
  78         case COND_NE: return !z;
  79         case COND_CS: return  c;
  80         case COND_CC: return !c;
  81         case COND_MI: return  n;
  82         case COND_PL: return !n;
  83         case COND_VS: return  v;
  84         case COND_VC: return !v;
  85         case COND_HI: return  (c && !z);
  86         case COND_LS: return !(c && !z);
  87         case COND_GE: return !(n ^ v);
  88         case COND_LT: return  (n ^ v);
  89         case COND_GT: return !(n ^ v || z);
  90         case COND_LE: return  (n ^ v || z);
  91         case COND_AL: return true;
  92         case COND_UC: return true;
  93         default:
  94             panic("Unhandled predicate condition: %d\n", code);
  95     }
  96 }
  97
  98 /**
  99  * Function to insure ISA semantics about 0 registers.
 100  * @param tc The thread context.
 101  */
 102 template <class TC>
 103 void zeroRegisters(TC *tc);
 104
 105 inline void startupCPU(ThreadContext *tc, int cpuId)
 106 {
 107     tc->activate();
 108 }
 109
 110 void copyRegs(ThreadContext *src, ThreadContext *dest);
 111
 112 static inline void
 113 copyMiscRegs(ThreadContext *src, ThreadContext *dest)
 114 {
 115     panic("Copy Misc. Regs Not Implemented Yet\n");
 116 }
 117
 118 void initCPU(ThreadContext *tc, int cpuId);
 119
 120 static inline bool
 121 inUserMode(CPSR cpsr)
 122 {
 123     return cpsr.mode == MODE_USER || cpsr.mode == MODE_EL0T;
 124 }
 125
 126 static inline bool
 127 inUserMode(ThreadContext *tc)
 128 {
 129     return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR));
 130 }
 131
 132 static inline bool
 133 inPrivilegedMode(CPSR cpsr)
 134 {
 135     return !inUserMode(cpsr);
 136 }
 137
 138 static inline bool
 139 inPrivilegedMode(ThreadContext *tc)
 140 {
 141     return !inUserMode(tc);
 142 }
 143
 144 bool inAArch64(ThreadContext *tc);
 145
 146 static inline OperatingMode
 147 currOpMode(ThreadContext *tc)
 148 {
 149     CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 150     return (OperatingMode) (uint8_t) cpsr.mode;
 151 }
 152
 153 static inline ExceptionLevel
 154 currEL(ThreadContext *tc)
 155 {
 156     CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 157     return (ExceptionLevel) (uint8_t) cpsr.el;
 158 }
 159
 160 bool ELIs64(ThreadContext *tc, ExceptionLevel el);
 161
 162 bool isBigEndian64(ThreadContext *tc);
 163
 164 /**
 165  * Removes the tag from tagged addresses if that mode is enabled.
 166  * @param addr The address to be purified.
 167  * @param tc The thread context.
 168  * @param el The controlled exception level.
 169  * @return The purified address.
 170  */
 171 Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
 172                       TTBCR tcr);
 173 Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el);
 174
 175 static inline bool
 176 inSecureState(SCR scr, CPSR cpsr)
 177 {
 178     switch ((OperatingMode) (uint8_t) cpsr.mode) {
 179       case MODE_MON:
 180       case MODE_EL3T:
 181       case MODE_EL3H:
 182         return true;
 183       case MODE_HYP:
 184       case MODE_EL2T:
 185       case MODE_EL2H:
 186         return false;
 187       default:
 188         return !scr.ns;
 189     }
 190 }
 191
 192 bool longDescFormatInUse(ThreadContext *tc);
 193
 194 bool inSecureState(ThreadContext *tc);
 195
 196 uint32_t getMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
 197
 198 static inline uint32_t
 199 mcrMrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn,
 200                uint32_t opc1, uint32_t opc2)
 201 {
 202     return (isRead <<  0) |
 203            (crm    <<  1) |
 204            (rt     <<  5) |
 205            (crn    << 10) |
 206            (opc1   << 14) |
 207            (opc2   << 17);
 208 }
 209
 210 static inline void
 211 mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt,
 212                  uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
 213 {
 214     isRead = (iss >>  0) & 0x1;
 215     crm    = (iss >>  1) & 0xF;
 216     rt     = (IntRegIndex) ((iss >>  5) & 0xF);
 217     crn    = (iss >> 10) & 0xF;
 218     opc1   = (iss >> 14) & 0x7;
 219     opc2   = (iss >> 17) & 0x7;
 220 }
 221
 222 static inline uint32_t
 223 mcrrMrrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex rt2,
 224                  uint32_t opc1)
 225 {
 226     return (isRead <<  0) |
 227            (crm    <<  1) |
 228            (rt     <<  5) |
 229            (rt2    << 10) |
 230            (opc1   << 16);
 231 }
 232
 233 static inline uint32_t
 234 msrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn,
 235                  uint32_t crm, uint32_t op2, IntRegIndex rt)
 236 {
 237     return isRead |
 238         (crm << 1) |
 239         (rt << 5) |
 240         (crn << 10) |
 241         (op1 << 14) |
 242         (op2 << 17) |
 243         (op0 << 20);
 244 }
 245
 246 bool
 247 mcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
 248                   HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss);
 249 bool
 250 mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
 251                   HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss);
 252 bool
 253 mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr,
 254                     HCR hcr, uint32_t iss);
 255
 256 bool msrMrs64TrapToSup(const MiscRegIndex miscReg, ExceptionLevel el,
 257                        CPACR cpacr);
 258 bool msrMrs64TrapToHyp(const MiscRegIndex miscReg, bool isRead, CPTR cptr,
 259                        HCR hcr, bool * isVfpNeon);
 260 bool msrMrs64TrapToMon(const MiscRegIndex miscReg, CPTR cptr,
 261                        ExceptionLevel el, bool * isVfpNeon);
 262
 263 bool
 264 vfpNeonEnabled(uint32_t &seq, HCPTR hcptr, NSACR nsacr, CPACR cpacr, CPSR cpsr,
 265                uint32_t &iss, bool &trap, ThreadContext *tc,
 266                FPEXC fpexc = (1<<30), bool isSIMD = false);
 267
 268 static inline bool
 269 vfpNeon64Enabled(CPACR cpacr, ExceptionLevel el)
 270 {
 271     if ((el == EL0 && cpacr.fpen != 0x3) ||
 272         (el == EL1 && !(cpacr.fpen & 0x1)))
 273         return false;
 274     return true;
 275 }
 276
 277 bool SPAlignmentCheckEnabled(ThreadContext* tc);
 278
 279 uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
 280
 281 void skipFunction(ThreadContext *tc);
 282
 283 inline void
 284 advancePC(PCState &pc, const StaticInstPtr &inst)
 285 {
 286     inst->advancePC(pc);
 287 }
 288
 289 Addr truncPage(Addr addr);
 290 Addr roundPage(Addr addr);
 291
 292 inline uint64_t
 293 getExecutingAsid(ThreadContext *tc)
 294 {
 295     return tc->readMiscReg(MISCREG_CONTEXTIDR);
 296 }
 297
 298 // Decodes the register index to access based on the fields used in a MSR
 299 // or MRS instruction
 300 bool
 301 decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
 302                       CPSR cpsr, SCR scr, NSACR nsacr,
 303                       bool checkSecurity = true);
 304
 305 // This wrapper function is used to turn the register index into a source
 306 // parameter for the instruction. See Operands.isa
 307 static inline int
 308 decodeMrsMsrBankedIntRegIndex(uint8_t sysM, bool r)
 309 {
 310     int  regIdx;
 311     bool isIntReg;
 312     bool validReg;
 313
 314     validReg = decodeMrsMsrBankedReg(sysM, r, isIntReg, regIdx, 0, 0, 0, false);
 315     return (validReg && isIntReg) ? regIdx : INTREG_DUMMY;
 316 }
 317
 318 /**
 319  * Returns the n. of PA bits corresponding to the specified encoding.
 320  */
 321 int decodePhysAddrRange64(uint8_t pa_enc);
 322
 323 /**
 324  * Returns the encoding corresponding to the specified n. of PA bits.
 325  */
 326 uint8_t encodePhysAddrRange64(int pa_size);
 327
 328 }
 329
 330 #endif