src/arch/arm/utility.hh

   1 /*
   2  * Copyright (c) 2010 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2007-2008 The Florida State University
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Korey Sewell
  42  *          Stephen Hines
  43  */
  44
  45 #ifndef __ARCH_ARM_UTILITY_HH__
  46 #define __ARCH_ARM_UTILITY_HH__
  47
  48 #include "arch/arm/isa_traits.hh"
  49 #include "arch/arm/miscregs.hh"
  50 #include "arch/arm/types.hh"
  51 #include "base/misc.hh"
  52 #include "base/trace.hh"
  53 #include "base/types.hh"
  54 #include "cpu/static_inst.hh"
  55 #include "cpu/thread_context.hh"
  56
  57 namespace ArmISA {
  58
  59 inline PCState
  60 buildRetPC(const PCState &curPC, const PCState &callPC)
  61 {
  62     PCState retPC = callPC;
  63     retPC.uEnd();
  64     return retPC;
  65 }
  66
  67 inline bool
  68 testPredicate(uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
  69 {
  70     bool n = (nz & 0x2);
  71     bool z = (nz & 0x1);
  72
  73     switch (code)
  74     {
  75         case COND_EQ: return  z;
  76         case COND_NE: return !z;
  77         case COND_CS: return  c;
  78         case COND_CC: return !c;
  79         case COND_MI: return  n;
  80         case COND_PL: return !n;
  81         case COND_VS: return  v;
  82         case COND_VC: return !v;
  83         case COND_HI: return  (c && !z);
  84         case COND_LS: return !(c && !z);
  85         case COND_GE: return !(n ^ v);
  86         case COND_LT: return  (n ^ v);
  87         case COND_GT: return !(n ^ v || z);
  88         case COND_LE: return  (n ^ v || z);
  89         case COND_AL: return true;
  90         case COND_UC: return true;
  91         default:
  92             panic("Unhandled predicate condition: %d\n", code);
  93     }
  94 }
  95
  96 /**
  97  * Function to insure ISA semantics about 0 registers.
  98  * @param tc The thread context.
  99  */
 100 template <class TC>
 101 void zeroRegisters(TC *tc);
 102
 103 inline void startupCPU(ThreadContext *tc, int cpuId)
 104 {
 105     tc->activate(Cycles(0));
 106 }
 107
 108 void copyRegs(ThreadContext *src, ThreadContext *dest);
 109
 110 static inline void
 111 copyMiscRegs(ThreadContext *src, ThreadContext *dest)
 112 {
 113     panic("Copy Misc. Regs Not Implemented Yet\n");
 114 }
 115
 116 void initCPU(ThreadContext *tc, int cpuId);
 117
 118 static inline bool
 119 inUserMode(CPSR cpsr)
 120 {
 121     return cpsr.mode == MODE_USER;
 122 }
 123
 124 static inline bool
 125 inUserMode(ThreadContext *tc)
 126 {
 127     return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR));
 128 }
 129
 130 static inline bool
 131 inPrivilegedMode(CPSR cpsr)
 132 {
 133     return !inUserMode(cpsr);
 134 }
 135
 136 static inline bool
 137 inPrivilegedMode(ThreadContext *tc)
 138 {
 139     return !inUserMode(tc);
 140 }
 141
 142 static inline bool
 143 vfpEnabled(CPACR cpacr, CPSR cpsr)
 144 {
 145     return cpacr.cp10 == 0x3 ||
 146         (cpacr.cp10 == 0x1 && inPrivilegedMode(cpsr));
 147 }
 148
 149 static inline bool
 150 vfpEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc)
 151 {
 152     if ((cpacr.cp11 == 0x3) ||
 153         ((cpacr.cp11 == 0x1) && inPrivilegedMode(cpsr)))
 154         return fpexc.en && vfpEnabled(cpacr, cpsr);
 155     else
 156         return fpexc.en && vfpEnabled(cpacr, cpsr) &&
 157             (cpacr.cp11 == cpacr.cp10);
 158 }
 159
 160 static inline bool
 161 neonEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc)
 162 {
 163     return !cpacr.asedis && vfpEnabled(cpacr, cpsr, fpexc);
 164 }
 165
 166 uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
 167
 168 void skipFunction(ThreadContext *tc);
 169
 170 inline void
 171 advancePC(PCState &pc, const StaticInstPtr inst)
 172 {
 173     inst->advancePC(pc);
 174 }
 175
 176 Addr truncPage(Addr addr);
 177 Addr roundPage(Addr addr);
 178
 179 inline uint64_t
 180 getExecutingAsid(ThreadContext *tc)
 181 {
 182     return tc->readMiscReg(MISCREG_CONTEXTIDR);
 183 }
 184
 185 }
 186
 187 #endif