src/arch/arm/utility.hh

   1 /*
   2  * Copyright (c) 2010, 2012-2013, 2016-2020 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2007-2008 The Florida State University
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  */
  41
  42 #ifndef __ARCH_ARM_UTILITY_HH__
  43 #define __ARCH_ARM_UTILITY_HH__
  44
  45 #include "arch/arm/isa_traits.hh"
  46 #include "arch/arm/miscregs.hh"
  47 #include "arch/arm/types.hh"
  48 #include "base/logging.hh"
  49 #include "base/trace.hh"
  50 #include "base/types.hh"
  51 #include "cpu/static_inst.hh"
  52 #include "cpu/thread_context.hh"
  53
  54 class ArmSystem;
  55
  56 namespace ArmISA {
  57
  58 inline PCState
  59 buildRetPC(const PCState &curPC, const PCState &callPC)
  60 {
  61     PCState retPC = callPC;
  62     retPC.uEnd();
  63     return retPC;
  64 }
  65
  66 inline bool
  67 testPredicate(uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
  68 {
  69     bool n = (nz & 0x2);
  70     bool z = (nz & 0x1);
  71
  72     switch (code)
  73     {
  74         case COND_EQ: return  z;
  75         case COND_NE: return !z;
  76         case COND_CS: return  c;
  77         case COND_CC: return !c;
  78         case COND_MI: return  n;
  79         case COND_PL: return !n;
  80         case COND_VS: return  v;
  81         case COND_VC: return !v;
  82         case COND_HI: return  (c && !z);
  83         case COND_LS: return !(c && !z);
  84         case COND_GE: return !(n ^ v);
  85         case COND_LT: return  (n ^ v);
  86         case COND_GT: return !(n ^ v || z);
  87         case COND_LE: return  (n ^ v || z);
  88         case COND_AL: return true;
  89         case COND_UC: return true;
  90         default:
  91             panic("Unhandled predicate condition: %d\n", code);
  92     }
  93 }
  94
  95 void copyRegs(ThreadContext *src, ThreadContext *dest);
  96
  97 static inline void
  98 copyMiscRegs(ThreadContext *src, ThreadContext *dest)
  99 {
 100     panic("Copy Misc. Regs Not Implemented Yet\n");
 101 }
 102
 103 /** Send an event (SEV) to a specific PE if there isn't
 104  * already a pending event */
 105 void sendEvent(ThreadContext *tc);
 106
 107 static inline bool
 108 inUserMode(CPSR cpsr)
 109 {
 110     return cpsr.mode == MODE_USER || cpsr.mode == MODE_EL0T;
 111 }
 112
 113 static inline bool
 114 inUserMode(ThreadContext *tc)
 115 {
 116     return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR));
 117 }
 118
 119 static inline bool
 120 inPrivilegedMode(CPSR cpsr)
 121 {
 122     return !inUserMode(cpsr);
 123 }
 124
 125 static inline bool
 126 inPrivilegedMode(ThreadContext *tc)
 127 {
 128     return !inUserMode(tc);
 129 }
 130
 131 bool inAArch64(ThreadContext *tc);
 132
 133 static inline OperatingMode
 134 currOpMode(const ThreadContext *tc)
 135 {
 136     CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
 137     return (OperatingMode) (uint8_t) cpsr.mode;
 138 }
 139
 140 static inline ExceptionLevel
 141 currEL(const ThreadContext *tc)
 142 {
 143     return opModeToEL(currOpMode(tc));
 144 }
 145
 146 inline ExceptionLevel
 147 currEL(CPSR cpsr)
 148 {
 149     return opModeToEL((OperatingMode) (uint8_t)cpsr.mode);
 150 }
 151
 152 bool HaveVirtHostExt(ThreadContext *tc);
 153 bool HaveSecureEL2Ext(ThreadContext *tc);
 154 bool IsSecureEL2Enabled(ThreadContext *tc);
 155 bool EL2Enabled(ThreadContext *tc);
 156
 157 /**
 158  * This function checks whether selected EL provided as an argument
 159  * is using the AArch32 ISA. This information might be unavailable
 160  * at the current EL status: it hence returns a pair of boolean values:
 161  * a first boolean, true if information is available (known),
 162  * and a second one, true if EL is using AArch32, false for AArch64.
 163  *
 164  * @param tc The thread context.
 165  * @param el The target exception level.
 166  * @retval known is FALSE for EL0 if the current Exception level
 167  *               is not EL0 and EL1 is using AArch64, since it cannot
 168  *               determine the state of EL0; TRUE otherwise.
 169  * @retval aarch32 is TRUE if the specified Exception level is using AArch32;
 170  *                 FALSE otherwise.
 171  */
 172 std::pair<bool, bool>
 173 ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el);
 174
 175 std::pair<bool, bool>
 176 ELStateUsingAArch32K(ThreadContext *tc, ExceptionLevel el, bool secure);
 177
 178 bool
 179 ELStateUsingAArch32(ThreadContext *tc, ExceptionLevel el, bool secure);
 180
 181 bool ELIs32(ThreadContext *tc, ExceptionLevel el);
 182
 183 bool ELIs64(ThreadContext *tc, ExceptionLevel el);
 184
 185 /**
 186  * Returns true if the current exception level `el` is executing a Host OS or
 187  * an application of a Host OS (Armv8.1 Virtualization Host Extensions).
 188  */
 189 bool ELIsInHost(ThreadContext *tc, ExceptionLevel el);
 190
 191 ExceptionLevel debugTargetFrom(ThreadContext *tc, bool secure);
 192
 193 bool isBigEndian64(const ThreadContext *tc);
 194
 195
 196 /**
 197  * badMode is checking if the execution mode provided as an argument is
 198  * valid and implemented for AArch32
 199  *
 200  * @param tc ThreadContext
 201  * @param mode OperatingMode to check
 202  * @return false if mode is valid and implemented, true otherwise
 203  */
 204 bool badMode32(ThreadContext *tc, OperatingMode mode);
 205
 206 /**
 207  * badMode is checking if the execution mode provided as an argument is
 208  * valid and implemented.
 209  *
 210  * @param tc ThreadContext
 211  * @param mode OperatingMode to check
 212  * @return false if mode is valid and implemented, true otherwise
 213  */
 214 bool badMode(ThreadContext *tc, OperatingMode mode);
 215
 216 static inline uint8_t
 217 itState(CPSR psr)
 218 {
 219     ITSTATE it = 0;
 220     it.top6 = psr.it2;
 221     it.bottom2 = psr.it1;
 222
 223     return (uint8_t)it;
 224 }
 225
 226 ExceptionLevel s1TranslationRegime(ThreadContext* tc, ExceptionLevel el);
 227
 228 /**
 229  * Removes the tag from tagged addresses if that mode is enabled.
 230  * @param addr The address to be purified.
 231  * @param tc The thread context.
 232  * @param el The controlled exception level.
 233  * @return The purified address.
 234  */
 235 Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
 236                       TCR tcr, bool isInstr);
 237 Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
 238                       bool isInstr);
 239 int computeAddrTop(ThreadContext *tc, bool selbit, bool isInstr,
 240                TCR tcr, ExceptionLevel el);
 241
 242 static inline bool
 243 inSecureState(SCR scr, CPSR cpsr)
 244 {
 245     switch ((OperatingMode) (uint8_t) cpsr.mode) {
 246       case MODE_MON:
 247       case MODE_EL3T:
 248       case MODE_EL3H:
 249         return true;
 250       case MODE_HYP:
 251       case MODE_EL2T:
 252       case MODE_EL2H:
 253         return false;
 254       default:
 255         return !scr.ns;
 256     }
 257 }
 258
 259 bool inSecureState(ThreadContext *tc);
 260
 261 bool isSecureBelowEL3(ThreadContext *tc);
 262
 263 bool longDescFormatInUse(ThreadContext *tc);
 264
 265 /** This helper function is either returing the value of
 266  * MPIDR_EL1 (by calling getMPIDR), or it is issuing a read
 267  * to VMPIDR_EL2 (as it happens in virtualized systems) */
 268 RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
 269
 270 /** This helper function is returning the value of MPIDR_EL1 */
 271 RegVal getMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
 272
 273 /** Retrieves MPIDR_EL1.{Aff2,Aff1,Aff0} affinity numbers */
 274 RegVal getAffinity(ArmSystem *arm_sys, ThreadContext *tc);
 275
 276 static inline uint32_t
 277 mcrMrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn,
 278                uint32_t opc1, uint32_t opc2)
 279 {
 280     return (isRead <<  0) |
 281            (crm    <<  1) |
 282            (rt     <<  5) |
 283            (crn    << 10) |
 284            (opc1   << 14) |
 285            (opc2   << 17);
 286 }
 287
 288 static inline void
 289 mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt,
 290                  uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
 291 {
 292     isRead = (iss >>  0) & 0x1;
 293     crm    = (iss >>  1) & 0xF;
 294     rt     = (IntRegIndex) ((iss >>  5) & 0xF);
 295     crn    = (iss >> 10) & 0xF;
 296     opc1   = (iss >> 14) & 0x7;
 297     opc2   = (iss >> 17) & 0x7;
 298 }
 299
 300 static inline uint32_t
 301 mcrrMrrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex rt2,
 302                  uint32_t opc1)
 303 {
 304     return (isRead <<  0) |
 305            (crm    <<  1) |
 306            (rt     <<  5) |
 307            (rt2    << 10) |
 308            (opc1   << 16);
 309 }
 310
 311 static inline uint32_t
 312 msrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn,
 313                  uint32_t crm, uint32_t op2, IntRegIndex rt)
 314 {
 315     return isRead |
 316         (crm << 1) |
 317         (rt << 5) |
 318         (crn << 10) |
 319         (op1 << 14) |
 320         (op2 << 17) |
 321         (op0 << 20);
 322 }
 323
 324 Fault
 325 mcrMrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst,
 326              ThreadContext *tc, uint32_t imm);
 327 bool
 328 mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss,
 329                   ExceptionClass *ec = nullptr);
 330
 331 bool
 332 mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
 333                   HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss);
 334
 335 Fault
 336 mcrrMrrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst,
 337                ThreadContext *tc, uint32_t imm);
 338 bool
 339 mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc,
 340                     uint32_t iss, ExceptionClass *ec = nullptr);
 341
 342 Fault
 343 AArch64AArch32SystemAccessTrap(const MiscRegIndex miscReg,
 344                                ExtMachInst machInst, ThreadContext *tc,
 345                                uint32_t imm, ExceptionClass ec);
 346 bool
 347 isAArch64AArch32SystemAccessTrapEL1(const MiscRegIndex miscReg,
 348                                     ThreadContext *tc);
 349 bool
 350 isAArch64AArch32SystemAccessTrapEL2(const MiscRegIndex miscReg,
 351                                     ThreadContext *tc);
 352 bool
 353 isGenericTimerHypTrap(const MiscRegIndex miscReg, ThreadContext *tc,
 354                       ExceptionClass *ec);
 355 bool condGenericTimerPhysHypTrap(const MiscRegIndex miscReg,
 356                                  ThreadContext *tc);
 357 bool
 358 isGenericTimerCommonEL0HypTrap(const MiscRegIndex miscReg, ThreadContext *tc,
 359                                ExceptionClass *ec);
 360 bool
 361 isGenericTimerPhysHypTrap(const MiscRegIndex miscReg, ThreadContext *tc,
 362                           ExceptionClass *ec);
 363 bool
 364 condGenericTimerPhysHypTrap(const MiscRegIndex miscReg, ThreadContext *tc);
 365 bool
 366 isGenericTimerSystemAccessTrapEL1(const MiscRegIndex miscReg,
 367                                   ThreadContext *tc);
 368 bool
 369 condGenericTimerSystemAccessTrapEL1(const MiscRegIndex miscReg,
 370                                     ThreadContext *tc);
 371 bool
 372 isGenericTimerSystemAccessTrapEL2(const MiscRegIndex miscReg,
 373                                   ThreadContext *tc);
 374 bool
 375 isGenericTimerCommonEL0SystemAccessTrapEL2(const MiscRegIndex miscReg,
 376                                            ThreadContext *tc);
 377 bool
 378 isGenericTimerPhysEL0SystemAccessTrapEL2(const MiscRegIndex miscReg,
 379                                          ThreadContext *tc);
 380 bool
 381 isGenericTimerPhysEL1SystemAccessTrapEL2(const MiscRegIndex miscReg,
 382                                          ThreadContext *tc);
 383 bool
 384 isGenericTimerVirtSystemAccessTrapEL2(const MiscRegIndex miscReg,
 385                                       ThreadContext *tc);
 386 bool
 387 condGenericTimerCommonEL0SystemAccessTrapEL2(const MiscRegIndex miscReg,
 388                                              ThreadContext *tc);
 389 bool
 390 condGenericTimerCommonEL1SystemAccessTrapEL2(const MiscRegIndex miscReg,
 391                                              ThreadContext *tc);
 392 bool
 393 condGenericTimerPhysEL1SystemAccessTrapEL2(const MiscRegIndex miscReg,
 394                                            ThreadContext *tc);
 395 bool
 396 isGenericTimerSystemAccessTrapEL3(const MiscRegIndex miscReg,
 397                                   ThreadContext *tc);
 398
 399 bool SPAlignmentCheckEnabled(ThreadContext* tc);
 400
 401 uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
 402
 403 inline void
 404 advancePC(PCState &pc, const StaticInstPtr &inst)
 405 {
 406     inst->advancePC(pc);
 407 }
 408
 409 Addr truncPage(Addr addr);
 410 Addr roundPage(Addr addr);
 411
 412 inline uint64_t
 413 getExecutingAsid(ThreadContext *tc)
 414 {
 415     return tc->readMiscReg(MISCREG_CONTEXTIDR);
 416 }
 417
 418 // Decodes the register index to access based on the fields used in a MSR
 419 // or MRS instruction
 420 bool
 421 decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
 422                       CPSR cpsr, SCR scr, NSACR nsacr,
 423                       bool checkSecurity = true);
 424
 425 // This wrapper function is used to turn the register index into a source
 426 // parameter for the instruction. See Operands.isa
 427 static inline int
 428 decodeMrsMsrBankedIntRegIndex(uint8_t sysM, bool r)
 429 {
 430     int  regIdx;
 431     bool isIntReg;
 432     bool validReg;
 433
 434     validReg = decodeMrsMsrBankedReg(sysM, r, isIntReg, regIdx, 0, 0, 0, false);
 435     return (validReg && isIntReg) ? regIdx : INTREG_DUMMY;
 436 }
 437
 438 /**
 439  * Returns the n. of PA bits corresponding to the specified encoding.
 440  */
 441 int decodePhysAddrRange64(uint8_t pa_enc);
 442
 443 /**
 444  * Returns the encoding corresponding to the specified n. of PA bits.
 445  */
 446 uint8_t encodePhysAddrRange64(int pa_size);
 447
 448 inline ByteOrder byteOrder(const ThreadContext *tc)
 449 {
 450     return isBigEndian64(tc) ? BigEndianByteOrder : LittleEndianByteOrder;
 451 };
 452
 453 bool isUnpriviledgeAccess(ThreadContext * tc);
 454
 455 }
 456 #endif