2 * Copyright (c) 2010, 2012-2013, 2016-2019 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * Authors: Korey Sewell
45 #ifndef __ARCH_ARM_UTILITY_HH__
46 #define __ARCH_ARM_UTILITY_HH__
48 #include "arch/arm/isa_traits.hh"
49 #include "arch/arm/miscregs.hh"
50 #include "arch/arm/types.hh"
51 #include "base/logging.hh"
52 #include "base/trace.hh"
53 #include "base/types.hh"
54 #include "cpu/static_inst.hh"
55 #include "cpu/thread_context.hh"
62 buildRetPC(const PCState &curPC, const PCState &callPC)
64 PCState retPC = callPC;
70 testPredicate(uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
77 case COND_EQ: return z;
78 case COND_NE: return !z;
79 case COND_CS: return c;
80 case COND_CC: return !c;
81 case COND_MI: return n;
82 case COND_PL: return !n;
83 case COND_VS: return v;
84 case COND_VC: return !v;
85 case COND_HI: return (c && !z);
86 case COND_LS: return !(c && !z);
87 case COND_GE: return !(n ^ v);
88 case COND_LT: return (n ^ v);
89 case COND_GT: return !(n ^ v || z);
90 case COND_LE: return (n ^ v || z);
91 case COND_AL: return true;
92 case COND_UC: return true;
94 panic("Unhandled predicate condition: %d\n", code);
99 * Function to insure ISA semantics about 0 registers.
100 * @param tc The thread context.
103 void zeroRegisters(TC *tc);
105 inline void startupCPU(ThreadContext *tc, int cpuId)
110 void copyRegs(ThreadContext *src, ThreadContext *dest);
113 copyMiscRegs(ThreadContext *src, ThreadContext *dest)
115 panic("Copy Misc. Regs Not Implemented Yet\n");
118 void initCPU(ThreadContext *tc, int cpuId);
120 /** Send an event (SEV) to a specific PE if there isn't
121 * already a pending event */
122 void sendEvent(ThreadContext *tc);
125 inUserMode(CPSR cpsr)
127 return cpsr.mode == MODE_USER || cpsr.mode == MODE_EL0T;
131 inUserMode(ThreadContext *tc)
133 return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR));
137 inPrivilegedMode(CPSR cpsr)
139 return !inUserMode(cpsr);
143 inPrivilegedMode(ThreadContext *tc)
145 return !inUserMode(tc);
148 bool inAArch64(ThreadContext *tc);
150 static inline OperatingMode
151 currOpMode(ThreadContext *tc)
153 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
154 return (OperatingMode) (uint8_t) cpsr.mode;
157 static inline ExceptionLevel
158 currEL(ThreadContext *tc)
160 return opModeToEL(currOpMode(tc));
163 inline ExceptionLevel
166 return opModeToEL((OperatingMode) (uint8_t)cpsr.mode);
169 bool HaveVirtHostExt(ThreadContext *tc);
170 bool HaveSecureEL2Ext(ThreadContext *tc);
171 bool IsSecureEL2Enabled(ThreadContext *tc);
172 bool EL2Enabled(ThreadContext *tc);
175 * This function checks whether selected EL provided as an argument
176 * is using the AArch32 ISA. This information might be unavailable
177 * at the current EL status: it hence returns a pair of boolean values:
178 * a first boolean, true if information is available (known),
179 * and a second one, true if EL is using AArch32, false for AArch64.
181 * @param tc The thread context.
182 * @param el The target exception level.
183 * @retval known is FALSE for EL0 if the current Exception level
184 * is not EL0 and EL1 is using AArch64, since it cannot
185 * determine the state of EL0; TRUE otherwise.
186 * @retval aarch32 is TRUE if the specified Exception level is using AArch32;
189 std::pair<bool, bool>
190 ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el);
192 bool ELIs32(ThreadContext *tc, ExceptionLevel el);
194 bool ELIs64(ThreadContext *tc, ExceptionLevel el);
197 * Returns true if the current exception level `el` is executing a Host OS or
198 * an application of a Host OS (Armv8.1 Virtualization Host Extensions).
200 bool ELIsInHost(ThreadContext *tc, ExceptionLevel el);
202 bool isBigEndian64(ThreadContext *tc);
205 * badMode is checking if the execution mode provided as an argument is
206 * valid and implemented for AArch32
208 * @param tc ThreadContext
209 * @param mode OperatingMode to check
210 * @return false if mode is valid and implemented, true otherwise
212 bool badMode32(ThreadContext *tc, OperatingMode mode);
215 * badMode is checking if the execution mode provided as an argument is
216 * valid and implemented.
218 * @param tc ThreadContext
219 * @param mode OperatingMode to check
220 * @return false if mode is valid and implemented, true otherwise
222 bool badMode(ThreadContext *tc, OperatingMode mode);
224 static inline uint8_t
229 it.bottom2 = psr.it1;
235 * Removes the tag from tagged addresses if that mode is enabled.
236 * @param addr The address to be purified.
237 * @param tc The thread context.
238 * @param el The controlled exception level.
239 * @return The purified address.
241 Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
243 Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el);
246 inSecureState(SCR scr, CPSR cpsr)
248 switch ((OperatingMode) (uint8_t) cpsr.mode) {
262 bool inSecureState(ThreadContext *tc);
265 * Return TRUE if an Exception level below EL3 is in Secure state.
266 * Differs from inSecureState in that it ignores the current EL
267 * or Mode in considering security state.
269 inline bool isSecureBelowEL3(ThreadContext *tc);
271 bool longDescFormatInUse(ThreadContext *tc);
273 /** This helper function is either returing the value of
274 * MPIDR_EL1 (by calling getMPIDR), or it is issuing a read
275 * to VMPIDR_EL2 (as it happens in virtualized systems) */
276 RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
278 /** This helper function is returing the value of MPIDR_EL1 */
279 RegVal getMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
281 static inline uint32_t
282 mcrMrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn,
283 uint32_t opc1, uint32_t opc2)
285 return (isRead << 0) |
294 mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt,
295 uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
297 isRead = (iss >> 0) & 0x1;
298 crm = (iss >> 1) & 0xF;
299 rt = (IntRegIndex) ((iss >> 5) & 0xF);
300 crn = (iss >> 10) & 0xF;
301 opc1 = (iss >> 14) & 0x7;
302 opc2 = (iss >> 17) & 0x7;
305 static inline uint32_t
306 mcrrMrrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex rt2,
309 return (isRead << 0) |
316 static inline uint32_t
317 msrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn,
318 uint32_t crm, uint32_t op2, IntRegIndex rt)
330 mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss);
333 mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
334 HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss);
336 mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr,
337 HCR hcr, uint32_t iss);
339 bool SPAlignmentCheckEnabled(ThreadContext* tc);
341 uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
343 void skipFunction(ThreadContext *tc);
346 advancePC(PCState &pc, const StaticInstPtr &inst)
351 Addr truncPage(Addr addr);
352 Addr roundPage(Addr addr);
355 getExecutingAsid(ThreadContext *tc)
357 return tc->readMiscReg(MISCREG_CONTEXTIDR);
360 // Decodes the register index to access based on the fields used in a MSR
361 // or MRS instruction
363 decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int ®Idx,
364 CPSR cpsr, SCR scr, NSACR nsacr,
365 bool checkSecurity = true);
367 // This wrapper function is used to turn the register index into a source
368 // parameter for the instruction. See Operands.isa
370 decodeMrsMsrBankedIntRegIndex(uint8_t sysM, bool r)
376 validReg = decodeMrsMsrBankedReg(sysM, r, isIntReg, regIdx, 0, 0, 0, false);
377 return (validReg && isIntReg) ? regIdx : INTREG_DUMMY;
381 * Returns the n. of PA bits corresponding to the specified encoding.
383 int decodePhysAddrRange64(uint8_t pa_enc);
386 * Returns the encoding corresponding to the specified n. of PA bits.
388 uint8_t encodePhysAddrRange64(int pa_size);
390 inline ByteOrder byteOrder(ThreadContext *tc)
392 return isBigEndian64(tc) ? BigEndianByteOrder : LittleEndianByteOrder;