src/arch/gcn3/gpu_isa.hh

   1 /*
   2  * Copyright (c) 2016-2018 Advanced Micro Devices, Inc.
   3  * All rights reserved.
   4  *
   5  * For use for simulation and test purposes only
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  * this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright notice,
  14  * this list of conditions and the following disclaimer in the documentation
  15  * and/or other materials provided with the distribution.
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  * contributors may be used to endorse or promote products derived from this
  19  * software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * Authors: Anthony Gutierrez
  34  */
  35
  36 #ifndef __ARCH_GCN3_GPU_ISA_HH__
  37 #define __ARCH_GCN3_GPU_ISA_HH__
  38
  39 #include <array>
  40 #include <type_traits>
  41
  42 #include "arch/gcn3/registers.hh"
  43 #include "gpu-compute/dispatcher.hh"
  44 #include "gpu-compute/hsa_queue_entry.hh"
  45 #include "gpu-compute/misc.hh"
  46
  47 class Wavefront;
  48
  49 namespace Gcn3ISA
  50 {
  51     class GPUISA
  52     {
  53       public:
  54         GPUISA(Wavefront &wf);
  55
  56         template<typename T> T
  57         readConstVal(int opIdx) const
  58         {
  59             panic_if(!std::is_integral<T>::value, "Constant values must "
  60                      "be an integer.\n");
  61             T val(0);
  62
  63             if (isPosConstVal(opIdx)) {
  64                 val = (T)readPosConstReg(opIdx);
  65             }
  66
  67             if (isNegConstVal(opIdx)) {
  68                 val = (T)readNegConstReg(opIdx);
  69             }
  70
  71             return val;
  72         }
  73
  74         ScalarRegU32 readMiscReg(int opIdx) const;
  75         void writeMiscReg(int opIdx, ScalarRegU32 operandVal);
  76         bool hasScalarUnit() const { return true; }
  77         void advancePC(GPUDynInstPtr gpuDynInst);
  78
  79       private:
  80         ScalarRegU32 readPosConstReg(int opIdx) const
  81         {
  82             return posConstRegs[opIdx - REG_INT_CONST_POS_MIN];
  83         }
  84
  85         ScalarRegI32 readNegConstReg(int opIdx) const
  86         {
  87             return negConstRegs[opIdx - REG_INT_CONST_NEG_MIN];
  88         }
  89
  90         static const std::array<const ScalarRegU32, NumPosConstRegs>
  91             posConstRegs;
  92         static const std::array<const ScalarRegI32, NumNegConstRegs>
  93             negConstRegs;
  94
  95         // parent wavefront
  96         Wavefront &wavefront;
  97
  98         // shader status bits
  99         StatusReg statusReg;
 100         // memory descriptor reg
 101         ScalarRegU32 m0;
 102     };
 103 } // namespace Gcn3ISA
 104
 105 #endif // __ARCH_GCN3_GPU_ISA_HH__