src/arch/gcn3/isa.cc

   1 /*
   2  * Copyright (c) 2016-2018 Advanced Micro Devices, Inc.
   3  * All rights reserved.
   4  *
   5  * For use for simulation and test purposes only
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  * this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright notice,
  14  * this list of conditions and the following disclaimer in the documentation
  15  * and/or other materials provided with the distribution.
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  * contributors may be used to endorse or promote products derived from this
  19  * software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * Authors: Anthony Gutierrez
  34  */
  35
  36 #include "arch/gcn3/gpu_isa.hh"
  37
  38 #include <numeric>
  39
  40 #include "gpu-compute/gpu_static_inst.hh"
  41 #include "gpu-compute/wavefront.hh"
  42
  43 namespace Gcn3ISA
  44 {
  45     GPUISA::GPUISA(Wavefront &wf) : wavefront(wf), m0(0)
  46     {
  47     }
  48
  49     ScalarRegU32
  50     GPUISA::readMiscReg(int opIdx) const
  51     {
  52         switch (opIdx) {
  53           case REG_M0:
  54             return m0;
  55           case REG_ZERO:
  56             return 0;
  57           case REG_SCC:
  58             return statusReg.SCC;
  59           default:
  60             fatal("attempting to read from unsupported or non-readable "
  61                   "register. selector val: %i\n", opIdx);
  62             return 0;
  63         }
  64     }
  65
  66     void
  67     GPUISA::writeMiscReg(int opIdx, ScalarRegU32 operandVal)
  68     {
  69         switch (opIdx) {
  70           case REG_M0:
  71             m0 = operandVal;
  72             break;
  73           case REG_SCC:
  74             statusReg.SCC = operandVal ? 1 : 0;
  75             break;
  76           default:
  77             fatal("attempting to write to an unsupported or non-writable "
  78                   "register. selector val: %i\n", opIdx);
  79             break;
  80         }
  81     }
  82
  83     void
  84     GPUISA::advancePC(GPUDynInstPtr gpuDynInst)
  85     {
  86         wavefront.pc(wavefront.pc()
  87                      + gpuDynInst->staticInstruction()->instSize());
  88     }
  89
  90     const std::array<const ScalarRegU32, NumPosConstRegs>
  91         GPUISA::posConstRegs = { {
  92             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
  93             20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
  94             37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
  95             54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
  96         } };
  97
  98     const std::array<const ScalarRegI32, NumNegConstRegs>
  99         GPUISA::negConstRegs = { {
 100             -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15,
 101             -16
 102         } };
 103 } // namespace Gcn3ISA