src/arch/gcn3/registers.cc

   1 /*
   2  * Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
   3  * All rights reserved.
   4  *
   5  * For use for simulation and test purposes only
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  * this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright notice,
  14  * this list of conditions and the following disclaimer in the documentation
  15  * and/or other materials provided with the distribution.
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  * contributors may be used to endorse or promote products derived from this
  19  * software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * Authors: Anthony Gutierrez
  34  */
  35
  36 #include "arch/gcn3/registers.hh"
  37
  38 namespace Gcn3ISA
  39 {
  40     std::string
  41     opSelectorToRegSym(int idx, int numRegs)
  42     {
  43         std::string reg_sym;
  44
  45         // we have an SGPR
  46         if (idx <= REG_SGPR_MAX) {
  47             if (numRegs > 1)
  48                 reg_sym = "s[" + std::to_string(idx) + ":" +
  49                     std::to_string(idx + numRegs - 1) + "]";
  50             else
  51                 reg_sym = "s" + std::to_string(idx);
  52             return reg_sym;
  53         } else if (idx >= REG_VGPR_MIN && idx <= REG_VGPR_MAX) {
  54             if (numRegs > 1)
  55                 reg_sym = "v[" + std::to_string(idx - REG_VGPR_MIN) + ":" +
  56                     std::to_string(idx - REG_VGPR_MIN + numRegs - 1) + "]";
  57             else
  58                 reg_sym = "v" + std::to_string(idx - REG_VGPR_MIN);
  59             return reg_sym;
  60         } else if (idx >= REG_INT_CONST_POS_MIN &&
  61                    idx <= REG_INT_CONST_POS_MAX) {
  62             reg_sym = std::to_string(idx - REG_INT_CONST_POS_MIN + 1);
  63             return reg_sym;
  64         } else if (idx >= REG_INT_CONST_NEG_MIN &&
  65                    idx <= REG_INT_CONST_NEG_MAX) {
  66             int inline_val = -1 - (idx - REG_INT_CONST_NEG_MIN);
  67             reg_sym = std::to_string(inline_val);
  68             return reg_sym;
  69         }
  70
  71         switch (idx) {
  72           case REG_FLAT_SCRATCH_LO:
  73             reg_sym = "flat_scratch_lo";
  74             break;
  75           case REG_FLAT_SCRATCH_HI:
  76             reg_sym = "flat_scratch_hi";
  77             break;
  78           case REG_VCC_LO:
  79             reg_sym = "vcc";
  80             break;
  81           case REG_M0:
  82             reg_sym = "m0";
  83             break;
  84           case REG_EXEC_LO:
  85             reg_sym = "exec";
  86             break;
  87           case REG_ZERO:
  88             reg_sym = "0";
  89             break;
  90           case REG_POS_HALF:
  91             reg_sym = "0.5";
  92             break;
  93           case REG_NEG_HALF:
  94             reg_sym = "-0.5";
  95             break;
  96           case REG_POS_ONE:
  97             reg_sym = "1";
  98             break;
  99           case REG_NEG_ONE:
 100             reg_sym = "-1";
 101             break;
 102           case REG_POS_TWO:
 103             reg_sym = "2";
 104             break;
 105           case REG_NEG_TWO:
 106             reg_sym = "-2";
 107             break;
 108           case REG_POS_FOUR:
 109             reg_sym = "4";
 110             break;
 111           case REG_NEG_FOUR:
 112             reg_sym = "-4";
 113             break;
 114           default:
 115             fatal("GCN3 ISA instruction has unknown register index %u\n", idx);
 116             break;
 117         }
 118
 119         return reg_sym;
 120     }
 121
 122     int
 123     opSelectorToRegIdx(int idx, int numScalarRegs)
 124     {
 125         int regIdx = -1;
 126
 127         if (idx <= REG_SGPR_MAX) {
 128             regIdx = idx;
 129         } else if (idx >= REG_VGPR_MIN && idx <= REG_VGPR_MAX) {
 130             regIdx = idx - REG_VGPR_MIN;
 131         } else if (idx == REG_VCC_LO) {
 132             /**
 133              * the VCC register occupies the two highest numbered
 134              * SRF entries. VCC is typically indexed by specifying
 135              * VCC_LO (simply called VCC) in the instruction encoding
 136              * and reading it as a 64b value so we only return the
 137              * index to the lower half of the VCC register.
 138              *
 139              * VCC_LO = s[NUM_SGPRS - 2]
 140              * VCC_HI = s[NUM_SGPRS - 1]
 141              *
 142              */
 143             regIdx = numScalarRegs - 2;
 144         } else if (idx == REG_VCC_HI) {
 145             regIdx = numScalarRegs - 1;
 146         } else if (idx == REG_FLAT_SCRATCH_LO) {
 147             /**
 148              * the FLAT_SCRATCH register occupies the two SRF entries
 149              * just below VCC. FLAT_SCRATCH is typically indexed by
 150              * specifying FLAT_SCRATCH_LO (simply called FLAT_SCRATCH)
 151              * in the instruction encoding and reading it as a 64b value
 152              * so we only return the index to the lower half of the
 153              * FLAT_SCRATCH register.
 154              *
 155              * FLAT_SCRATCH_LO = s[NUM_SGPRS - 4]
 156              * FLAT_SCRATCH_HI = s[NUM_SGPRS - 3]
 157              *
 158              */
 159             regIdx = numScalarRegs - 4;
 160         } else if (idx == REG_FLAT_SCRATCH_HI) {
 161             regIdx = numScalarRegs - 3;
 162         }
 163
 164         return regIdx;
 165     }
 166
 167     bool
 168     isPosConstVal(int opIdx)
 169     {
 170         bool is_pos_const_val = (opIdx >= REG_INT_CONST_POS_MIN
 171             && opIdx <= REG_INT_CONST_POS_MAX);
 172
 173         return is_pos_const_val;
 174     }
 175
 176     bool
 177     isNegConstVal(int opIdx)
 178     {
 179         bool is_neg_const_val = (opIdx >= REG_INT_CONST_NEG_MIN
 180             && opIdx <= REG_INT_CONST_NEG_MAX);
 181
 182         return is_neg_const_val;
 183     }
 184
 185     bool
 186     isConstVal(int opIdx)
 187     {
 188         bool is_const_val = isPosConstVal(opIdx) || isNegConstVal(opIdx);
 189         return is_const_val;
 190     }
 191
 192     bool
 193     isLiteral(int opIdx)
 194     {
 195         return opIdx == REG_SRC_LITERAL;
 196     }
 197
 198     bool
 199     isExecMask(int opIdx)
 200     {
 201         return opIdx == REG_EXEC_LO || opIdx == REG_EXEC_HI;
 202     }
 203
 204     bool
 205     isVccReg(int opIdx)
 206     {
 207         return opIdx == REG_VCC_LO || opIdx == REG_VCC_HI;
 208     }
 209
 210     bool
 211     isFlatScratchReg(int opIdx)
 212     {
 213         return opIdx == REG_FLAT_SCRATCH_LO || opIdx == REG_FLAT_SCRATCH_HI;
 214     }
 215
 216     bool
 217     isScalarReg(int opIdx)
 218     {
 219         // FLAT_SCRATCH and VCC are stored in an SGPR pair
 220         if (opIdx <= REG_SGPR_MAX || opIdx == REG_FLAT_SCRATCH_LO ||
 221             opIdx == REG_FLAT_SCRATCH_HI || opIdx == REG_VCC_LO ||
 222             opIdx == REG_VCC_HI) {
 223             return true;
 224         }
 225
 226         return false;
 227     }
 228
 229     bool
 230     isVectorReg(int opIdx)
 231     {
 232         if (opIdx >= REG_VGPR_MIN && opIdx <= REG_VGPR_MAX)
 233             return true;
 234
 235         return false;
 236     }
 237
 238 } // namespace Gcn3ISA