src/arch/gcn3/registers.hh

   1 /*
   2  * Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
   3  * All rights reserved.
   4  *
   5  * For use for simulation and test purposes only
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  * this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright notice,
  14  * this list of conditions and the following disclaimer in the documentation
  15  * and/or other materials provided with the distribution.
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  * contributors may be used to endorse or promote products derived from this
  19  * software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * Authors: Anthony Gutierrez
  34  */
  35
  36 #ifndef __ARCH_GCN3_REGISTERS_HH__
  37 #define __ARCH_GCN3_REGISTERS_HH__
  38
  39 #include <array>
  40 #include <cstdint>
  41 #include <string>
  42
  43 #include "arch/generic/vec_reg.hh"
  44 #include "base/intmath.hh"
  45 #include "base/logging.hh"
  46
  47 namespace Gcn3ISA
  48 {
  49     enum OpSelector : int
  50     {
  51         REG_SGPR_MIN = 0,
  52         REG_SGPR_MAX = 101,
  53         REG_FLAT_SCRATCH_LO = 102,
  54         REG_FLAT_SCRATCH_HI = 103,
  55         REG_XNACK_MASK_LO = 104,
  56         REG_XNACK_MASK_HI = 105,
  57         REG_VCC_LO = 106,
  58         REG_VCC_HI = 107,
  59         REG_TBA_LO = 108,
  60         REG_TBA_HI = 109,
  61         REG_TMA_LO = 110,
  62         REG_TMA_HI = 111,
  63         REG_TTMP_0 = 112,
  64         REG_TTMP_1 = 113,
  65         REG_TTMP_2 = 114,
  66         REG_TTMP_3 = 115,
  67         REG_TTMP_4 = 116,
  68         REG_TTMP_5 = 117,
  69         REG_TTMP_6 = 118,
  70         REG_TTMP_7 = 119,
  71         REG_TTMP_8 = 120,
  72         REG_TTMP_9 = 121,
  73         REG_TTMP_10 = 122,
  74         REG_TTMP_11 = 123,
  75         REG_M0 = 124,
  76         REG_RESERVED_1 = 125,
  77         REG_EXEC_LO = 126,
  78         REG_EXEC_HI = 127,
  79         REG_ZERO = 128,
  80         REG_INT_CONST_POS_MIN = 129,
  81         REG_INT_CONST_POS_MAX = 192,
  82         REG_INT_CONST_NEG_MIN = 193,
  83         REG_INT_CONST_NEG_MAX = 208,
  84         REG_RESERVED_2 = 209,
  85         REG_RESERVED_3 = 210,
  86         REG_RESERVED_4 = 211,
  87         REG_RESERVED_5 = 212,
  88         REG_RESERVED_6 = 213,
  89         REG_RESERVED_7 = 214,
  90         REG_RESERVED_8 = 215,
  91         REG_RESERVED_9 = 216,
  92         REG_RESERVED_10 = 217,
  93         REG_RESERVED_11 = 218,
  94         REG_RESERVED_12 = 219,
  95         REG_RESERVED_13 = 220,
  96         REG_RESERVED_14 = 221,
  97         REG_RESERVED_15 = 222,
  98         REG_RESERVED_16 = 223,
  99         REG_RESERVED_17 = 224,
 100         REG_RESERVED_18 = 225,
 101         REG_RESERVED_19 = 226,
 102         REG_RESERVED_20 = 227,
 103         REG_RESERVED_21 = 228,
 104         REG_RESERVED_22 = 229,
 105         REG_RESERVED_23 = 230,
 106         REG_RESERVED_24 = 231,
 107         REG_RESERVED_25 = 232,
 108         REG_RESERVED_26 = 233,
 109         REG_RESERVED_27 = 234,
 110         REG_RESERVED_28 = 235,
 111         REG_RESERVED_29 = 236,
 112         REG_RESERVED_30 = 237,
 113         REG_RESERVED_31 = 238,
 114         REG_RESERVED_32 = 239,
 115         REG_POS_HALF = 240,
 116         REG_NEG_HALF = 241,
 117         REG_POS_ONE = 242,
 118         REG_NEG_ONE = 243,
 119         REG_POS_TWO = 244,
 120         REG_NEG_TWO = 245,
 121         REG_POS_FOUR = 246,
 122         REG_NEG_FOUR = 247,
 123         REG_PI = 248,
 124         /* NOTE: SDWA and SWDA both refer to sub d-word addressing */
 125         REG_SRC_SWDA = 249,
 126         REG_SRC_DPP = 250,
 127         REG_VCCZ = 251,
 128         REG_EXECZ = 252,
 129         REG_SCC = 253,
 130         REG_LDS_DIRECT = 254,
 131         REG_SRC_LITERAL = 255,
 132         REG_VGPR_MIN = 256,
 133         REG_VGPR_MAX = 511
 134     };
 135
 136     constexpr size_t MaxOperandDwords(16);
 137     const int NumVecElemPerVecReg(64);
 138     // op selector values 129 - 192 correspond to const values 1 - 64
 139     const int NumPosConstRegs = REG_INT_CONST_POS_MAX
 140         - REG_INT_CONST_POS_MIN + 1;
 141     // op selector values 193 - 208 correspond to const values -1 - 16
 142     const int NumNegConstRegs = REG_INT_CONST_NEG_MAX
 143         - REG_INT_CONST_NEG_MIN + 1;
 144     const int BITS_PER_BYTE = 8;
 145     const int BITS_PER_WORD = 16;
 146     const int MSB_PER_BYTE = (BITS_PER_BYTE - 1);
 147     const int MSB_PER_WORD = (BITS_PER_WORD - 1);
 148
 149     // typedefs for the various sizes/types of scalar regs
 150     typedef uint8_t ScalarRegU8;
 151     typedef int8_t ScalarRegI8;
 152     typedef uint16_t ScalarRegU16;
 153     typedef int16_t ScalarRegI16;
 154     typedef uint32_t ScalarRegU32;
 155     typedef int32_t ScalarRegI32;
 156     typedef float ScalarRegF32;
 157     typedef uint64_t ScalarRegU64;
 158     typedef int64_t ScalarRegI64;
 159     typedef double ScalarRegF64;
 160
 161     // typedefs for the various sizes/types of vector reg elements
 162     typedef uint8_t VecElemU8;
 163     typedef int8_t VecElemI8;
 164     typedef uint16_t VecElemU16;
 165     typedef int16_t VecElemI16;
 166     typedef uint32_t VecElemU32;
 167     typedef int32_t VecElemI32;
 168     typedef float VecElemF32;
 169     typedef uint64_t VecElemU64;
 170     typedef int64_t VecElemI64;
 171     typedef double VecElemF64;
 172
 173     // typedefs for the various sizes/types of vector regs
 174     using VecRegU8 = ::VecRegT<VecElemU8, NumVecElemPerVecReg, false>;
 175     using VecRegI8 = ::VecRegT<VecElemI8, NumVecElemPerVecReg, false>;
 176     using VecRegU16 = ::VecRegT<VecElemU16, NumVecElemPerVecReg, false>;
 177     using VecRegI16 = ::VecRegT<VecElemI16, NumVecElemPerVecReg, false>;
 178     using VecRegU32 = ::VecRegT<VecElemU32, NumVecElemPerVecReg, false>;
 179     using VecRegI32 = ::VecRegT<VecElemI32, NumVecElemPerVecReg, false>;
 180     using VecRegF32 = ::VecRegT<VecElemF32, NumVecElemPerVecReg, false>;
 181     using VecRegU64 = ::VecRegT<VecElemU64, NumVecElemPerVecReg, false>;
 182     using VecRegI64 = ::VecRegT<VecElemI64, NumVecElemPerVecReg, false>;
 183     using VecRegF64 = ::VecRegT<VecElemF64, NumVecElemPerVecReg, false>;
 184     // non-writeable versions of vector regs
 185     using ConstVecRegU8 = ::VecRegT<VecElemU8, NumVecElemPerVecReg, true>;
 186     using ConstVecRegI8 = ::VecRegT<VecElemI8, NumVecElemPerVecReg, true>;
 187     using ConstVecRegU16 = ::VecRegT<VecElemU16, NumVecElemPerVecReg, true>;
 188     using ConstVecRegI16 = ::VecRegT<VecElemI16, NumVecElemPerVecReg, true>;
 189     using ConstVecRegU32 = ::VecRegT<VecElemU32, NumVecElemPerVecReg, true>;
 190     using ConstVecRegI32 = ::VecRegT<VecElemI32, NumVecElemPerVecReg, true>;
 191     using ConstVecRegF32 = ::VecRegT<VecElemF32, NumVecElemPerVecReg, true>;
 192     using ConstVecRegU64 = ::VecRegT<VecElemU64, NumVecElemPerVecReg, true>;
 193     using ConstVecRegI64 = ::VecRegT<VecElemI64, NumVecElemPerVecReg, true>;
 194     using ConstVecRegF64 = ::VecRegT<VecElemF64, NumVecElemPerVecReg, true>;
 195
 196     using VecRegContainerU8 = VecRegU8::Container;
 197     using VecRegContainerU16 = VecRegU16::Container;
 198     using VecRegContainerU32 = VecRegU32::Container;
 199     using VecRegContainerU64 = VecRegU64::Container;
 200
 201     struct StatusReg
 202     {
 203         StatusReg() : SCC(0), SPI_PRIO(0), USER_PRIO(0), PRIV(0), TRAP_EN(0),
 204             TTRACE_EN(0), EXPORT_RDY(0), EXECZ(0), VCCZ(0), IN_TG(0),
 205             IN_BARRIER(0), HALT(0), TRAP(0), TTRACE_CU_EN(0), VALID(0),
 206             ECC_ERR(0), SKIP_EXPORT(0), PERF_EN(0), COND_DBG_USER(0),
 207             COND_DBG_SYS(0), ALLOW_REPLAY(0), INSTRUCTION_ATC(0), RESERVED(0),
 208             MUST_EXPORT(0), RESERVED_1(0)
 209         {
 210         }
 211
 212         uint32_t SCC : 1;
 213         uint32_t SPI_PRIO : 2;
 214         uint32_t USER_PRIO : 2;
 215         uint32_t PRIV : 1;
 216         uint32_t TRAP_EN : 1;
 217         uint32_t TTRACE_EN : 1;
 218         uint32_t EXPORT_RDY : 1;
 219         uint32_t EXECZ : 1;
 220         uint32_t VCCZ : 1;
 221         uint32_t IN_TG : 1;
 222         uint32_t IN_BARRIER : 1;
 223         uint32_t HALT : 1;
 224         uint32_t TRAP : 1;
 225         uint32_t TTRACE_CU_EN : 1;
 226         uint32_t VALID : 1;
 227         uint32_t ECC_ERR : 1;
 228         uint32_t SKIP_EXPORT : 1;
 229         uint32_t PERF_EN : 1;
 230         uint32_t COND_DBG_USER : 1;
 231         uint32_t COND_DBG_SYS : 1;
 232         uint32_t ALLOW_REPLAY : 1;
 233         uint32_t INSTRUCTION_ATC : 1;
 234         uint32_t RESERVED : 3;
 235         uint32_t MUST_EXPORT : 1;
 236         uint32_t RESERVED_1 : 4;
 237     };
 238
 239     std::string opSelectorToRegSym(int opIdx, int numRegs=0);
 240     int opSelectorToRegIdx(int opIdx, int numScalarRegs);
 241     bool isPosConstVal(int opIdx);
 242     bool isNegConstVal(int opIdx);
 243     bool isConstVal(int opIdx);
 244     bool isLiteral(int opIdx);
 245     bool isScalarReg(int opIdx);
 246     bool isVectorReg(int opIdx);
 247     bool isFlatScratchReg(int opIdx);
 248     bool isExecMask(int opIdx);
 249     bool isVccReg(int opIdx);
 250 } // namespace Gcn3ISA
 251
 252 #endif // __ARCH_GCN3_REGISTERS_HH__