src/arch/generic/memhelpers.hh

   1 /*
   2  * Copyright (c) 2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2011 Google
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Gabe Black
  41  */
  42
  43 #ifndef __ARCH_GENERIC_MEMHELPERS_HH__
  44 #define __ARCH_GENERIC_MEMHELPERS_HH__
  45
  46 #include "arch/isa_traits.hh"
  47 #include "base/types.hh"
  48 #include "mem/packet.hh"
  49 #include "mem/request.hh"
  50 #include "sim/byteswap.hh"
  51 #include "sim/insttracer.hh"
  52
  53 /// Initiate a read from memory in timing mode.  Note that the 'mem'
  54 /// parameter is unused; only the type of that parameter is used
  55 /// to determine the size of the access.
  56 template <class XC, class MemT>
  57 Fault
  58 initiateMemRead(XC *xc, Trace::InstRecord *traceData, Addr addr,
  59                 MemT &mem, Request::Flags flags)
  60 {
  61     return xc->initiateMemRead(addr, sizeof(MemT), flags);
  62 }
  63
  64 /// Extract the data returned from a timing mode read.
  65 template <class MemT>
  66 void
  67 getMem(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData)
  68 {
  69     mem = pkt->get<MemT>();
  70     if (traceData)
  71         traceData->setData(mem);
  72 }
  73
  74 /// Read from memory in atomic mode.
  75 template <class XC, class MemT>
  76 Fault
  77 readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
  78               Request::Flags flags)
  79 {
  80     memset(&mem, 0, sizeof(mem));
  81     Fault fault = xc->readMem(addr, (uint8_t *)&mem, sizeof(MemT), flags);
  82     if (fault == NoFault) {
  83         mem = TheISA::gtoh(mem);
  84         if (traceData)
  85             traceData->setData(mem);
  86     }
  87     return fault;
  88 }
  89
  90 /// Write to memory in timing mode.
  91 template <class XC, class MemT>
  92 Fault
  93 writeMemTiming(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr,
  94                Request::Flags flags, uint64_t *res)
  95 {
  96     if (traceData) {
  97         traceData->setData(mem);
  98     }
  99     mem = TheISA::htog(mem);
 100     return xc->writeMem((uint8_t *)&mem, sizeof(MemT), addr, flags, res);
 101 }
 102
 103 /// Write to memory in atomic mode.
 104 template <class XC, class MemT>
 105 Fault
 106 writeMemAtomic(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
 107                Addr addr, Request::Flags flags, uint64_t *res)
 108 {
 109     if (traceData) {
 110         traceData->setData(mem);
 111     }
 112     MemT host_mem = TheISA::htog(mem);
 113     Fault fault =
 114           xc->writeMem((uint8_t *)&host_mem, sizeof(MemT), addr, flags, res);
 115     if (fault == NoFault && res != NULL) {
 116         if (flags & Request::MEM_SWAP || flags & Request::MEM_SWAP_COND)
 117             *res = TheISA::gtoh((MemT)*res);
 118         else
 119             *res = TheISA::gtoh(*res);
 120     }
 121     return fault;
 122 }
 123
 124 #endif