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43 #ifndef __ARCH_GENERIC_TLB_HH__
44 #define __ARCH_GENERIC_TLB_HH__
46 #include "base/misc.hh"
47 #include "mem/request.hh"
48 #include "sim/sim_object.hh"
53 class BaseTLB : public SimObject
56 BaseTLB(const Params *p)
61 enum Mode { Read, Write, Execute };
64 virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
67 * Remove all entries from the TLB
69 virtual void flushAll() = 0;
72 * Take over from an old tlb context
74 virtual void takeOverFrom(BaseTLB *otlb) = 0;
77 * Get the table walker master port if present. This is used for
78 * migrating port connections during a CPU takeOverFrom()
79 * call. For architectures that do not have a table walker, NULL
80 * is returned, hence the use of a pointer rather than a
83 * @return A pointer to the walker master port or NULL if not present
85 virtual BaseMasterPort* getMasterPort() { return NULL; }
87 void memInvalidate() { flushAll(); }
92 virtual ~Translation()
96 * Signal that the translation has been delayed due to a hw page table
99 virtual void markDelayed() = 0;
102 * The memory for this object may be dynamically allocated, and it may
103 * be responsible for cleaning itself up which will happen in this
104 * function. Once it's called, the object is no longer valid.
106 virtual void finish(const Fault &fault, RequestPtr req,
107 ThreadContext *tc, Mode mode) = 0;
109 /** This function is used by the page table walker to determine if it
110 * should translate the a pending request or if the underlying request
112 * @ return Is the instruction that requested this translation squashed?
114 virtual bool squashed() const { return false; }
118 class GenericTLB : public BaseTLB
121 GenericTLB(const Params *p)
126 void demapPage(Addr vaddr, uint64_t asn) override;
128 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
129 void translateTiming(RequestPtr req, ThreadContext *tc,
130 Translation *translation, Mode mode);
134 * Do post-translation physical address finalization.
136 * This method is used by some architectures that need
137 * post-translation massaging of physical addresses. For example,
138 * X86 uses this to remap physical addresses in the APIC range to
139 * a range of physical memory not normally available to real x86
142 * @param req Request to updated in-place.
143 * @param tc Thread context that created the request.
144 * @param mode Request type (read/write/execute).
145 * @return A fault on failure, NoFault otherwise.
147 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
150 #endif // __ARCH_GENERIC_TLB_HH__