src/arch/mips/dsp.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __ARCH_MIPS_DSP_HH__
  30 #define __ARCH_MIPS_DSP_HH__
  31
  32 #include "arch/mips/isa_traits.hh"
  33 #include "arch/mips/types.hh"
  34 #include "base/logging.hh"
  35 #include "base/types.hh"
  36
  37 class ThreadContext;
  38
  39 namespace MipsISA {
  40
  41 // SIMD formats
  42 enum {
  43     SIMD_FMT_L,    // long word
  44     SIMD_FMT_W,    // word
  45     SIMD_FMT_PH,   // paired halfword
  46     SIMD_FMT_QB,   // quad byte
  47     SIMD_NUM_FMTS
  48 };
  49
  50 // DSPControl Fields
  51 enum {
  52     DSP_POS,       // insertion bitfield position
  53     DSP_SCOUNT,    // insertion bitfield size
  54     DSP_C,         // carry bit
  55     DSP_OUFLAG,    // overflow-underflow flag
  56     DSP_CCOND,     // condition code
  57     DSP_EFI,       // extract fail indicator bit
  58     DSP_NUM_FIELDS
  59 };
  60
  61 // compare instruction operations
  62 enum {
  63     CMP_EQ,        // equal
  64     CMP_LT,        // less than
  65     CMP_LE         // less than or equal
  66 };
  67
  68 // SIMD operation order modes
  69 enum {
  70     MODE_L,        // left
  71     MODE_R,        // right
  72     MODE_LA,       // left-alternate
  73     MODE_RA,       // right-alternate
  74     MODE_X         // cross
  75 };
  76
  77 // dsp operation parameters
  78 enum { UNSIGNED, SIGNED };
  79 enum { NOSATURATE, SATURATE };
  80 enum { NOROUND, ROUND };
  81
  82 // DSPControl field positions and masks
  83 const uint32_t DSP_CTL_POS[DSP_NUM_FIELDS] = { 0, 7, 13, 16, 24, 14 };
  84 const uint32_t DSP_CTL_MASK[DSP_NUM_FIELDS] =
  85 { 0x0000003f, 0x00001f80, 0x00002000,
  86   0x00ff0000, 0x0f000000, 0x00004000 };
  87
  88 /*
  89  * SIMD format constants
  90  */
  91
  92 // maximum values per register
  93 const uint32_t SIMD_MAX_VALS = 4;
  94 // number of values in fmt
  95 const uint32_t SIMD_NVALS[SIMD_NUM_FMTS] = { 1, 1, 2, 4 };
  96 // number of bits per value
  97 const uint32_t SIMD_NBITS[SIMD_NUM_FMTS] = { 64, 32, 16, 8 };
  98 // log2(bits per value)
  99 const uint32_t SIMD_LOG2N[SIMD_NUM_FMTS] = { 6, 5, 4, 3 };
 100
 101
 102 // DSP maximum values
 103 const uint64_t FIXED_L_SMAX = ULL(0x7fffffffffffffff);
 104 const uint64_t FIXED_W_SMAX = ULL(0x000000007fffffff);
 105 const uint64_t FIXED_H_SMAX = ULL(0x0000000000007fff);
 106 const uint64_t FIXED_B_SMAX = ULL(0x000000000000007f);
 107 const uint64_t FIXED_L_UMAX = ULL(0xffffffffffffffff);
 108 const uint64_t FIXED_W_UMAX = ULL(0x00000000ffffffff);
 109 const uint64_t FIXED_H_UMAX = ULL(0x000000000000ffff);
 110 const uint64_t FIXED_B_UMAX = ULL(0x00000000000000ff);
 111 const uint64_t FIXED_SMAX[SIMD_NUM_FMTS] =
 112 { FIXED_L_SMAX, FIXED_W_SMAX, FIXED_H_SMAX, FIXED_B_SMAX };
 113 const uint64_t FIXED_UMAX[SIMD_NUM_FMTS] =
 114 { FIXED_L_UMAX, FIXED_W_UMAX, FIXED_H_UMAX, FIXED_B_UMAX };
 115
 116 // DSP minimum values
 117 const uint64_t FIXED_L_SMIN = ULL(0x8000000000000000);
 118 const uint64_t FIXED_W_SMIN = ULL(0xffffffff80000000);
 119 const uint64_t FIXED_H_SMIN = ULL(0xffffffffffff8000);
 120 const uint64_t FIXED_B_SMIN = ULL(0xffffffffffffff80);
 121 const uint64_t FIXED_L_UMIN = ULL(0x0000000000000000);
 122 const uint64_t FIXED_W_UMIN = ULL(0x0000000000000000);
 123 const uint64_t FIXED_H_UMIN = ULL(0x0000000000000000);
 124 const uint64_t FIXED_B_UMIN = ULL(0x0000000000000000);
 125 const uint64_t FIXED_SMIN[SIMD_NUM_FMTS] =
 126 { FIXED_L_SMIN, FIXED_W_SMIN, FIXED_H_SMIN, FIXED_B_SMIN };
 127 const uint64_t FIXED_UMIN[SIMD_NUM_FMTS] =
 128 { FIXED_L_UMIN, FIXED_W_UMIN, FIXED_H_UMIN, FIXED_B_UMIN };
 129
 130 // DSP utility functions
 131 int32_t bitrev(int32_t value);
 132 uint64_t dspSaturate(uint64_t value, int32_t fmt, int32_t sign,
 133                      uint32_t *overflow);
 134 uint64_t checkOverflow(uint64_t value, int32_t fmt, int32_t sign,
 135                        uint32_t *overflow);
 136 uint64_t signExtend(uint64_t value, int32_t signpos);
 137 uint64_t addHalfLsb(uint64_t value, int32_t lsbpos);
 138 int32_t dspAbs(int32_t a, int32_t fmt, uint32_t *dspctl);
 139 int32_t dspAdd(int32_t a, int32_t b, int32_t fmt, int32_t saturate,
 140                int32_t sign, uint32_t *dspctl);
 141 int32_t dspAddh(int32_t a, int32_t b, int32_t fmt, int32_t round,
 142                 int32_t sign);
 143 int32_t dspSub(int32_t a, int32_t b, int32_t fmt, int32_t saturate,
 144                int32_t sign, uint32_t *dspctl);
 145 int32_t dspSubh(int32_t a, int32_t b, int32_t fmt, int32_t round,
 146                 int32_t sign);
 147 int32_t dspShll(int32_t a, uint32_t sa, int32_t fmt, int32_t saturate,
 148                 int32_t sign, uint32_t *dspctl);
 149 int32_t dspShrl(int32_t a, uint32_t sa, int32_t fmt, int32_t sign);
 150 int32_t dspShra(int32_t a, uint32_t sa, int32_t fmt, int32_t round,
 151                 int32_t sign, uint32_t *dspctl);
 152 int32_t dspMul(int32_t a, int32_t b, int32_t fmt, int32_t saturate,
 153                uint32_t *dspctl);
 154 int32_t dspMulq(int32_t a, int32_t b, int32_t fmt, int32_t saturate,
 155                 int32_t round, uint32_t *dspctl);
 156 int32_t dspMuleu(int32_t a, int32_t b, int32_t mode, uint32_t *dspctl);
 157 int32_t dspMuleq(int32_t a, int32_t b, int32_t mode, uint32_t *dspctl);
 158 int64_t dspDpaq(int64_t dspac, int32_t a, int32_t b, int32_t ac,
 159                 int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode,
 160                 uint32_t *dspctl);
 161 int64_t dspDpsq(int64_t dspac, int32_t a, int32_t b, int32_t ac,
 162                 int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode,
 163                 uint32_t *dspctl);
 164 int64_t dspDpa(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt,
 165                int32_t sign, int32_t mode);
 166 int64_t dspDps(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt,
 167                int32_t sign, int32_t mode);
 168 int64_t dspMaq(int64_t dspac, int32_t a, int32_t b, int32_t ac,
 169                int32_t fmt, int32_t mode, int32_t saturate, uint32_t *dspctl);
 170 int64_t dspMulsa(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt);
 171 int64_t dspMulsaq(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt,
 172                   uint32_t *dspctl);
 173 void dspCmp(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op,
 174             uint32_t *dspctl);
 175 int32_t dspCmpg(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op);
 176 int32_t dspCmpgd(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op,
 177                  uint32_t *dspctl);
 178 int32_t dspPrece(int32_t a, int32_t infmt, int32_t insign, int32_t outfmt,
 179                  int32_t outsign, int32_t mode);
 180 int32_t dspPrecrqu(int32_t a, int32_t b, uint32_t *dspctl);
 181 int32_t dspPrecrq(int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl);
 182 int32_t dspPrecrSra(int32_t a, int32_t b, int32_t sa, int32_t fmt,
 183                     int32_t round);
 184 int32_t dspPick(int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl);
 185 int32_t dspPack(int32_t a, int32_t b, int32_t fmt);
 186 int32_t dspExtr(int64_t dspac, int32_t fmt, int32_t sa, int32_t round,
 187                 int32_t saturate, uint32_t *dspctl);
 188 int32_t dspExtp(int64_t dspac, int32_t size, uint32_t *dspctl);
 189 int32_t dspExtpd(int64_t dspac, int32_t size, uint32_t *dspctl);
 190
 191 // SIMD pack/unpack utility functions
 192 void simdPack(uint64_t *values_ptr, int32_t *reg, int32_t fmt);
 193 void simdUnpack(int32_t reg, uint64_t *values_ptr, int32_t fmt, int32_t sign);
 194
 195 // DSPControl r/w utility functions
 196 void writeDSPControl(uint32_t *dspctl, uint32_t value, uint32_t mask);
 197 uint32_t readDSPControl(uint32_t *dspctl, uint32_t mask);
 198
 199 } // namespace MipsISA
 200
 201 #endif // __ARCH_MIPS_DSP_HH__