src/arch/mips/faults.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include "arch/mips/faults.hh"
  30 #include "cpu/exec_context.hh"
  31 #include "cpu/base.hh"
  32 #include "base/trace.hh"
  33
  34 namespace MipsISA
  35 {
  36
  37 FaultName MachineCheckFault::_name = "Machine Check";
  38 FaultVect MachineCheckFault::_vect = 0x0401;
  39 FaultStat MachineCheckFault::_count;
  40
  41 FaultName AlignmentFault::_name = "Alignment";
  42 FaultVect AlignmentFault::_vect = 0x0301;
  43 FaultStat AlignmentFault::_count;
  44
  45 FaultName ResetFault::_name = "reset";
  46 FaultVect ResetFault::_vect = 0x0001;
  47 FaultStat ResetFault::_count;
  48
  49 FaultName ArithmeticFault::_name = "arith";
  50 FaultVect ArithmeticFault::_vect = 0x0501;
  51 FaultStat ArithmeticFault::_count;
  52
  53 FaultName InterruptFault::_name = "interrupt";
  54 FaultVect InterruptFault::_vect = 0x0101;
  55 FaultStat InterruptFault::_count;
  56
  57 FaultName NDtbMissFault::_name = "dtb_miss_single";
  58 FaultVect NDtbMissFault::_vect = 0x0201;
  59 FaultStat NDtbMissFault::_count;
  60
  61 FaultName PDtbMissFault::_name = "dtb_miss_double";
  62 FaultVect PDtbMissFault::_vect = 0x0281;
  63 FaultStat PDtbMissFault::_count;
  64
  65 FaultName DtbPageFault::_name = "dfault";
  66 FaultVect DtbPageFault::_vect = 0x0381;
  67 FaultStat DtbPageFault::_count;
  68
  69 FaultName DtbAcvFault::_name = "dfault";
  70 FaultVect DtbAcvFault::_vect = 0x0381;
  71 FaultStat DtbAcvFault::_count;
  72
  73 FaultName ItbMissFault::_name = "itbmiss";
  74 FaultVect ItbMissFault::_vect = 0x0181;
  75 FaultStat ItbMissFault::_count;
  76
  77 FaultName ItbPageFault::_name = "itbmiss";
  78 FaultVect ItbPageFault::_vect = 0x0181;
  79 FaultStat ItbPageFault::_count;
  80
  81 FaultName ItbAcvFault::_name = "iaccvio";
  82 FaultVect ItbAcvFault::_vect = 0x0081;
  83 FaultStat ItbAcvFault::_count;
  84
  85 FaultName UnimplementedOpcodeFault::_name = "opdec";
  86 FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
  87 FaultStat UnimplementedOpcodeFault::_count;
  88
  89 FaultName FloatEnableFault::_name = "fen";
  90 FaultVect FloatEnableFault::_vect = 0x0581;
  91 FaultStat FloatEnableFault::_count;
  92
  93 FaultName PalFault::_name = "pal";
  94 FaultVect PalFault::_vect = 0x2001;
  95 FaultStat PalFault::_count;
  96
  97 FaultName IntegerOverflowFault::_name = "intover";
  98 FaultVect IntegerOverflowFault::_vect = 0x0501;
  99 FaultStat IntegerOverflowFault::_count;
 100
 101 #if FULL_SYSTEM
 102
 103 void MipsFault::invoke(ExecContext * xc)
 104 {
 105     FaultBase::invoke(xc);
 106     countStat()++;
 107
 108     // exception restart address
 109     if (setRestartAddress() || !xc->inPalMode())
 110         xc->setMiscReg(MipsISA::IPR_EXC_ADDR, xc->readPC());
 111
 112     if (skipFaultingInstruction()) {
 113         // traps...  skip faulting instruction.
 114         xc->setMiscReg(MipsISA::IPR_EXC_ADDR,
 115                    xc->readMiscReg(MipsISA::IPR_EXC_ADDR) + 4);
 116     }
 117
 118     xc->setPC(xc->readMiscReg(MipsISA::IPR_PAL_BASE) + vect());
 119     xc->setNextPC(xc->readPC() + sizeof(MachInst));
 120 }
 121
 122 void ArithmeticFault::invoke(ExecContext * xc)
 123 {
 124     FaultBase::invoke(xc);
 125     panic("Arithmetic traps are unimplemented!");
 126 }
 127
 128 #endif
 129
 130 } // namespace MipsISA
 131