src/arch/mips/faults.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * Copyright (c) 2007 MIPS Technologies, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #include "arch/mips/faults.hh"
  31
  32 #include "arch/mips/pra_constants.hh"
  33 #include "base/trace.hh"
  34 #include "cpu/base.hh"
  35 #include "cpu/thread_context.hh"
  36 #include "debug/MipsPRA.hh"
  37 #include "mem/page_table.hh"
  38 #include "sim/process.hh"
  39
  40 namespace MipsISA
  41 {
  42
  43 typedef MipsFaultBase::FaultVals FaultVals;
  44
  45 template <> FaultVals MipsFault<SystemCallFault>::vals =
  46     { "Syscall", 0x180, ExcCodeSys };
  47
  48 template <> FaultVals MipsFault<ReservedInstructionFault>::vals =
  49     { "Reserved Instruction Fault", 0x180, ExcCodeRI };
  50
  51 template <> FaultVals MipsFault<ThreadFault>::vals =
  52     { "Thread Fault", 0x180, ExcCodeDummy };
  53
  54 template <> FaultVals MipsFault<IntegerOverflowFault>::vals =
  55     { "Integer Overflow Exception", 0x180, ExcCodeOv };
  56
  57 template <> FaultVals MipsFault<TrapFault>::vals =
  58     { "Trap", 0x180, ExcCodeTr };
  59
  60 template <> FaultVals MipsFault<BreakpointFault>::vals =
  61     { "Breakpoint", 0x180, ExcCodeBp };
  62
  63 template <> FaultVals MipsFault<DspStateDisabledFault>::vals =
  64     { "DSP Disabled Fault", 0x180, ExcCodeDummy };
  65
  66 template <> FaultVals MipsFault<MachineCheckFault>::vals =
  67     { "Machine Check", 0x180, ExcCodeMCheck };
  68
  69 template <> FaultVals MipsFault<ResetFault>::vals =
  70     { "Reset Fault", 0x000, ExcCodeDummy };
  71
  72 template <> FaultVals MipsFault<SoftResetFault>::vals =
  73     { "Soft Reset Fault", 0x000, ExcCodeDummy };
  74
  75 template <> FaultVals MipsFault<NonMaskableInterrupt>::vals =
  76     { "Non Maskable Interrupt", 0x000, ExcCodeDummy };
  77
  78 template <> FaultVals MipsFault<CoprocessorUnusableFault>::vals =
  79     { "Coprocessor Unusable Fault", 0x180, ExcCodeCpU };
  80
  81 template <> FaultVals MipsFault<InterruptFault>::vals =
  82     { "Interrupt", 0x000, ExcCodeInt };
  83
  84 template <> FaultVals MipsFault<AddressErrorFault>::vals =
  85     { "Address Error", 0x180, ExcCodeDummy };
  86
  87 template <> FaultVals MipsFault<TlbInvalidFault>::vals =
  88     { "Invalid TLB Entry Exception", 0x180, ExcCodeDummy };
  89
  90 template <> FaultVals MipsFault<TlbRefillFault>::vals =
  91     { "TLB Refill Exception", 0x180, ExcCodeDummy };
  92
  93 template <> MipsFaultBase::FaultVals MipsFault<TlbModifiedFault>::vals =
  94     { "TLB Modified Exception", 0x180, ExcCodeMod };
  95
  96 void
  97 MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
  98 {
  99     // modify SRS Ctl - Save CSS, put ESS into CSS
 100     StatusReg status = tc->readMiscReg(MISCREG_STATUS);
 101     if (status.exl != 1 && status.bev != 1) {
 102         // SRS Ctl is modified only if Status_EXL and Status_BEV are not set
 103         SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL);
 104         srsCtl.pss = srsCtl.css;
 105         srsCtl.css = srsCtl.ess;
 106         tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl);
 107     }
 108
 109     // set EXL bit (don't care if it is already set!)
 110     status.exl = 1;
 111     tc->setMiscRegNoEffect(MISCREG_STATUS, status);
 112
 113     // write EPC
 114     PCState pc = tc->pcState();
 115     DPRINTF(MipsPRA, "PC: %s\n", pc);
 116     bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc();
 117     tc->setMiscRegNoEffect(MISCREG_EPC,
 118             pc.pc() - (delay_slot ? sizeof(MachInst) : 0));
 119
 120     // Set Cause_EXCCODE field
 121     CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
 122     cause.excCode = excCode;
 123     cause.bd = delay_slot ? 1 : 0;
 124     cause.ce = 0;
 125     tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
 126 }
 127
 128 void
 129 MipsFaultBase::invoke(ThreadContext *tc, const StaticInstPtr &inst)
 130 {
 131     if (FullSystem) {
 132         DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
 133         setExceptionState(tc, code());
 134         tc->pcState(vect(tc));
 135     } else {
 136         panic("Fault %s encountered.\n", name());
 137     }
 138 }
 139
 140 void
 141 ResetFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
 142 {
 143     if (FullSystem) {
 144         DPRINTF(MipsPRA, "%s encountered.\n", name());
 145         /* All reset activity must be invoked from here */
 146         Addr handler = vect(tc);
 147         tc->pcState(handler);
 148         DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", handler);
 149     }
 150
 151     // Set Coprocessor 1 (Floating Point) To Usable
 152     StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
 153     status.cu.cu1 = 1;
 154     tc->setMiscReg(MISCREG_STATUS, status);
 155 }
 156
 157 void
 158 SoftResetFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
 159 {
 160     panic("Soft reset not implemented.\n");
 161 }
 162
 163 void
 164 NonMaskableInterrupt::invoke(ThreadContext *tc, const StaticInstPtr &inst)
 165 {
 166     panic("Non maskable interrupt not implemented.\n");
 167 }
 168
 169 } // namespace MipsISA
 170